radv: do not add extra SGPR when push constants are not used

This is not because the vertex stage needs some push constants
that other stages need them too. This should reduce the number
of loaded SGPRs in some situations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: change the needs_push_constants logic

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: store pipeline stages that need push constants

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: remove one useless check in ac_nir_shader_info_pass()

pipeline->layout can't be NULL now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: remove one useless check in radv_flush_constants()

pipeline->layout can't be NULL now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: add assertions to make sure pipeline layout objects are valid

The spec requires it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: create pipeline layout objects for all meta operations

They are dummy objects but the spec requires layout to not be
NULL, this just makes sure we are creating valid pipeline layout
objects. This will allow us to remove some useless checks.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: Use a sort for rebuilding the sparse buffer bo list.

It uses slightly more memory (though still bounded by the number
of mapped ranges), but gives less quadratic behavior.

Cuts 4 minutes from the runtime of the CTS *.sparse.* tests.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

freedreno/ir3: handle VTXID_BASE for indirect draws

Need to do some gymnastics to copy the parameter from the indirect
parameters buffer to uniform so shader sees the correct base-vertex-id.

Fixes ./bin/arb_draw_indirect-vertexid on a5xx and probably a4xx too.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: add ctx->mem_to_mem()

For dealing with indirect-draw + gl_VertexID, we'll introduce another
case where we need to use CP_MEM_TO_MEM.  Rather than adding more
if(a5xx)/else make this a ctx vfunc.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: use vertex_id_zero_base

Cmdstream traces from blob make it clear that the blob driver dev's
*think* a5xx has a real (non-zero-based) vtxid.  But reality claims
differently.

Fixes ./bin/gl-3.2-basevertex-vertexid and probably others.

This means draw-indirect is going to need some gymnastics to copy
base-vertex into uniform.  (a4xx probably needs that too.)

Signed-off-by: Rob Clark <robdclark@gmail.com>

r600: clear compressed flags in image state on unbind.

If we aren't binding an image, clear the compressed flags.

This fixes a segfault seen with an apitrace.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104331
Signed-off-by: Dave Airlie <airlied@redhat.com>

swr: Account for index_bias in offsets

When calculating buffer offsets for client buffers account for info.index_bias.

Fixes the follow piglit tests:
arb_draw_elements_base_vertex-drawelements-user_varrays
arb_draw_elements_base_vertex-negative-index-user_varrays

Reviewed-By: Bruce Cherniak <bruce.cherniak@intel.com>

r600: only reported tgsi ir compute support on evergreen+

This fixes a crash on r600/r700.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Advertise sync fd import and export.

Passes dEQP-VK.*.sync_fd.*

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Implement sync file import/export for fences & semaphores.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv/amdgpu: wrap sync fd import/export.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: fix lds store for patch outputs.

This wasn't calculating the correct value, this along with
a nir patch fixes a regression in:
dEQP-VK.tessellation.shader_input_output.barrier

Fixes: 043d14db30a (ac/nir: don't write tcs outputs to LDS that aren't read back.)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

nir/linking: always set the used_across_stages/outputs_read bits

If we don't remap and output this code would trample the outputs
read bits.

This fixes a regression in
dEQP-VK.tessellation.shader_input_output.barrier

Fixes: 1c9c42d16b4c (nir: add varying component packing helpers)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

spirv: Relax the validation conditions of OpSelect

The Talos Principle contains shaders with an OpSelect between two
vectors where the condition is a scalar boolean.  This is technically
against the spec bout nir_builder gracefully handles it by splatting
out the condition to all the channels.  So long as the condition is a
boolean, just emit a warning instead of failing.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104246

radv: remove useless radv_cmask_info::base_address_reg

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

amd/common: add ac_vgt_gs_mode() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

amd/common: add ac_get_cb_shader_mask() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

Revert "radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components"

This reverts commit 2294d35b243dee15af15895e876a63b7d22e48cc.

We can't do this without adjusting the input SGPRs/VGPRs logic.
For now, just revert it. I will send a proper solution later.

It fixes a rendering issue in F1 2017 that CTS didn't catch up.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: port merge tess info from anv

anv merges the tess info correctly, but radv wasn't doing this.

This fixes hangs in
dEQP-VK.tessellation.winding.default_domain.hlsl_triangles_ccw

Fixes: 60fc0544e0 (radv/pipeline: handle tessellation shader compilation)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Add external fence support.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Implement VK_KHR_external_fence_fd.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Implement fences based on syncobjs.

Reviewed-by: Dave Airlie <airlied@redhat.com>

amd/common: Add detection of the syncobj wait/signal/reset ioctls.

First amdgpu bump after inclusion was 20 (which was done for local BOs).

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Add syncobj signal/reset/wait to winsys.

Reviewed-by: Dave Airlie <airlied@redhat.com>

configure/meson: Bump libdrm_amdgpu version requirement.

For the radv dependencies on syncobj signal/reset.

Reviewed-by: Dave Airlie <airlied@redhat.com>

android: fix vulkan driver build

fixes undefined references by adding missing wsi common API

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

android: fix undefined references to futex API

Fixes: f98a2768ca "mesa: Add new fast mtx_t mutex type for basic use cases"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

docs: mark GL4.3 as finished for r600

Still only on fp64 supported hw.

r600: export robust buffer access

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: export GLSL 430

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600/cs: add compute support to caps

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: always flush between gfx and compute

This is in no way optimal, but there seems to be some problems
mixing at the moment, lots of hangs, it is possible, just need
to figure out more magic.

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: fix unused variable warning

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Fix multi-layer blits.

We did not set the layer correctly for the dst, as we would keep
using the base layer. Same for the source image.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102710
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>

freedreno/a5xx: add a5xx blitter

FD_MESA_DEBUG=noblit to disable

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: add generic blitter

Basically a clone of util_blitter_blit() but with special handling to
blit PIPE_BUFFER as a PIPE_TEXTURE_1D.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: add non-draw batches for compute/blit

Get rid of "gmem" (ie. tiling) ringbuffer, and just emit setup commands
directly to "draw" ringbuffer for compute (and in future for blits not
using the 3d pipe).  This way we can have a simple flat cmdstream buffer
and bypass setup related to 3d pipe.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: track staging and shadow perf ctrs for the HUD

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: staging upload transfers

In the busy && !needs_flush case, we can support a DISCARD_RANGE upload
using a staging buffer.  This is a bit different from the case of mid-
batch uploads which require us to shadow the whole resource (because
later draws in an earlier tile happen before earlier draws in a later
tile).

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: update generated headers

Signed-off-by: Rob Clark <robdclark@gmail.com>

anv: Remove unused variable.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radeonsi: don't call force_dcc_off for buffers

This was undefined yet harmless behavior in LLVM.
Not anymore - it causes a hang now.

Cc: 17.3 <mesa-stable@lists.freedesktop.org>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>

isl: Don't require VALIGN_2 for R32G32B32_FLOAT on Haswell.

According to the RENDER_SURFACE_STATE internal documentation, the
R32G32B32_FLOAT restriction is marked "IVB" only.  We choose to apply
it to Ivybridge and Baytrail, but not Haswell.

Apparently fixes KHR-GL46.texture_size_promotion.functional on Haswell.

Changes these tests from crashing to skipping on Haswell:
- KHR-GL46.direct_state_access.textures_storage_multisample_2d_rgb32f
- KHR-GL46.direct_state_access.textures_storage_multisample_3d_rgb32f

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radeon/uvd: add and manage render picture list

Create a list in decoder to store all render picture buffer pointers that
currently being used in reference picture lists.

During get message buffer call, check each pointer in render_pic_list[]
within given pic->ref[] list, remove pointer that no longer being used by
pic->ref[]. Then add current render surface pointer to the render_pic_list[]
and assign the associated index to result.curr_idx.

As a result, result.curr_idx will have the correct index to represent the
current render picture, instead of the previous increamenting values.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: add and manage render picture list

Create a list in decoder to store all render picture buffer pointers that
currently being used in reference picture lists.

During get message buffer call, check each pointer in render_pic_list[]
within given pic->ref[] list, remove pointer that no longer being used by
pic->ref[]. Then add current render surface pointer to the render_pic_list[]
and assign the associated index to result.curr_idx.

As a result, result.curr_idx will have the correct index to represent the
current render picture, instead of the previous increamenting values.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

vl: remove is idr flag

Remove is_idr flag since not being used anymore.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: directly use idr pic flag

Remove is_idr flag, and use idr_pic_flag provided by vaapi directly

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vce: determine idr by pic type

Vaapi encode interface provides idr frame flags, where omx interface doesn't.
Therefore, change to use picture type to determine idr frame, which will
work for both interfaces.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

radeon/vcn: determine idr by pic type

Vaapi encode interface provides idr frame flags, where omx interface doesn't.
Therefore, change to use picture type to determine idr frame, which will
work for both interfaces.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

util: scons: wire up the sha1 test

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

swr/rast: Move more RTAI handling out of binner

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: EXTRACT2 changed from vextract/vinsert to vshuffle

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Fix cache of API thread event manager

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Replace VPSRL with LSHR

Replace use of x86 intrinsic with general llvm IR instruction.

Generates the same final assembly.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Rework thread binding parameters for machine partitioning

Add BASE_NUMA_NODE, BASE_CORE, BASE_THREAD parameters to
SwrCreateContext.

Add optional SWR_API_THREADING_INFO parameter to SwrCreateContext to
control reservation of API threads.

Add SwrBindApiThread() function to allow binding of API threads to
reserved HW threads.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Pull of RTAI gather & offset out of clip/bin code

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Remove no-op VBROADCAST of vID

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 Fetch - Fully widen 32-bit integer vertex components

Also widen the 16-bit a 8-bit integer vertex component gathers to SIMD16.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Replace INSERT2 vextract/vinsert with JOIN2 vshuffle

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 Fetch - Fully widen 16-bit float vertex components

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 Fetch - Fully widen 32-bit float vertex components

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Pass prim to ClipSimd

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Pull most of the VPAI manipulation out of the binner/clipper

Move out of binner/clipper; hand them down from the frontend code instead.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Move GatherScissors to header

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Rewrite Shuffle8bpcGatherd using shuffle

Ease future code maintenance, prepare for folding simd8 and simd16 versions.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Convert gather masks to Nx1bit

Simplifies calling code, gets gather function interface closer to llvm's
masked_gather.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: WIP - Widen fetch shader to SIMD16

Widen vertex gather/storage to SIMD16 for all component types.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Corrections to multi-scissor handling

binner's GatherScissors() will be turned into a real gather in the not
too distant future.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Binner fixes for viewport index offset handling

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Remove unneeded copy of gather mask

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

i965: Allow old begin/end queryobj for gen4/5 with HW contexts

Since we have HW contexts on gen4/5, we could take advantage of them, as
done for gen6+ in commit e32cd5ffbb72 ("i965: Rely on hardware contexts
for query objects on Gen6+."), to only emit a pair of counters at
begin/end queryobj, rather than around every primitive. However, to keep
queryobj working in the meantime as we bringup support for HW ctx on
gen4/5, we can keep using the existing code.

References: e32cd5ffbb72 ("i965: Rely on hardware contexts for query objects on Gen6+.")
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

freedreno: use u_transfer_helper

Signed-off-by: Rob Clark <robdclark@gmail.com>

gallium/util: add u_transfer_helper

Add a new helper that drivers can use to emulate various things that
need special handling in particular in transfer_map:

 1) z32_s8x24.. gl/gallium treats this as a single buffer with depth
    and stencil interleaved but hardware frequently treats this as
    separate z32 and s8 buffers.  Special pack/unpack handling is
    needed in transfer_map/unmap to pack/unpack the exposed buffer

 2) fake RGTC.. GPUs designed with GLES in mind, but which can other-
    wise do GL3, if native RGTC is not supported it can be emulated
    by converting to uncompressed internally, but needs pack/unpack
    in transfer_map/unmap

 3) MSAA resolves in the transfer_map() case

v2: add MSAA resolve based on Eric's "gallium: Add helpers for MSAA
    resolves in pipe_transfer_map()/unmap()." patch; avoid wrapping
    pipe_resource, to make it possible for drivers to use both this
    and threaded_context.

Signed-off-by: Rob Clark <robdclark@gmail.com>

i965: enable EXT_disjoint_timer_query extension

Following dEQP cases pass:
   dEQP-EGL.functional.get_proc_address.extension.gl_ext_disjoint_timer_query
   dEQP-EGL.functional.client_extensions.disjoint

Piglit test 'ext_disjoint_timer_query-simple' passes with these changes.

No changes/regression observed in Intel CI.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: GL_EXT_disjoint_timer_query extension API bits

Patch adds GL_GPU_DISJOINT_EXT and enables to use timer queries when
EXT_disjoint_timer_query is enabled.

v2: enable extension only when EXT_disjoint_timer_query set

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glapi: add GL_EXT_disjoint_timer_query

Most entrypoints already available via other extensions like
GL_EXT_occlusion_query_boolean, GL_EXT_timer_query.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: add DisjointOperation to gl_shared_state

This state will be used by EXT_disjoint_timer_query. As first
usage, patch sets DisjointOperation true when gpu reset happens.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

broadcom/vc5: Fix a typo in memcmp for sig unpack checking.

This shockingly ended up working out, because only the first byte of *sig
is used and (sizeof(*sig) != 0) == 1.  Fixes a compiler warning.

Link: https://bugs.freedesktop.org/show_bug.cgi?id=104183

broadcom/vc5: Enable NIR txd lowering on all txd instructions.

Fixes almost all of piglit's arb_shader_texture_lod grad tests, except for
the base -texgrad/texgradcube ones which fail on what appear to be
precision problems.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nir: Add a new lowering option to lower all txd to txl.

VC5 requires that all txd are lowered in the shader.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nir: Fix interaction of GL_CLAMP lowering with texture offsets.

We want the clamping of the coordinate to apply after the offset, so we
need to do math to lower the offset out of the instruction.  Fixes texwrap
offset cases for GL_CLAMP with GL_NEAREST on vc5.

Note: I moved the get_texture_size() verbatim, so that it was defined
before use.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

broadcom/vc5: Fix shader input/outputs for gallium's new NIR linking.

gallivm: implement accurate corner behavior for textureGather with cube maps

The spec says the missing texel (when we wrap around both x and y axis)
should be synthesized as the average of the 3 other texels. For bilinear
filtering however we instead adjusted the filter weights (because, while
the complexity looks similar, there would be 4 times as many color values
to fix up than weights). Obviously this could not work for gather (hence
accurate corner filtering was disabled with gather).
Implement this by just doing it as the spec implies - calculate the 4th
texel as the average of the other 3. With gather of course there's only
one color to worry about, so it's not all that many instructions neither
(albeit surely the whole cube map filtering is hilariously complex).

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

gallivm: fix an issue with NaNs with seamless cube filtering

Cube texture wrapping is a bit special since the values (post face
projection) always are within [0,1], so we took advantage of that and
omitted some clamps.
However, we can still get NaNs (either because the coords already had NaNs,
or the face projection generated them), and in fact we didn't handle them
quite safely. I've seen -INT_MAX + 1 been propagated through as the final int
coord value, albeit I didn't observe a crash. (Not quite a coincidence, since
any stride mul with -INT_MAX or -INT_MAX+1 will turn up as a small positive
number - nevertheless, I'd rather not try my luck, I'm not entirely sure it
can't really turn up negative neither due to seamless coord swapping, plus
ifloor of a NaN is not guaranteed to return -INT_MAX by any standard. And
we kill off NaNs similarly with ordinary texture wrapping too.)
So kill off the NaNs by using the common max against zero method.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

intel/tools: Convert aubinator over to the common framework

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: Decode registers

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: Decode dynamic state

Unfortunately, in aubinator and aubinator_error_decode we don't always
know how many of a given state we have, so we must guess.  One day,
we'll come up with a way to annotate the batch to solve this problem.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: Decode constants, binding tables, and samplers

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/tools: Switch aubinator_error_decode over to the gen_print_batch

The shared framework can now do everything that aubinator_error_decode
ever did and more.  It's time to make the switch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: Decode graphics shaders

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: Decode vertex and index buffers

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: Decode MEDIA_INTERFACE_DESCRIPTOR_LOAD

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/tools: Add the start of a generic batch decoder

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/decoder: Expose the raw field value in the iterator

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>