isl: Don't use surface format R32_FLOAT for typed atomic integer operations

From Skylake PRM Surface Formats section:

   "The surface format for the typed atomic integer operations must
    be R32_UINT or R32_SINT."

Fixes an error and a piglit GPU hang in simulation environment.
Piglit test: gl45-imageAtomicExchange-float.shader_test

Suggested-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.co
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "18.0 17.3" <mesa-stable@lists.freedesktop.org>

radeonsi/nir: fix si_nir_load_tcs_varyings() for outputs

We were incorrectly using the input info for outputs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac: implement nir_intrinsic_image_samples

Fixes cts test:
KHR-GL45.shader_texture_image_samples_tests.image_functional_test

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st: add NIR GL_ARB_get_program_binary support

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/shader_cache: add st_{de}serialise_nir_program() helpers

These will be used for NIR GL_ARB_get_program_binary support.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/nir_to_llvm: fix image size for arrays of arrays

Fixes cts test:
KHR-GL44.shader_image_size.advanced-changeSize

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi/nir: fix shader ballot return value bitsize

Fixes cts test:
KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

intel/aubinator: Correctly decode INTERFACE_DESCRIPTOR_DATA

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add gl_state_index casts for PATCH_VERTICES_IN

This fixes the build in clang

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105088
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/miptree: Initialize mcs with a linear map

When initializing mcs, map with MAP_RAW and fill in the linear
map. Removes a place where gtt mapping is used.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/tiled_memcpy: change linear pointer from (0, 0) to (xt1, yt1)

In all current uses, the linear surface is only allocated starting
at (xt1, yt1) anyway, so this improves the calling ergonomics.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/tiled_memcpy: linear_to_ytiled a cache line at a time

TileY's low 6 address bits are: v1 v0 u3 u2 u1 u0
Thus a cache line in the tiled surface is composed of a 2d area of
16x4 bytes of the linear surface.

Add a special case where the area being copied is 4-line aligned
and a multiple of 4-lines so that entire cache lines will be
written at a time.

On Apollolake, this increases tiling throughput to wc maps by
84.0103% +/- 0.862818%

v2: Split [y0, y1) and [y2, y3) loops apart for clarity (Jason Ekstrand)
v3: Don't reset src var (Jason), Ensure y0 <= y1 <= y2 <= y3

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

docs: Add Cannonlake support to 18.0 release notes.

17.4 is actually 18.0.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: "18.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv/gen10: Remove warning message.

Gen10 seems pretty stable so far, remove "alpha support" message.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: "18.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen10: Remove warning message.

Gen10 seems pretty stable so far, so there's no reason to keep this
message.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: "18.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

egl/x11: Fix leak in dri3_create_image_khr_pixmap

bp_reply wasn't properly free'd

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>

i965/compiler: clean up nir_intrinsic_load_input for vertex shaders

This code to re-set the type of the source and destination is not
necessary since we never manipulate the types. Looks like a
left over from a time where we had to retype to float temporarily
to handle 64-bit inputs.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

intel/compiler: fix first_component for 64-bit types on vertex inputs

Divide it by two as we do for other stages. This is because the
component layout qualifier is always in 32-bit units.

Fixes issues in a new CTS test (still WIP):
KHR-GL45.enhanced_layouts.varying_double_components

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

ac/nir: rename nir_to_llvm_context to radv_shader_context

There is still more to do in that area, but it's a good start.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: remove nir_to_llvm_context from ac_nir_translate()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: remove nir_to_llvm_context::nir link

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: move the outputs array to the ABI

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/shader: scan force_persample

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

r600: fix regression in gl_FragColor drawing

This fixes a regression in the broadcast color to all color bufs case.

Fixes: 6c691081a (r600: fixup sparse color exports.)
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: fix array spill if temp[0] is before all arrays

I found a shader with
DCL TEMP[0], LOCAL
DCL TEMP[1..256], ARRAY(1), LOCAL
DCL TEMP[257..512], ARRAY(2), LOCAL
DCL TEMP[513..768], ARRAY(3), LOCAL
DCL TEMP[769], LOCAL

This would remap badly, as it would add up all the spilled sizes
and subtract it from the temp for 0. If the current temp is less
than the array start break out.

Fixes: 1d871aa6 (r600g: Implement spilling of temp arrays (v2))
Signed-off-by: Dave Airlie <airlied@redhat.com>

virgl: add ARB_sample_shading support.

This enable ARB_sample_shading if the renderer supports it.

Signed-off-by: Dave Airlie <airlied@redhat.com>

virgl: add ARB_draw_indirect support.

This relies on the renderer code landing first.

Signed-off-by: Dave Airlie <airlied@redhat.com>

tgsi: Recognize RET in main for tgsi_transform

Shaders coming from dx10 state trackers have a RET before the END.
And the epilog needs to be placed before the RET (otherwise it will
get ignored).
Hence figure out if a RET is in main, in this case we'll place
the epilog there rather than before the END.
(At a closer look, there actually seem to be problems with control
flow in general with output redirection, that would need another
look. It's enough however to fix draw's aa line emulation in some
internal bug - lines tend to be drawn with trivial shaders, moving
either a constant color or a vertex color directly to the output).

v2: add assert so buggy handling of RET in main is detected

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

ac: Use the renumbered const address space for LLVM 7.

The LLVM AMDGPU backend decided to renumber the constant address
space ....

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

gallium: drop all the guard band float caps.

Nobody queries these and nobody sets them to anything useful,
the docs say TODO.

Drop them until a use appears.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: add glsl version query (v4)

Add support for GL_NUM_SHADING_LANGUAGE_VERSIONS
and glGetStringi for GL_SHADING_LANGUAGE_VERSION

v2:
  - Combine similar functionality into
    _mesa_get_shading_language_version() function.
  - Change GLSL version return mechanism.
v3:
  - Add return of empty string for GLSL ver 1.10.
  - Move _mesa_get_shading_language_version() function
    to src/mesa/main/version.c.
v4:
  - Add OpenGL version check.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104915
Signed-off-by: Andriy Khulap <andriy.khulap@globallogic.com>
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: add missing switch case for EXTRA_VERSION_40 in check_extra()

The EXTRA_VERSION_40 predicate is tested as part of
extra_gl40_ARB_sample_shading but there was no switch case for it.

Fixes: 77b440e42d8e7247c2295 ("mesa: Add new functions and enums required
by GL_ARB_sample_shading")
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

mesa: fix compile failure

Missing header triggered a failure in i965 CI buildtest project.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105067
Fixes: e149a0253c12d103805230bc7bc0a36887c3b8df

Partially revert "mesa: use GLenum16 in a few more places"

This reverts part of commit ca721b3d894a49d7342f5aa053ed132017e9352a.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105067

Revert "mesa: reduce the size of gl_texture_image"

This reverts commit f4ea2b2a9e99d93fbf36c3f0e5f6f384be3cdb89.

Several members reduced in size by the offending commit are not large
enough to store the data needed by the i965 driver.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105067

i965: fix tessellation regressions with gl_state_index16

Looks like one conversion was missed.

Fixes: e149a0253 (mesa,glsl,nir: reduce gl_state_index size to 2 bytes)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105067
Signed-off-by: Dave Airlie <airlied@redhat.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>

virgl: Support v2 caps struct (v2)

This struct allows us to report:
- accurate max point size/line width.
- accurate texel and texture gather offsets
- vertex/geometry limits.

Signed-off-by: Dave Airlie <airlied@redhat.com>

ac/nir: add nir_intrinsic_{load,store}_shared support

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

ac/nir_to_llvm: add support for nir_intrinsic_shared_atomic_*

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: make si_declare_compute_memory() more generic and call for nir

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/glsl: set req_local_mem earlier for compute shaders

Without this change it will never be set for backends using nir.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: move STATE_LENGTH to shader_enums.h and use it everywhere

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: reduce the size of gl_texture_image

80 -> 40 bytes.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: reduce the size of gl_program_parameter

40 -> 24 bytes, which includes the gl_state_index16 change.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa,glsl,nir: reduce gl_state_index size to 2 bytes

Let's use the new gl_state_index16 type everywhere and remove
the typecasts.

This helps reduce the size of gl_program_parameter.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: reduce the size of gl_viewport_attrib

All drivers convert these to float, so there is no reason to use double.
The piglit test that expects double precision from glGet will be adjusted
not to require it (there is a piglit patch).

gl_context::ViewportArray: 512 -> 384 bytes

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: reduce the size of gl_texture_object

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: reduce the size of gl_program

gl_program: 1456 -> 976 bytes

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: reduce the size of gl_image_unit (v2)

gl_context::ImageUnits: 6144 -> 4608 bytes

v2: use ASSERT_BITFIELD_SIZE

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: further reduce the size of ctx->Texture

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: decrease the array size of ctx->Texture.FixedFuncUnit to 8

GL allows doing glTexEnv on 192 texture units, while in reality,
only MaxTextureCoordUnits units are used by fixed-func shaders.

There is a piglit patch that adjusts piglits/texunits to check only
MaxTextureCoordUnits units.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: separate legacy stuff from gl_texture_unit into gl_fixedfunc_texture_unit

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: inline init_texture_unit

because this is going to be changed

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: use GLenum16 in a few more places

Reviewed-by: Brian Paul <brianp@vmware.com>

anv: Move setting current_pipeline to cmd_state_init

We were setting current_pipeline to UINT32_MAX and then calling
cmd_cmd_state_reset which memsets the entire state struct to 0 which
implicitly resets current_pipeline to 3D.  I have no idea how this
hasn't caused everything to explode.

Fixes: cd3feea74582 "anv/cmd_buffer: Rework anv_cmd_state_reset"
cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Don't resolve or ambiguate non-existent layers

The previous code was trying to avoid non-existent layers by taking a
MAX with anv_image_aux_layers.  Unfortunately, it wasn't taking into
account that layer_count starts at base_layer which may not be zero.
Instead, we need to subtract base_layer from anv_image_aux_layers with
a guard against roll-over.

Fixes: de3be6180169f9 "anv/cmd_buffer: Rework aux tracking"
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

i965: Fix bugs in intel_from_planar

This commit fixes two bugs in intel_from_planar.  First, if the planar
format was non-NULL but only had a single plane, we were falling through
to the planar case.  If we had a CCS modifier and plane == 1, we would
return NULL instead of the CCS plane.  Second, if we did end up in the
planar_format == NULL case and the modifier was DRM_FORMAT_MOD_INVALID,
we would end up segfaulting in isl_drm_modifier_has_aux.

Cc: mesa-stable@lists.freedesktop.org
Fixes: 8f6e54c92966bb94a3f05f2cc7ea804273e125ad
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radv: Fix compiler warning about uninitialized 'set'

The compiler doesn't figure out that we only get result == VK_SUCCESS if
set got initialized.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

glsl/tests: Fix strict aliasing warning about int64/double.

Fixes: 4bf986274728 ("glsl/tests: Add UINT64 and INT64 types")
Reviewed-by: Rhys Kidd <rhyskidd@gmail.com>

ac/nir: Fix compiler warning about uninitialized dw_addr.

Even switching the def's condition to be the same chip revision check as
the use, the compiler doesn't figure it out.  Just NULL-init it.

Fixes: ec53e527421d ("ac/nir: Add ES output to LDS for GFX9.")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

gallium/llvmpipe: Fix compiler warnings about ddx/ddy/ddmax.

My gcc doesn't figure out that dims >= 1 (seems reasonable), and doesn't
notice that ddmax is used from the same no_rho_opt as its initialization.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

anv: Drop I915_EXEC_CONSTANTS_REL_GENERAL from execbuf.

The kernel used to have execbuf parameters to program the INSTPM bit
for whether 3DSTATE_CONSTANT_* should be relative to dynamic state
base address or an absolute address.  However, they never worked in
the presence of hardware contexts, so I deleted them a while back.

It doesn't make sense to set this flag, as it doesn't exist anymore.
It also never did anything anyway - the flag is zero, so |'ing it in
did nothing.  The default is relative anyway.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

r200: remove left over dead code

0aaa27f29187ffb739c7 removed the references to this array without
removing the array itself

Cc: Ian Romanick <ian.d.romanick@intel.com>
Fixes: 0aaa27f29187ffb739c7 "mesa: Pass the translated color logic op dd_function_table::LogicOpcode"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>

ac/nir: remove backlink to nir_to_llvm_context

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: remove nir_to_llvm_context::module

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: remove nir_to_llvm_context::builder

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: drop nir_to_llvm_context from glsl_to_llvm_type()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: drop nir_to_llvm_context from visit_var_atomic()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: drop nir_to_llvm_context from visit_vulkan_resource_reindex()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: drop nir_to_llvm_context from visit_load_push_constant()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: drop nir_to_llvm_context from cast_ptr()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: drop nir_to_llvm_context from visit_load_local_invocation_index()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: drop nir_to_llvm_context from emit_f2f16()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: remove unused parameters in abi::load_tess_coord()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: remove useless bitcast in load_tess_coord()

nir_intrinsic_load_tess_coord always returns a v3i32.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: add load_resource() to the ABI

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: add load_sample_mask_in() to the ABI

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: move view_index to the ABI

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: move push_constants to the ABI

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: move tg_size to the ABI

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: remove unused nir_to_llvm_context:{defs,phis}

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

egl/gbm: Fix compiler warning about visual matching.

The compiler doesn't know that num_visuals > 0.

Fixes: 37a8d907cc16 ("egl/gbm: Ensure EGLConfigs match GBM surface format")
Reviewed-by: Daniel Stone <daniels@collabora.com>

freedreno: small fix for flushing dependent batches

Flush a resource's previous write_batch synchronously.  Because a
resource's associated batches are not updated until after the flush
thread submits rendering to the kernel, this was causing a bit of
confusion in the following loop.  This fixes a bug that appeared with
recent stk.

Perhaps we need to re-work things a bit to clear out dependent patches
in the ctx's thread and use a fence to deal with the period between
when a flush is queued and when it is submitted to the kernel.  But
this will do until time permits a larger refactor.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: intra-block scheduling

Because of loops, we can't schedule all of a block's predecessors first.
Instead just assume that the result consumed in a block was written far
enough away in all paths into a block.  And do an intra-block scheduling
pass to figure out if there are any cases where we need to insert extra
nop's.  This works out better than always assuming the worst case (ie.
that a value live into a block was written in the last instruction in
the predecessor block).

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: "boost" the depth of if/else condition

Account for the move to predicate register, to try to avoid needing to
insert extra NOPs later.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: account for arrays in delayslot calc

Normally false-deps are not something to consider, since they mostly
exist for delay-slot related reasons:

 * barriers
 * ordering writes after read
 * SSBO/image access ordering

The exception is a false-dependency on an array store.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: more clever legalize algorithm

Previously we didn't handle flow control in legalize, and instead just
set (ss)(sy) on the first instruction in every block.  Which isn't very
clever.

Instead, consider output state of all predecessor blocks, so we only
set a sync bit if needed for any possible path leading into a block.
Because of loops, we can't require that all successor blocks are
legalized before a given block, so instead run in a loop until results
converge.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: track block predecessors

Useful in the following patches.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: clean up dangling false-dep's

Maybe there is a better way for this..  where it comes useful is "array"
loads, which end up as a false-dep for a later array store.

If all the uses of an array load are CP'd into their consumer, it still
leaves the dangling array load, leading to funny things like:

  mov.u32u32 r5.y, r0.y
  mov.u32u32 r5.y, r0.z

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: handle IMMED for mad 2nd src special case

Consider also immediates for swapping the first two srcs, because they
can be lowered to constant.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: remove ir3 phi instruction

Now that we convert phi webs to ssa, we can drop all this.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: remove lower_if_else pass

Now that it is unused.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: add experimental GCM pass

Generally seems to do worse on instruction count and register usage,
according to shader-db.  But shader-db also doesn't do a very good job
of weighting loop bodies, so that might not be totally valid.

So add an env variable to enable GCM pass for easier experimentation.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: change opt passes

There are more useful nir passes added since initial conversion to nir.
But ir3 was never updated to use them.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: use peephole select pass

Agressively lowering all if/else to selects in some extreme cases
results in much higher register pressure.  Using peephole select instead
with a modest threshold speeds up alu2 4x!

16 seems like a good limit, low enough to help alu2 but not too low that
it penalizes everything else.  With a bit better scheduling of the
instruction that moves a value into a predicate register, we might be
able to lower this limit a bit more in the future, but since we need 6
cycles from the move to predicate register to predicated branch, that
puts some sort of lower bound on how far we can lower this threshold.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: lower phi webs to regs

nir's from_ssa pass is much better at avoiding inserting extra moves
than our logic is.  And lowering phi webs to regs just treats anything
involved in a phi web as an array of length=1.  Which with previous
array related fixes in RA/etc ends up working out quite well.  This cuts
down on extra instructions and also helps with register pressure.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: separate arrays from groups

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: make block/instruction serialno per-shader

Makes it easier to compare values seen in-game (where there are many
shaders) to cmdline standalone compiler.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: add spirv support to cmdline compiler

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: don't lower fsat

Instead, if possible fold (sat) flag into src, otherwise use:

  (sat)max.f rD, rS, rS

Signed-off-by: Rob Clark <robdclark@gmail.com>