aco: remove superflous (bool & exec) if the result comes from VOPC

This works in cases where the VOPC instruction was executed with
the same exec mask.

Totals from affected shaders: (VEGA)
SGPRS: 1342204 -> 1342164 (-0.00 %)
VGPRS: 877220 -> 877220 (0.00 %)
Spilled SGPRs: 157800 -> 157800 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 118083212 -> 118021748 (-0.05 %) bytes
LDS: 26 -> 26 (0.00 %) blocks
Max Waves: 144024 -> 144024 (0.00 %)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5563>

radv: enable zerovram for Quantic Dream games

Fixes various artifacts with Detroit: Become Human. This assumes other
Vulkan games using the same engine could have the same issues.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5710>

gitlab-ci: More stable URL for kernel and ramdisk artifacts, for LAVA

Place the kernel and ramdisk into a place in the file server so the URL
will only change when the contents also change.

Also put the Mesa build into a separate tarball so the ramdisk's
contents don't change every build.

With proper caching in place, all devices in the same farm need only to
download the mesa tarball once, saving time.

As we switch to MinIO for making kernels and rootfs available to LAVA
devices, we can stop using Docker to distribute them.

Instead, build when needed in separate jobs that push directly to MinIO,
from where LAVA devices can download them.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5515>

gitlab-ci: Build kernel drivers for a few ethernet USB dongles

So LAVA devices can download traces and upload test results.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5515>

nv50/ir/nir: fix cache mode conversion

The nir access qualifier is actually a bitfield, so we need to read out
like one.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5747>

gv100/ir: fix coherent and volatile memory access

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5747>

gv100/ir: implement sample shading

Fixes sample shading tests in the Khronos OpenGL(ES) CTS

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5747>

nv50/ir/nir: fix interpolation on explicit operations

Fixes a bunch of interpolate tests in the aosp GLES CTS

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5747>

iris: Fix fast-clearing of depth via glClearTex(Sub)Image

If we clear depth only texture via glClearTex(Sub)Image it may cause:
../src/intel/blorp/blorp_genX_exec.h:1554: blorp_emit_surface_states: Assertion `params->depth.enabled || params->stencil.enabled' failed.

due to clear_depth_stencil calling blorp_clear_depth_stencil when
depth is already fast-cleared and there is no stencil.

Fixes piglit test: arb_clear_texture-depth

Fixes: 51638cf18a532510f9e1fd8f36207b56d38137b8
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5770>

docs: fixup envvar output

Sphinx 2.x has changed how this works, and some of this whitespace now
gets stripped as a result. So let's instead actual whitespace as separate
text-nodes instead.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5706>

docs: use svg for graphviz output

This works a lot better on hidpi screens.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5706>

docs: move gallium specific docs into gallium folder

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5706>

docs: add an extension to generate redirects

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5706>

docs: clean up gallium index-file

This makes the TOC make much more sense.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5706>

merge gallium docs into main docs

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5706>

ci: add graphviz to the .docs-base template

The Gallium docs uses graphviz, so let's make sure it's installed first.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5706>

freedreno: Sync registers with envytools

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5557>

freedreno: Include adreno_pm4.xml.h before adreno_a6xx.xml.h

This matches the XML, and soon adreno_a6xx.xml will start including
types from adreno_pm4.xml.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5557>

gallium/swr: Fix compilation warnings

In some places in SWR cod objects are initialized using
memset/memcpy. This is usually done to enable
allocating those objects in aligned memory.
It generates compilation warnings though,
which are worked around by casting the pointers to void*
before calling memset/memcpy.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5777>

freedreno/a6xx: Force gl_Layer to 0 when necessary

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5732>

tu: Force gl_Layer to 0 when necessary

In particular this will help us implement input attachments correctly
with layered rendering.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5732>

ir3: Add layer_zero variant bit

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5732>

pan/decode: Make mapped memory read-only while decoding

This will help catch any bugs where descriptors are accidentally
modified.

v2: Use a dynarray of ro memory mappings rather than iterating through
    the mmap hash table.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5590>

panfrost: Expose MSAA 4x

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Save sample_mask before blitting

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Enable MSAA if we render to such a surface

We hit this case for clears of MSAA surfaces without draws.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Set depth/stencil_layer_stride accordingly

Same logic as colour layer stride, I think.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Identify depth/stencil layer strides

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Implement alpha-to-coverage

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Pass sample_mask to the hardware

Gallium computes it for us.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Identify coverage_mask

The driver specifies the mask directly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Don't advertise MSAA 2x

Let the frontend promote to MSAA 4x if the app requests it. We don't
support MSAA 2x.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Set layer_stride for multisampled rendering

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Include pointer for each sample

Treating it like an array/3D texture.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Index texture by sample

This will allow MSAA to route through.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Allocate space for multisampling

As an effective depth. Ugly but matches the blob.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Identify layer_stride

For MSAA.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

panfrost: Set depth to sample_count for MSAA 2D

Treated like a 3D texture.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

pan/mdg: Use _VTX tag for texelFetch in frag shaders

Probably a misnomer, let's match what the blob seemingly does though? At
least in blit shaders?

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

pan/mdg: Handle nir_texop_txf_ms

Same as nir_texop_txf, the special case where sample = 0.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

pan/mdg: Handle nir_tex_src_ms_index

Goes in .z for a txf_ms coordinate, same as a shadow comparator so we
reuse the impl.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

pan/mdg: Handle GLSL_SAMPLER_DIM_MS

Same as 2D.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

pan/mdg: Allow ignoring move mode

Ensures we can gaurantee we'll pick something, which matters for
depth/stencil export.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: de41c4c103d ("pan/mdg: Prioritize non-moves on VADD/VLUT")
Tested-by: Icecream95 <ixn@keemail.me>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

pan/decode: Identify layered MSAA flag

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

pan/decode: Fix MSAA texture decoding

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5782>

pan/mdg: Fix indirect UBO swizzles

Helps a lot of vertex shaders dramatically.

total instructions in shared programs: 48491 -> 48252 (-0.49%)
instructions in affected programs: 3091 -> 2852 (-7.73%)
helped: 30
HURT: 0
helped stats (abs) min: 1 max: 35 x̄: 7.97 x̃: 5
helped stats (rel) min: 0.57% max: 21.60% x̄: 7.98% x̃: 6.85%
95% mean confidence interval for instructions value: -11.11 -4.83
95% mean confidence interval for instructions %-change: -10.17% -5.80%
Instructions are helped.

total bundles in shared programs: 23392 -> 23105 (-1.23%)
bundles in affected programs: 2017 -> 1730 (-14.23%)
helped: 35
HURT: 0
helped stats (abs) min: 1 max: 34 x̄: 8.20 x̃: 7
helped stats (rel) min: 1.11% max: 34.69% x̄: 15.52% x̃: 18.42%
95% mean confidence interval for bundles value: -10.91 -5.49
95% mean confidence interval for bundles %-change: -19.28% -11.77%
Bundles are helped.

total quadwords in shared programs: 39586 -> 39611 (0.06%)
quadwords in affected programs: 1717 -> 1742 (1.46%)
helped: 5
HURT: 24
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.83% max: 3.57% x̄: 2.45% x̃: 2.78%
HURT stats (abs)   min: 1 max: 2 x̄: 1.25 x̃: 1
HURT stats (rel)   min: 1.00% max: 3.77% x̄: 2.17% x̃: 1.89%
95% mean confidence interval for quadwords value: 0.50 1.22
95% mean confidence interval for quadwords %-change: 0.61% 2.13%
Quadwords are HURT.

total registers in shared programs: 3337 -> 3272 (-1.95%)
registers in affected programs: 373 -> 308 (-17.43%)
helped: 34
HURT: 0
helped stats (abs) min: 1 max: 5 x̄: 1.91 x̃: 1
helped stats (rel) min: 6.25% max: 33.33% x̄: 16.76% x̃: 16.03%
95% mean confidence interval for registers value: -2.31 -1.51
95% mean confidence interval for registers %-change: -19.15% -14.37%
Registers are helped.

total threads in shared programs: 2593 -> 2615 (0.85%)
threads in affected programs: 22 -> 44 (100.00%)
helped: 21
HURT: 0
helped stats (abs) min: 1 max: 2 x̄: 1.05 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
95% mean confidence interval for threads value: 0.95 1.15
95% mean confidence interval for threads %-change: 100.00% 100.00%
Threads are [helped].

total loops in shared programs: 6 -> 6 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 17 -> 1 (-94.12%)
spills in affected programs: 16 -> 0
helped: 2
HURT: 0

total fills in shared programs: 35 -> 5 (-85.71%)
fills in affected programs: 30 -> 0
helped: 2
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5781>

pan/mdg: Respect type/mask in mir_lower_special_reads

Fixes RA issues with the lowered moves, as well as enabling more
aggressive scheduling (hence the slight shdaer-db win).

total instructions in shared programs: 48539 -> 48491 (-0.10%)
instructions in affected programs: 4400 -> 4352 (-1.09%)
helped: 13
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 3.69 x̃: 3
helped stats (rel) min: 0.50% max: 1.89% x̄: 1.06% x̃: 1.10%
95% mean confidence interval for instructions value: -5.05 -2.33
95% mean confidence interval for instructions %-change: -1.29% -0.84%
Instructions are helped.

total bundles in shared programs: 23447 -> 23392 (-0.23%)
bundles in affected programs: 2224 -> 2169 (-2.47%)
helped: 21
HURT: 1
helped stats (abs) min: 1 max: 8 x̄: 2.67 x̃: 2
helped stats (rel) min: 0.89% max: 20.00% x̄: 9.04% x̃: 2.40%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.20% max: 1.20% x̄: 1.20% x̃: 1.20%
95% mean confidence interval for bundles value: -3.51 -1.49
95% mean confidence interval for bundles %-change: -12.52% -4.63%
Bundles are helped.

total quadwords in shared programs: 39651 -> 39586 (-0.16%)
quadwords in affected programs: 5557 -> 5492 (-1.17%)
helped: 38
HURT: 1
helped stats (abs) min: 1 max: 2 x̄: 1.74 x̃: 2
helped stats (rel) min: 0.61% max: 14.29% x̄: 3.92% x̃: 1.20%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.69% max: 0.69% x̄: 0.69% x̃: 0.69%
95% mean confidence interval for quadwords value: -1.87 -1.47
95% mean confidence interval for quadwords %-change: -5.55% -2.05%
Quadwords are helped.

total registers in shared programs: 3336 -> 3337 (0.03%)
registers in affected programs: 21 -> 22 (4.76%)
helped: 1
HURT: 2
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 11.11% max: 11.11% x̄: 11.11% x̃: 11.11%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 16.67% max: 16.67% x̄: 16.67% x̃: 16.67%

total threads in shared programs: 2592 -> 2593 (0.04%)
threads in affected programs: 1 -> 2 (100.00%)
helped: 1
HURT: 0

total spills in shared programs: 17 -> 17 (0.00%)
spills in affected programs: 0 -> 0
helped: 0
HURT: 0

total fills in shared programs: 35 -> 35 (0.00%)
fills in affected programs: 0 -> 0
helped: 0
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5781>

ir3: use empirical size for params as used by the shader

For example only some UCPs may be used by the shader, triggering asserts
that too many consts are being uploaded.

While we're at it, also fix the const size when loading UCPs, since
otherwise it doesn't correspond to what the shader is actually using.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5752>

bifrost: Set RTZ rounding mode for f2i conversion

Fixes dEQP-GLES2.functional.shaders.conversions.scalar_to_scalar.float_to_int_fragment

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5779>

tu: Enable KHR_variable_pointers

Passes dEQP-VK.spirv_assembly.instruction.graphics.variable_pointers.*
and dEQP-VK.spirv_assembly.instruction.compute.variable_pointers.*

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5684>

tu: Rewrite variable lowering

Don't lower to offsets, instead use nir_lower_explicit_io here and
use actual pointers for UBO's and SSBO's. This makes
KHR_variable_pointers trivial. This also fixes asserts with shared
variables, which are now supposed to be lowered with
nir_lower_explicit_io.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5684>

anv: garbage collect timeline semaphore when querying value

If we don't garbage collect the timeline, the value never progresses
even though work completed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3226
Fixes: 34f32a6d664807 ("anv: implement VK_KHR_timeline_semaphore")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5774>

v3d: Enable perpendicular line caps when line smoothing

V3D has a bit to set the line caps to be perpendicular to the line
rather than aligned to the edges of the framebuffer. I don’t know what
the disadvantages are of enabling this, but I noticed by experimentation
that enabling line smoothing on the Intel driver also enables nicer line
caps, so it seems nice to enable it here too.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5624>

v3d: Add a lowering pass for line smoothing

When line smoothing is enabled, the driver now increases the width of
the line so that it can add some semi-transparent pixels to either side
of the line. A lowering pass is added which modifies the alpha component
of every write to fragment output 0 so that if the fragment is outside
the width of the line then the alpha is reduced. It additionally
discards fragments that are completely invisible. It might seem bad to
use discard on a tiled renderer but the assumption is that any bad
effects from using discard will also happen anyway because of enabling
alpha blending.

v2: Disable the line smoothing pass entirely when the framebuffer
    contains an integer colour output or one with no alpha channel.
    Calculate the coverage once upfront and store in a global variable
    instead of calculating each time an output write is modified. Also
    do the conditional discard once upfront.
v3: Don’t check whether the output buffer has an alpha channel. Only
    look at output 0. Use aa_line_width intrinsic instead of calculating
    the real line width in the shader. Clamp the coverage as part of the
    global variable, not per output write.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5624>

v3d: Handle the line width intrinsics

Adds new QUNIFORMs to store the line widths.

v2: Also handle the aa_line_width intrinsic

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5624>

nir: Add intrinsics for the line width

The first intrinsic is intended to expose the value set by glLineWidth
to shaders internally. The second intrinsic exposes the value actually
sent to the hardware. This may be wider than the first one in order to
implement anti-aliasing. These will be used in later patches to
implement a line smoothing lowering pass.

v2: Add a second intrinsic for the expanded line width for
    anti-aliasing.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5624>

v3d: Implement the line coord intrinsic

The line coord intrinsic is loaded from the implicit varying stored in
the same slot as the point coord when drawing lines.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5624>

compiler: Add a system value for the line coord

The line coord is a coordinate along the axis perpendicular to the line.
It is in the range [0,1] between the two edges of the line. It is
available at least on Broadcom hardware.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5624>

intel/perf: move query_mask and location out of gen_perf_query_counter

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5399>

iris: remove iris_monitor_config

perf_cfg is enough - it already contains almost all necessary
information and is constructed in a more optimal way (O(n) vs O(n^2)
- it uses hash table to build the unique counter list).

"Almost all", because it doesn't contain OA raw counters, but
we should have not exposed them anyway. Quoting Mark Janes:
"I see no reason to include the OA raw counters in the list that
are provided to the user. They are unusable.
The MDAPI library can be used to configure raw counters in a way
that provides esoteric metrics, but that library is written against
INTEL_performance_query."

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5399>

a4xx: hook up centroid ij coords

This is necessary now that the compiler respects centroid interpolation,
even in non-MSAA mode. Otherwise the interpolation doesn't work. Fixes a
bunch of dEQP centroid transform feedback tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5778>

nir: Add docs to nir_lower[_explicit]_io

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5418>

nir: Remove shared support from lower_io

No drivers are using this anymore so we can delete it and not keep
maintaining this legacy code-path.  If any drivers want this in the
future, they should use nir_lower_varst_to_explicit_types followed by
nir_lower_explicit_io.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5418>

nir: Assert that nir_lower_io is only called with allowed modes

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5418>

panfrost: Only call nir_lower_io on shader_in/out

Gallium drivers should never see nir_var_uniform because gallium lowers
regular uniforms to a UBO.  No GL driver should ever see either
nir_var_mem_shared because that's lowered in GLSL IR.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5418>

v3d: Only call nir_lower_io on shader_in/out

Gallium drivers should never see nir_var_uniform because gallium lowers
regular uniforms to a UBO.  No GL driver should ever see either
nir_var_mem_shared because that's lowered in GLSL IR.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5418>

vc4: Only call nir_lower_io on shader_in/out

Gallium drivers should never see nir_var_uniform because gallium lowers
regular uniforms to a UBO.  No GL driver should ever see either
nir_var_mem_shared because that's lowered in GLSL IR.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5418>

nouveau: Only call nir_lower_io on shader_in/out

Gallium drivers should never see nir_var_uniform because gallium lowers
regular uniforms to a UBO.  No GL driver should ever see either
nir_var_mem_shared because that's lowered in GLSL IR.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5418>

lima: Only call nir_lower_io on shader_in/out

Gallium drivers should never see nir_var_uniform because gallium lowers
regular uniforms to a UBO.  No GL driver should ever see either
nir_var_mem_shared because that's lowered in GLSL IR.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5418>

freedreno: Only call nir_lower_io on shader_in/out

Gallium drivers should never see nir_var_uniform because gallium lowers
regular uniforms to a UBO.  No GL driver should ever see either
nir_var_mem_shared because that's lowered in GLSL IR.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5418>

ir3: mark ucp_enables as allowed values on all keys

Both vertex and fragment shaders need to have the lowering.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5751>

etnaviv: replace prims-emitted query

As we do not support stream output buffers we only count the primitives
processed by the pipeline. Use the correct query type.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5754>

a4xx: add polygon offset clamp, fix units

For some reason, in order to get all tests to pass, pretty much all
hardware (across vendors) has to program in offset_units * 2. This fixes
dEQP-GLES3.functional.polygon_offset.float32_displacement_with_units.

While we're at it, add polygon offset clamp support.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5763>

a4xx: add noperspective interpolation support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5753>

nir: add vec2_index_32bit_offset address format

For turnip, we use the "bindless" model on a6xx. Loads and stores with
the bindless model require a bindless base, which is an immediate field
in the instruction that selects between 5 different 64-bit "bindless
base registers", a 32-bit descriptor index that's added to the base, and
the usual 32-bit offset. The bindless base usually, but not always,
corresponds to the Vulkan descriptor set.  We can handle the case where
the base is non-constant by using a bunch of if-statements, to make it a
little easier in core NIR, and this seems to be what Qualcomm's driver
does too. Therefore, the pointer format we need to use in NIR has a vec2
index, for the bindless base and descriptor index. Plumb this format
through core NIR.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5683>

nir: Refactor load/store intrinsic helper

Add the possibility to specify the source components. This is necessary
to let the UBO/SSBO index have more than one component, and it also lets
us remove a few hand-rolled load intrinsic definitions.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5683>

freedreno/regs: document SS6_UBO state src

Document this new a6xx_state_src value seen in A640/A650 tess traces.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5760>

freedreno/fdperf: prefer render node

Avoid inadvertantly becoming master if fdperf happens to be the first
thing to open the device.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5762>

freedreno/fdperf: better compatible string matching

Previously we would match the start of the compatible string, in
a couple of cases, in order to match compatible strings like
"qcom,adreno-630.2".  But these cases would always list a more
generic compatible (ie. "qcom,adreno") as a later choice.  So if
we parse all the compatible strings, we can do a more precise
exact match.

This avoids us accidentially matching on "qcom,adreno-smmu" and
the hilarity that ensues.

Fixes: 5a13507164a ("freedreno/perfcntrs: add fdperf")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5762>

freedreno/fdperf: fix print of base address

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5762>

wsi/x11: Log swapchain status changes

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5672>

vulkan/wsi: Don't consider VK_SUBOPTIMAL_KHR to be an error condition

This was causing vkAcquireNextImageKHR to not signal the fences and
semaphores.  In the case where the semaphore was brand new, this could
cause an unsignalled syncobj to be passed into execbuffer2 which it will
reject with -EINVAL leading to VK_ERROR_DEVICE_LOST.  Thanks to Henrik
Rydgård who works on the PPSSPP project for helping me figure this out.

Fixes: ca3cfbf6f1e00 "vk: Add an initial implementation of the actual..."
Fixes: 778b51f491cfe "vulkan/wsi: Add a hooks for signaling semaphores..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5672>

Revert "radv: add support for MRTs compaction to avoid holes"

This reverts commit 7a5e6fd25f2e132ef4cacc3a5b714c4e153227b0.

Since we have two different users bisecting issues to this commit, let's
revert.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 7a5e6fd25f2 "radv: add support for MRTs compaction to avoid holes"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3202
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3228
(Other report in https://gitlab.freedesktop.org/mesa/mesa/-/issues/3151#note_558589)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5758>

radv: Always enable PERFECT_ZPASS_COUNTS.

We have an issue with early depth testing and discard, where
non-perfect counts count the tile if the early depth test succeeds.

We could spend a lot of effort to set this conditionally based
on the presence of the two conditions, but in the presence of
inherited queries let's try this first.

Changing PERFECT_ZPASS_COUNTS since I'm pretty sure this has a lower
performance impact than always using late depth testing.

CC: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5757>

radv: Set handle types in Android semaphore/fence import.

Seems like we forgot to set it all this time ...

Fixes: b1444c9ccb0 "radv: Implement VK_ANDROID_native_buffer."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5759>

radv: disable FMASK compression when drawing with GENERAL layout

Fixes: 96063100 "radv: enable shaderStorageImageMultisample feature on GFX8+"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3219
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/855
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3165>

Revert "nir: Support sysval tess levels in SPIR-V to NIR"

This reverts commit d2d4677b56efa0003065b61e39c1ef977c83f7da.

The option is not used by any driver.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5744>

Revert "nir: Add an option for lowering TessLevelInner/Outer to vecs"

This reverts commit d2df0761200ba9680f0d22defaa02c33fb051fcf.

The option is not used by any driver.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5744>

freedreno/ir3: fix/rework tess levels

The previous version assumes tess level outputs will only be written once
in the shader, however its not possible to guarantee that.

It also assumes all invocations will write all the levels, which is also
not guaranteed.

This is required to fix the "tesselation" and "terraintessellation" demos
with turnip.

The comment about nir_lower_io_to_temporaries in lower_tess_ctrl_block is
removed because nir_lower_io_to_temporaries specifically skips TESS_CTRL
shaders so the comment doesn't make sense.

The split load for tess levels workaround is removed, the new version only
has scalar access unless if ever gets vectorized.

This sets NIR_COMPACT_ARRAYS cap to avoid the glsl tess vec lowering with
gallium. It seems this will also disable "LowerCombinedClipCullDistance",
which I'm not sure was needed or not.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5744>

freedreno/layout: fix explicit layout offset not added to slice offset

Accidentally broke this when rebasing the offending commit.

My use case with non-zero explicit offset is UV plane of UBWC NV12, and
only the UBWC slice offset is used for the UBWC sampler, so I didn't catch
it immediately.

Fixes: d53dc6c37680eba8e8 ("freedreno/fdl6: rework layout code a bit (reduce linear align to 64 bytes)")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5761>

amd/addrlib: fix another C++ one definition rule violation

Clashes with the SI definition.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3116
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5673>

iris: return max counter value for AMD_performance_monitor

glGetPerfMonitorCounterInfoAMD(..., ..., GL_COUNTER_RANGE_AMD, ...)
returned NAN (binary representation of uint64_t(-1) as float) as
a max value.

Fixes: 0fd4359733e6 ("iris/perf: implement routines to return counter info")
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5473>

st/mesa: fix reporting of float perf counters max value

Some Piglit tests (rightfully) fail because of min >= max when exposed
to perf counters that do not explicitly define their max value.

Failing tests:
spec/amd_performance_monitor/api/test_counter_info
spec/amd_performance_monitor/vc4/test_counter_info

u32/u64 changes are no-ops.

Fixes: 4cd1cfb9831d ("st/mesa: implement GL_AMD_performance_monitor")
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5473>

llvmpipe: enable GL 4.2

mostly just docs patch, features were all complete already

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5724>

llvmpipe: bump to GL support to GL 4.1

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5724>

llvmpipe: bump texture/scene limits to enable GL 4.1

Do we need to make this more dynamic? or have some options for vmware
embedded?

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5724>

mesa/version: only enable GL4.1 with correct limits.

I haven't tested all the limits, but these two should be enough
for driver writers to realise.

I've also submitted a minmax test for piglit to test this.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5727>

turnip: enable 420_UNORM formats

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4600>

turnip: support multi-image layouts

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4600>

turnip: clear_blit: pass aspect mask to setup function

Avoids having to duplicate logic to figure out the write mask on D24S8

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4600>