turnip: add astc format layout

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

turnip: fix assert failing for 0 color attachments

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

turnip: fix segmentation fault with compute pipeline

Not supported, so always set pointer to NULL

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

turnip: fix segmentation fault in events

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

turnip: fix 32 vertex attributes case

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

turnip: fix triangle strip

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

freedreno/regs: update a6xx 2d blit bits

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

radv: rename VK_KHR_shader_float16_int8 structs/constants

Trivial change.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

v3d: drop unused shader_rec_count member from context

Looks like this was copied from the vc4 driver where it is actually
included in the submit CL ioctl.

Reviewed-by: Eric Anholt <eric@anholt.net>

freedreno/ir3: implement fquantize2f16

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robclark@gmail.com>

freedreno/ir3: implement texop_texture_samples

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robclark@gmail.com>

freedreno/ir3: fix GETLOD for negative LODs

Note: for output type U32, negative LOD is not sign extended from 16 bits

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robclark@gmail.com>

freedreno/ir3: implement fdd{x,y}_coarse opcodes

Same as regular fddx/fddy.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robclark@gmail.com>

freedreno/ir3: increase size of inputs/outputs arrays

Makes it possible to support 32 varyings.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robclark@gmail.com>

freedreno/ir3: remove input ncomp field

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robclark@gmail.com>

etnaviv: fix vertex buffer state emission for single stream GPUs

GPUs with a single supported vertex stream must use the single state
address to program the stream.

Fixes: 3d09bb390a39 (etnaviv: GC7000: State changes for HALTI3..5)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>

gallivm/draw/swr: make the gs_iface not depend on tgsi.

This gs_iface doesn't seem to require a dependence on the tgsi
context, except for the swr end prim code.

This refactors the API to include all the info that the swr
code needs in the interface rather than having to dig it out of
the struct inheritance.

This is a precursor to adding NIR support to llvmpipe.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>

iris: Implement the Gen < 9 tessellation quads workaround

Fixes several CTS tests:
- KHR-GL46.tessellation_shader.vertex.vertex_spacing
- KHR-GL46.tessellation_shader.tessellation_shader_point_mode.points_verification

Fixes: 823609b1a39 ("iris/WIP: add broadwell support")

anv: Advertise VK_KHR_spirv_1_4

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

vulkan: Update the XML and headers to 1.1.125

Acked-by: Jason Ekstrand <jason@jlekstrand.net>

android: amd/common: export amd/llvm headers

Fixes the following building error:

external/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c:42:10:
fatal error: 'ac_llvm_util.h' file not found
         ^~~~~~~~~~~~~~~~
1 error generated.

Fixes: 3a08110 ("amd: Move all amd/common code that depends on LLVM to amd/llvm.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

gallium: rename PIPE_CAP_MAX_FRAMES_IN_FLIGHT to PIPE_CAP_THROTTLE

v2: [ Michel Dänzer ]
* Update src/gallium/docs/source/screen.rst accordingly

Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> # v1
Reviewed-by: Marek Olšák <marek.olsak@amd.com> # v1

gallium: simplify throttle implementation

All gallium drivers currently set MAX_FRAME_IN_FLIGHT to either 1
or 0, which means that the drivers either throttle on the previous
render or don't throttle, the current implementation is more
complicated than necessary and can be simplified.

Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radv: fix DCC fast clear code for intensity formats

This fixes a rendering issue with DiRT 4 on GFX10. Only GFX10 was
affected because intensity formats are different.

Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1923
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

gbm: use size_t for array indexes

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>

gbm: replace NULL sentinel with explicit ARRAY_SIZE()

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>

gbm: replace 1/0 bool with true/false

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>

gbm: turn 0/-1 bool into true/false

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>

radv: add exported symbols check

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

anv: add exported symbols check

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

symbols-check: ignore exported C++ symbols

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

panfrost: Fix support for packed 24-bit formats

pan_pack_color() color was missing the 24-bit packed format case.
Looks like putting the clear color in a 32-bit slot does the trick.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

glsl: fix crash compiling bindless samplers inside unnamed UBOs

The check to see if we were dealing with a buffer block was
too late and only worked for named UBOs.

Fixes: f32b01ca435c "glsl/linker: remove ubo explicit binding handling"
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1900

glsl/builtin: Add alternate versions of atan using new ops

Adds alternate versions of the atan builtin functions that use
ir_unop_atan and ir_binop_atan2 instead of inlining to the IR
implementation of the function. These alternatives are selected if the
IR is going to be consumed by NIR. In that case the IR ops will be
translated to the appropriate NIR op.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

glsl: Add opcodes for atan and atan2

Adds ir_binop_atan2 and ir_unop_atan. When converting to NIR these are
expanded out using the appropriate builtin generator. If they are used
with anything else then it will just hit an assert.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

nir/builtin: Add extern "C" guards to nir_builtin_builder.h

That way it can also be included from a C++ source.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

nir/builtin: Add #include u_math.h to the header

The inline functions use M_PI so they should include a header to make
sure it is defined.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

nir/builder: Move nir_atan and nir_atan2 from SPIR-V translator

Moves build_atan and build_atan2 into nir_builtin_builder. The goal is
to be able to use this from the GLSL translator too.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

egl: Configs w/o double buffering support have no `EGL_WINDOW_BIT`.

When users pass a config to `eglCreateWindowSurface` it requests double
buffering, but if the config doesn't have the appropriate `__DRIconfig`,
`eglCreateWindowSurface` fails with a `EGL_BAD_MATCH`.

Given that such behaviour is completely unacceptable, we drop the
`EGL_WINDOW_BIT` if we don't have at least one `__DRIconfig` supporting double
buffering, otherwise dropping the `EGL_PIXMAP_BIT`.

Fixes: 049f343e8ac "egl: Allow 24-bit visuals for 32-bit RGBA8888 configs"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67676
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Hal Gentz <zegentzy@protonmail.com>

egl: Puts RGBA visuals in the second config selection group.

That way applications don't get windows that are compositor alpha-blended
accidentally.

In the ideal world, this would be done by the xserver, as it does for
GLX, however, an appropriate place could not be found, so it's being
placed here instead.

Fixes: 049f343e8ac "egl: Allow 24-bit visuals for 32-bit RGBA8888 configs"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67676
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Hal Gentz <zegentzy@protonmail.com>

egl: Fixes transparency with EGL and X11.

This commit does this by allowing both RGB and RGBA visuals to match with
EGL configs. We also expose the `EGL_MESA_config_select_group` egl
extension, which is similar to GLX's visual select group extension, to
allow the RGBA visuals to get less priority.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67676
Fixes: 049f343e8ac "egl: Allow 24-bit visuals for 32-bit RGBA8888 configs"
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Hal Gentz <zegentzy@protonmail.com>

egl: Add EGL_CONFIG_SELECT_GROUP_MESA ext.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67676
Fixes: 049f343e8ac "egl: Allow 24-bit visuals for 32-bit RGBA8888 configs"
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Hal Gentz <zegentzy@protonmail.com>

intel/fs/gen12: Use TCS 8_PATCH mode.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

intel/fs/gen12: Implement gl_FrontFacing on gen12+.

The bit moved on gen12 in order to prepare for dual-SIMD8 dispatch.
This implementation isn't an entirely complete as it only works on SIMD8
and SIMD16 and not dual-SIMD8.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/fs/gen11+: Fix CS_OPCODE_CS_TERMINATE codegen.

Apparently the ts_request_type and ts_resource_select thread spawner
message descriptor bits were removed from the hardware at least since
ICL.  Drop them in order to avoid assertion failures on Gen12+
platforms which don't have any encoding for this.  On Gen9+ these are
probably just ignored by the hardware, so this is unlikely to have had
any functional implications prior to Gen12.

v2: Mark TS message fields as non-existing in brw_inst.h on ICL. (Caio)

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/fs/gen12: Fix barrier codegen.

The WAIT instruction has been removed, but SYNC.bar can be used
instead to wait for a notification on n0.0.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu: Don't set notify descriptor field of gateway barrier message.

Apparently this field was removed on SKL, and according to the
hardware docs for previous platforms "This field is only valid for a
ForwardMsg message. It is ignored for other messages. The BarrierMsg
message always increments the N0 notification counter".

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/ir/gen12: Update assert in brw_stage_has_packed_dispatch().

Confirmed no regressions after a full Piglit run on TGL with the
brw_fs_test_dispatch_packing() test enabled.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/validate/gen12: Don't blow up on indirect src0.

They look like a NULL source if you don't look at the address mode.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/validate/gen12: Validation fixes for SEND instruction.

The following fix-up by Jordan Justen is squashed in:

 intel/eu/validate: gen12 send instruction doesn't have a dst type field

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/validate/gen12: Fix validation of SYNC instruction.

src0 will typically be null for this instruction.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/validate/gen12: Implement integer multiply restrictions in EU validator.

Due to hardware bug filed as HSDES#1604601757.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/ir: Lower fpow on Gen12.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/fs/gen12: Don't support source mods for 32x16 integer multiply.

Due to hardware bug filed as HSDES#1604601757.

v2: Only return if result of fs_inst::can_do_source_mods() is known to
    be false for the case new orthogonal restrictions are implemented
    below in the future. (Caio)

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/disasm: Disassemble register file of split SEND sources.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/disasm: Don't disassemble saturate control on SEND instructions.

The field is gone on Gen12+ and it was illegal on previous
generations.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/disasm/gen12: Disassemble Gen12 SEND instructions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/disasm/gen12: Disassemble Gen12 SYNC instruction.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/disasm/gen12: Disassemble three-source instruction source and destination regions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/disasm/gen12: Fix disassembly of some common instruction controls.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/disasm/gen12: Disassemble software scoreboard information.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/fs/gen12: Demodernize software scoreboard lowering pass.

Kept as a separate commit in order to avoid distracting reviewers of
the software scoreboard pass with memory management boilerplate.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/fs/gen12: Introduce software scoreboard lowering pass.

Gen12+ hardware lacks the register scoreboard logic that used to
guarantee data coherency between register reads and writes in previous
generations.  This lowering pass runs after register allocation in
order to make up for it.

It works by performing global dataflow analysis in order to determine
the set of potential dependencies of every instruction in the shader,
and then inserts any required SWSB annotations and additional SYNC
instructions in order to guarantee data coherency.

v2: Drop unnecessary _safe list iteration (Caio).

v3: Temporarily workaround potential WaR hazard between FPU
    instruction and subsequent out-of-order write, pending
    clarification from the hardware team.  Drop redundant tracking of
    implicit access of acc0-1, since the hardware guarantees coherency
    of these (but not the other accumulators...).

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/fs/gen12: Add scheduling information to the IR.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/eu/gen12: Set SWSB annotations in hand-crafted assembly.

Reviewers are encouraged to audit the code generation pass
independently for the case I missed some potential data hazard or new
code has been added in the meantime.

v2: Add SYNC instruction to cr0 workaround in brw_float_controls_mode().

v3: Drop likely redundant (and potentially harmful) RegDist SWSB
    annotation from ce0 read in brw_find_live_channel() (Caio).

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/eu/gen12: Add tracking of default SWSB state to the current brw_codegen instruction.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.

v2: Introduce extra tgl_swsb_sbid() constructor (Caio).

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/fs/gen12: Add codegen support for the SYNC instruction.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/ir/gen12: Add SYNC hardware instruction.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Don't set thread control, it's gone.

An effect similar to the one formerly provided by setting thread
control to "switch" can be achieved now by setting a RegDist of 1 on
the SWSB field.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Don't set DD control, it's gone.

A future lowering pass will simulate the same behavior originally
provided by NoDDChk/NoDDClr at the IR level by using appropriate SWSB
annotations.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Use SEND instruction for split sends.

The new SEND instruction behaves like the former SENDS instruction.
The original single-payload SEND instruction is gone.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Codegen SEND descriptor regions correctly.

The SEND instruction is now four-source.  The descriptor is no longer
part of source 1, so avoid touching it to avoid corruption while
initializing the descriptor.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Codegen pathological SEND source and destination regions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Codegen control flow instructions correctly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Codegen three-source instruction source and destination regions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Fix codegen of immediate source regions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Add Gen12 opcode descriptions to the table.

Quite a lot of churn because the encoding of most hardware opcodes has
changed unfortunately.

v2: Split dot-product description fixes to separate patch (Caio).

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen11+: Mark dot product opcodes as unsupported on opcode_descs table.

These instructions have been removed from the hardware.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/eu/gen12: Implement datatype binary encoding.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Implement immediate 64 bit constant encoding.

On Gen12, 64 bit immediate constants are loaded in reverse order. Lower
32 bit gets loaded from bit 96-127 and higher 32 bits from 64-95 in
instruction encoding.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Co-authored-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/eu/gen12: Implement compact instruction binary encoding.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/eu/gen12: Implement indirect region binary encoding.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/eu/gen12: Implement SEND instruction binary encoding.

v2: Fix off-by-one upper GET_BITS() bound, combine 25-29 and 30-31
    descriptor fields (Ken).  Shorten name of GEN12_MD() macro, drop
    some removed TS message descriptor fields (Jordan).

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Implement control flow instruction binary encoding.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Implement three-source instruction binary encoding.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Implement basic instruction binary encoding.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Add sanity-check asserts to brw_inst_bits() and brw_inst_set_bits().

These caught a few bugs during the development of this series.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu/gen12: Extend brw_inst.h macros for Gen12 support.

The encoding of almost every instruction field has changed in Gen12,
so this involves adding a Gen12+ bitfield spec to every brw_inst
macro.  In addition some new macros are required to handle certain
discontiguous and variable-length fields.

This commit doesn't actually include the Gen12 updated bitfield specs,
only the macros are extended here for reviewability.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
v2: Rename FDC() to FFDC() and FDC1() to FDC() for consistency with
    the existing F() and FF() macros.

intel/ir: Represent physical edge of unconditional CONTINUE instruction.

This edge doesn't exist in the original scalar program, but it
represents a potential control flow path the EU will take in cases
where control flow isn't uniform across channels of the same SIMD
thread.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/ir: Represent physical edge of ELSE instruction.

This edge doesn't exist in the original scalar program, but it
represents a potential control flow path the EU will take in cases
where the condition isn't uniform across channels of the same SIMD
thread.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/ir: Represent logical edge of BREAK instruction.

Currently only the physical back-edge is represented, which
incidentally also leads to the exit block of the loop, but we need the
direct logical edge in addition for our logical CFG representation to
be complete.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/ir: Add helper function to push block onto CFG analysis stack.

Requested-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/ir: Represent physical and logical subsets of the CFG.

This represents two control flow graphs in the same cfg_t data
structure: The physical CFG that will include all possible control
flow paths the EU can physically take, and the logical CFG restricted
to the control flow paths that exist in the original scalar program.
The latter is a subset of the former because in case of divergence the
SIMD vectorized program will take control flow paths that aren't part
of the original scalar program.

The bblock_link constructor and bblock_t::add_successor() now take a
"kind" parameter that specifies whether the edge is purely physical or
whether it's part of both the logical and physical CFGs (a logical
edge is of course always guaranteed to be in the physical CFG as
well).  bblock_t::is_predecessor_of() and ::is_successor_of() also
take a kind parameter specifying which CFG is being queried.  The '~>'
notation will be used now in order to represent purely physical edges
in IR dumps.

This commit doesn't actually add nor remove any edges from the CFG
(the only edges marked as purely physical here are the two WHILE loop
ones that already existed).  Optimization passes should continue using
the same (incomplete) physical CFG they were using before until
they're fixed to do something smarter in a later commit, so this
shouldn't lead to any functional changes.

v2: Remove tabs from lines changed in this file (Caio).

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

intel/ir: Drop hard-coded correspondence between IR and HW opcodes.

Having the IR opcodes locked to their hardware representation is risky
because it causes opcodes as different as BRC and IFF to compare equal
at the IR level (luckily the back-end only ever uses one opcode from
each group, right now), and it prevents us from supporting
instructions that change their hardware representation across
generations, which will become a problem on Gen12+ platforms.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu: Encode and decode native instruction opcodes from/to IR opcodes.

Change brw_inst_set_opcode() and brw_inst_opcode() to call
brw_opcode_encode/decode() transparently in order to translate between
hardware and IR opcodes, and update the EU compaction code in order to
do the same as needed, so we can eventually drop the one-to-one
correspondence between hardware and IR opcodes.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu: Rework opcode description tables to allow efficient look-up by either HW or IR opcode.

This rewrites the current opcode description tables as a more compact
flat data structure.  The purpose is to allow efficient constant-time
look-up by either HW or IR opcode, which will allow us to drop the
hard-coded correspondence between HW and IR opcodes -- See the next
commits for the rationale.

brw_eu.c is now built as C++ source so we can take advantage of
pointers to member in order to make the look-up function work
regardless of the opcode_desc member used as look-up key.

v2: Optimize devinfo struct comparison (Caio)

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/eu: Fix up various type conversions in brw_eu.c that are illegal C++.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/eu: Split brw_inst ex_desc accessors for SEND(C) vs. SENDS(C).

The brw_inst opcode accessors are going away in one of the following
commits.  We could potentially replace them with the new helpers that
do opcode remapping, but that would lead to a circular dependency
between brw_inst.h and brw_eu.h.  This way we also avoid ordering
issues that can cause the semantics of the ex_desc accessors to change
depending on whether the ex_desc field is set after or before the
opcode instruction field.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/fs: Fix constness of implied_mrf_writes() argument.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>