systemc: Import tests from the Accellera systemc distribution.

Change-Id: Iad76b398949a55d768a34d027a2d8e3739953da6
Reviewed-on: https://gem5-review.googlesource.com/10845
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Add the Accellera implementation for the data type classes.

These files have been cleaned up style wise, and some macros have been
resolved like they were for the header files.

Change-Id: I447e5311961036847e7da0c5a86c0da25a633010
Reviewed-on: https://gem5-review.googlesource.com/10844
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

Systemc: Port over all of the systemc "datatype" headers.

These are the headers originally written by Accellera with a few
modifications. Most significantly, I went through and mostly (but not
entirely) manually editted them to conform to gem5 style and to be
more self consistent. Second, I resolved some macros which optionally
select features. I removed support for deprecated functions, and
otherwise enabled everything.

The actual implementation behind these headers will also be ported
over, but in a subsequent change.

Change-Id: I203d3f6c8a3af9120b946001d01defbb0643a6b6
Reviewed-on: https://gem5-review.googlesource.com/10843
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Stub out all the standard utilility classes and functions.

Change-Id: I9e9724edb6281e0b0a6bae5546b0ede77d295c12
Reviewed-on: https://gem5-review.googlesource.com/10841
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: Don't fail to initialise PMU if BP is missing

The branch predictor currently assumes that each CPU has a branch
predictor. This isn't true in some cases (e.g., KVM, Atomic).

Change-Id: I61e80dca940c2dadba1b812449691c9dba1c06d9
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11520
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-riscv: Add xret instructions

This patch adds the uret, sret, and mret instructions for use with
returning from user-, supervisor-, and machine-level code, respectively.
These instructions read the STATUS register to determine the previous
privilege level and modify it to re-enable interrupts at the old
privilege level. These instructions can only be executed at the
corresponding privilege level or higher.

Change-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9
Reviewed-on: https://gem5-review.googlesource.com/11136
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Robert Scheffel <robert.scheffel1@tu-dresden.de>

arch-riscv: Add support for trap value register

RISC-V has a set of CSRs that contain information about a trap that was
taken into each privilegel level, such as illegal instruction bytes or
faulting address.  This patch adds that register, modifies existing
faults to make use of it, and adds a new fault for future use with
handling page faults and bad addresses.

Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551
Reviewed-on: https://gem5-review.googlesource.com/11135
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

arch-riscv: Add support for fault handling

This patch adds support for handling RISC-V faults, including tracking
current and previous execution privilege, correctly switching to
the privilege mode specified by CSRs, and setting/storing the PC.  It
also includes changes introduced by patch #9821, which disables
interrupts during handling of a fault.

Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9
Reviewed-on: https://gem5-review.googlesource.com/9161
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

misc: Update CONTRIBUTING with gerrit changes

Change-Id: I39b5a784a056195a5e71fd21b3abb5fc91ab70e7
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/11872

base: Fix ucontext compilation error for macOS

ucontext functions (like getcontext, setcontext etc) have been marked
as deprecated and are hence hidden in latest macOS releases.
This patch uncovers them; warnings wil be produced but compilation
won't fail since -Wno-error=deprecated-declarations flag is currently
used.

Change-Id: Ic10e6f77a38875828b1891eaed2f0626ecffff67
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11729
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Warn when (un)serializing a traffic generator

When checkpointing a system with a traffic generator, a warning is
produced so that the user is reminded serialization does not keep all
the traffic generator internal state.

Change-Id: I3c49c912c9ff3a4208f55b2da0a88fc694147280
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11831
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Allow creation of traffic gen from generic SimObjects

This patch allows to instantiate a Traffic generator starting from a
generic SimObject, so that linking to a BaseTrafficGen only is no longer
mandatory. This permits SimObjects different than a BaseTrafficGen to
instantiate generators and to manually specify the MasterID they
will be using when generating memory requests.

Change-Id: Ic286cfa49fd9c9707e6f12a4ea19993dd3006b2b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11789
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: TempCacheBlk allocates and destroys its own data

This change is because I want to make CacheBlk::data private, so that
I can track all the places which write to it. But to keep that commit
smaller (it is pretty big, because of all the places which might
change it), I have split this into a commit of its own.

Change-Id: I15a2fc1752085ff3681f5c74ec90be3828a559ea
Reviewed-on: https://gem5-review.googlesource.com/11829
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

systemc: Flesh out the sc_port implementation slightly.

This makes other files compile because it changes the relationship
between constructors,etc., slightly.

Change-Id: I8d9a6e12ec640a82da166fe05c4f5e91f3f608de
Reviewed-on: https://gem5-review.googlesource.com/10840
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Stub out the predefined channels.

Change-Id: Ie030aad26875bd49e54981ec1e9076b7b5af6630
Reviewed-on: https://gem5-review.googlesource.com/10839
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Add systemc and systemc.h header files.

These are the header files as defined by the standard, although some
predefined channel types and most of the sc_dt namespace have yet to be
stubbed out, and so those portions are excluded.

Change-Id: Ic70f887c06e591974a4265c820eb0fdfa740d19a
Reviewed-on: https://gem5-review.googlesource.com/10838
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Stub out the sc_spawn related classes and functions.

Change-Id: I79f695cca97aaae9af324eb18cab073f42f0a193
Reviewed-on: https://gem5-review.googlesource.com/10837
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Stub out the sc_process_handle class.

Change-Id: I2250ccb369e0a5f2b9172d35662a9ce5e41ab1c1
Reviewed-on: https://gem5-review.googlesource.com/10836
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Seperate the "external" header interface.

Most (but not all) of the SystemC headers are part of the "external"
interface that an existing, standard compliant module would include
through <systemc.h> or <systemc>. Since those follow slightly different
rules (relative includes, no gem5 includes), this change separates them
out so that they're easier to identify.

Also, this change moves the other files into a "core" subdirectory,
with the intention to add a "dt", aka data type, directory some time in
the future when those standard defined types are implemented.

Change-Id: Ida63f9cc0bc0431024d4dd691cc5b22b944a99a8
Reviewed-on: https://gem5-review.googlesource.com/10835
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Stub out the sc_module class and related functions.

Change-Id: I2c20717fe1f750bf7ae84de79726b1503ec6e1cd
Reviewed-on: https://gem5-review.googlesource.com/10834
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Add a stubbed out implementation of the sc_sensitive class.

This sc_sensitive class is mostly implementation defined, but has a
few standards defined methods.

Change-Id: I7157f6bfaaef38b5804b19a1de9f3f0aff08b697
Reviewed-on: https://gem5-review.googlesource.com/10833
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Add a stub implementation for sc_attr related classes.

Change-Id: I59ba11f71b5412643ea7026df91587fafa0c6fda
Reviewed-on: https://gem5-review.googlesource.com/10832
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu-o3: Missing freeing the heads of DepGraph in IQ squashing

Free the squahsed instructions' heads of DepGraph in IQ squashing

In a system with large register file (ex.2048), the number of
DynInst hits the hardcoded limit (1500). This is caused by
missing freeing the heads of DepGraph in IQ. IQ only clears
out the heads when instructions reach writeback stage.
If a instruction is squashed before writeback stage, its head of
dependency graph, which holds the instruction's DynInstPtr,
would not be cleared out. This prevents freeing the DynInst of the
squahsed instruction even after it is committed.

Change-Id: I05b3db93cb6ad8960183d7ae765149c7f292e5b3
Reviewed-on: https://gem5-review.googlesource.com/7481
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

systemc: Add a stubbed out sc_event_finder class.

The standard defines this class very loosely, and so there isn't much
in the stub definition.

Change-Id: I2f8d07927a4eb087235e345a09d5a4d4891413b5
Reviewed-on: https://gem5-review.googlesource.com/10831
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Implement a stub version of the sc_prim class.

Change-Id: Iad32f6e385e62dc10491783c1e5cdd5d9bfcc3e6
Reviewed-on: https://gem5-review.googlesource.com/10830
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Add stubbed out versions of sc_port and sc_export.

Change-Id: I04edb5da995212f9179eeb7a97486031eea71aff
Reviewed-on: https://gem5-review.googlesource.com/10829
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Add stubbed out versions of sc_event and related classes.

Change-Id: Id45c80cbb8774d8469d4df6ce7915161df977de0
Reviewed-on: https://gem5-review.googlesource.com/10828
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Add stubbed out versions of the sc_time functions.

Change-Id: Ie7e3eac0382dc2ed861eaa9ea53ab11069812db8
Reviewed-on: https://gem5-review.googlesource.com/10827
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Add the sc_nbdefs.hh header from Accellera.

This header defines the uint64 type alias needed for the sc_time class.

Change-Id: I7793dbfb98001796c8c8fe24f69fe7868249ff85
Reviewed-on: https://gem5-review.googlesource.com/10826
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Add a stub version of the sc_interface class.

Change-Id: Iad1da472e13b0e16ad4de03f456ca0a001e69b51
Reviewed-on: https://gem5-review.googlesource.com/10825
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Hook up sc_main.

sc_main is exported as a python method on the SystemC_Kernel class and
takes a series of string arguments. The internal c++ implementation
converts those arguments into the standard argc and argv and uses them
to call the standard SystemC version of that function.

A weak SystemC version of sc_main is provided so that systemc will
compile with or without a simulation provided version of that
function. The weak version just complains and dies.

Change-Id: Iad735536c37c8bc85d06cf24779f607ae4309b8b
Reviewed-on: https://gem5-review.googlesource.com/10824
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Partially implement the sc_module_name class.

This class is mostly implemented as defined by the spec, except that
it doesn't maintain the module name stack (which doesn't yet exist).

Change-Id: I05fdc4aa40fb0497b0165824baee87ebf01a7821
Reviewed-on: https://gem5-review.googlesource.com/10823
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Rename Packet::checkFunctional to trySatisfyFunctional

Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
  - calls Packet::checkFunctional
- MSHR::checkFunctional
  - calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
  - calls Packet::checkFunctional
- Queue<>::checkFunctional
  (of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
  - Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
  - calls Packet::checkFunctional
- WriteQueueEntry::TargetList
  - calls Packet::checkFunctional
- MemDelay::checkFunctional
  - calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
  - calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
  - calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
  - calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
  - calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem: Removed "using namespace std;" from src/mem/packet.cc

To avoid unintentional variable capture, all std calls must be
prefixed. These are the identifiers which are in the std
namespace (according to
https://en.cppreference.com/w/cpp/symbol_index), but that will remain
unprefixed with this change:

int8_t int16_t int32_t int64_t
uint8_t uint16_t uint32_t uint64_t

The (u)int types are included from the packet header file, which
includes <inttypes.h>, where they occur in the global namespace. They
are in the std namespace in <cinttypes>/<cstdint>.

There is an occurrence of "set" in this file, which is "Packet::set"
and not "std::set", so it is not prefixed with the std namespace

Change-Id: I7f6c0b61b09658e224fe31a9f73150b81861d6f8
Reviewed-on: https://gem5-review.googlesource.com/11809
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem: Fix off-by-one error in checkFunctional, and simplify it

There was an off-by-one error in the isRead() case, as `val_end` and
`func_end` pointed to the last byte to write to (not one past the last
byte), and thus `*_end - *_start` was not the length of the data to
memcpy.

This was correct in the case of

    val_start >= func_start && val_end <= func_end

where `overlap_size = size`, but if it were (as the other cases
suggest) `overlap_size = val_end - val_start`, then it would also be
off by one.

Also, the isWrite() case catered for this.

I simplified the four ifs into one case which uses min/max (this is
how I spotted the inconsistency).

Change-Id: Ib5c5da084652e752f6baf1eec56b51b4f0f5c95c
Reviewed-on: https://gem5-review.googlesource.com/11750
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Typo in comment: 'proceed' -> 'precede'

The writebacks happen before anything below, not after.

Change-Id: I7eaefbbf33aa17c496255dedd964a56118a28741
Reviewed-on: https://gem5-review.googlesource.com/11749
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev, arm: accept and ignore writes to GIC APRn registers

Otherwise the Linux kernel v4.17 boot fails with error:

Tried to write Gic cpu at offset 0xd0

Change-Id: Ie8063212c9e2b29e2e4766801b4b9538e9eccbf8
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11590
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Add a stub kernel SimObject.

The guts of this class will be added in later changes.

Change-Id: I3582c40f88f7d9ba6028a6f0a8ee5c32924a65bf
Reviewed-on: https://gem5-review.googlesource.com/10822
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

systemc: Add a stubbed out sc_object class.

Also add a SConsopt variable USE_SYSTEMC to hide systemc support until
it's usable.

Change-Id: Ibb37483432b147ee690a36bb5c8dd74f1c4c7ae4
Reviewed-on: https://gem5-review.googlesource.com/10821
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: Introduce ARMv8.1 Virtual Timer System Registers

Adding CNTHV_CTL_EL2, CNTHV_CVAL_EL2, CNTHV_TVAL_EL2 System Registers
into the decode tree. They are currently implemented as a generic timer
and produces a warning if accessed.

Change-Id: I1a23035d67f95eeac49d890283e9a0d58426d504
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11592
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Introduce RAS System Registers

Adding RAS Extension System Registers into the decode tree.  They are
currently unimplemented and produce a warning (not failure) if accessed.

Change-Id: I4baeded822c9582a2cb9d5277409b029eb00a962
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11591
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

configs: Update the DRAM sweep script to use PyTrafficGen

Instead of generating a text configuration, use the new Python-based
traffic generator.

Change-Id: I6fb88ec45b74bb87470aa265af18b5a2ff24c314
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11519
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Add a Python-enabled traffic generator

The current traffic generator relies on a configuration file that
describes a small machine to generate stimuli. This configuration file
is usually generated by the gem5 Python configuration. This creates an
unnecessary and fragile step.

This changeset introduces a Python-based trace module. When
instantiated, the module exposes a start method that takes an iterable
object as a parameter (e.g., a generator). The iterable object is
expected to represent a list of generators that will be run one after
the other. For example:

    system.tgen = PyTrafficGen()
    m5.instantiate()

    def trace():
        yield system.tgen.createIdle(1000)
        yield system.tgen.createExit(0)

    system.tgen.start(trace())

Change-Id: I58e60ca517e86c197859f4daaa67750066abdc1c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11518
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Support trace termination in BaseTrafficGen

Make the BaseTrafficGen handle cases where getNextPacket() can't find
a new packet and returns NULL. In that case, assume the generator has
run out of packets and switch to the next generator.

Change-Id: I5ca6ead550005812fb849ed9ce6b5007a65ddfa7
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11517
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Unify error handling for address generators

Unify error handling and create factory methods for address
generators.

Change-Id: Ic3ab705e1bb58affd498a7db176536ebc721b904
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11516
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Split the traffic generator into two classes

The traffic generator currently assumes that it is always driven from
a configuration file. Split it into a base class (BaseTrafficGen) that
handles basic packet generation and a derived class that implements
the config handling (TrafficGen).

Change-Id: I9407f04c40ad7e40a263c8d1ef29d37ff8e6f1b4
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11515

misc: Fix BaseCPU doxygen

Doxygen was stopping with #include "arch/null/cpu_dummy.hh" so the html
for BaseCPU was only the three functions defined in the dummy CPU. This
forces doxygen to skip this #include correctly.

Note: The file references for base_cpu still aren't quite right, but it's
better than it was.

Change-Id: Ifafe247df2511caee2569d534bd29348a5ce9e8e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/11649
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

arch-riscv: enable rudimentary fs simulation

These changes enable a simple binary to be simulated in full system mode.
Additionally, a new fault was implemented.
It is executed once the CPU is initialized.
This fault clears all interrupts and sets the pc to a reset vector.

Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Reviewed-on: https://gem5-review.googlesource.com/9061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-riscv: Fix the srlw and srliw instructions.

Change-Id: I14ccb0655819887db2306fee1188e1c83a991743
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/11669
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

base: Add a M5_PUBLIC and M5_LOCAL attribute macro

There are cases where we need to limit the symbol visibility to avoid
compilation errors. This is a problem for Python code that relies on
PyBind11 since recent versions enforce hidden symbols. As a
consequence, classes that have member variables from PyBind11 need to
be declared with the hidden attribute (or gem5 needs to be compiled
with -fvisibility=hidden).

Change-Id: I30e582fde494ff61ab7a596a595efc26a2952a5f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11513
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

python: Fix call bug in @cxxMethod when override is True

Change-Id: Ifa9efbd329fd01eb13100bc6690e651df2c12294
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Javier Setoain <javier.setoain@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11514
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Remove reduntant protobuf includes

Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

python: Fixup incorrect syntax in PyBind argument handler

Change-Id: Ie81104d89b554795ec1020d5ce4edcf28795eda8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11511
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem: Add a memory delay simulator

Add a memory system component that delays traffic. The base
functionality to delay packets is implemented in the abstract MemDelay
class. This class exposes three methods that control packet delays:

  * delayReq(pkt)
  * delayResp(pkt)
  * delaySnoopResp(pkt)

These methods should be specialized to implement delays for specific
packet types.

The class SimpleMemDelay uses the MemDelay base class to implement
constant delays for read/write requests and responses.

The intention is that these classes can be used for rapid prototyping
of components that add a small fixed delay and the same throughput as
the interconnect. I.e., any buffering done in the base class will be
small and proportional to the introduced delay.

Change-Id: I158cb85f20e32bfdbcbfed66a785b4b2dd47b628
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nicholas Lindsey <nicholas.lindsay@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11521
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Fix incorrect t{0,1}sz field in TTBCR

The t0sz and t1sz fields in TTBCR only are only three bits wide unlike
aarch64 which has a 6-bit wide field. The higher bits of the
aarch64-equivalent should be treated as RES0.

Change-Id: I60df73105c34500c0348a44a491c117e9b28f18f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11589
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Add an asymmetrical Coroutine class

This patch is providing gem5 a Coroutine class to be used for
instantiating asymmetrical coroutines. Coroutines are built on top of
gem5 fibers, which makes them ucontext based.

Change-Id: I7bb673a954d4a456997afd45b696933534f3e239
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11195
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

gpu-compute: Remove unneeded Request::setVirt call

This sets the members of a Request object to the values they
already hold, except the atomicOpFunctor which is set to
nullptr. This call introduces a bug for atomics and is not
useful for non-atomic requests. This changeset is also
adding the wave PC and instruction sequence number to the
Request object.

Change-Id: I62f7b4a597483b0aa848a0cfbc72181e1063f56a
Reviewed-on: https://gem5-review.googlesource.com/11549
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

python: Add support for multiplying proxies to compatible Param

Previously we allowed multiplications between proxy Param and
compatible constants (int, long, float). This change extends this
functionality and adds support for multiplying with between proxy
Param and compatible proxy Param.

Change-Id: I23a083881ae4d770e818895b893534767cd2472d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11510
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

scons: Generalize building binaries.

Building gem5 binaries or regression test binaries needs to be done
from within the make_env function which builds an environment for each
flavor of build (opt, fast, debug, etc.). That makes it impossible to
add new types of binaries without modifying the central SConscript.

This change refactors how binaries are set up so that the class that
represents them handles the details of how the binary should be built.
Also, a metaclass and some lists track types of binaries and individual
instances of binaries so that they can be iterated over automatically
in make_env.

Each new executable class can define a declare_all class function which
calls declare() on individual instances. declare_all is a place to do
any processing that only has to happen once (for instance specializing
the environment) for a particular family of executables.

Change-Id: I8a6ee9438280cd67e6c0b92ca28738a53cb16950
Reviewed-on: https://gem5-review.googlesource.com/10915
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

syscall_emul: adding symlink system call

Change-Id: Iebda05c130b4d2ee8434cad1e703933bfda486c8
Reviewed-on: https://gem5-review.googlesource.com/11490
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

syscall_emul: adding link system call

Change-Id: If8922c2233bbe1f6fce35f64d1a44b91d2cfeed2
Reviewed-on: https://gem5-review.googlesource.com/11489
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

mem-cache: Promote deferred targets on cache clean responses

While a cache clean operation is pending, all requests to the
corresponding block get deferred. When the response of a cache clean
operation is received, if the block is present and the response is not
invalidating, we can service all deferred targets that didn't require
writable. This change implements this functionality.

Change-Id: Ief47e74d07749a6a9736ab450eb46eefa53464a2
Reviewed-on: https://gem5-review.googlesource.com/11018
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Promote targets that don't require writable

Until now, all deferred targets of an MSHR would be promoted together
as soon as the targets were serviced. Due to the way we handle cache
clean operations we might need to promote only deferred targets that
don't require writable, leaving some targets as deferred. This change
adds support for this selective promotion.

Change-Id: I502e523dc9adbaf394955cbacea8286ab6a9b6bc
Reviewed-on: https://gem5-review.googlesource.com/11017
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix promoting of targets that need writable

There are cases where a request which does not need a writable copy
gets an response upgraded reponse and fills in a writable copy. When
this happens, we promote deferred MSHR targets that were deferred
because they needed a writable copy to service them immediately.

Previously, we would uncoditionally promote deferred targets. Since
the deferred targets might contain a cache invalidation operation, we
have to make sure that any targets following the cache invalidation is
not promoted.

Change-Id: I1f7b28f7d35f84329e065c8f63117db21852365a
Reviewed-on: https://gem5-review.googlesource.com/11016
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Selectively clear downstream pending

Until now, all deferred targets of an MSHR would be promoted together
as soon as the targets were serviced. When we promote deferred targets
we also clear the downstreamPending flag.

Due to the way we handle cache clean operations we might need to
promote only deferred targets that don't require writable, leaving
some targets as deferred. To allow for partial target promotion, this
change adds support for clearing the downstreamPending only for a
subset of a TargetsList.

Change-Id: Id06953643ba9a975ebacc76ac10215441e264e74
Reviewed-on: https://gem5-review.googlesource.com/11015
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

SConstruct: additional message for the error checking of the python 2.7 headers

One of the most common errors during the installation of gem5 is the one
related to the failure of the check of the Python2.7 headers in the
SConstruct file. In some cases the headers are correctly installed, but a
wrong selection of the C compiler can make this check fail. This commit
wants to add some useful information this error message.

Change-Id: I0d087ad01c6e4cca3559f23070c37b5c13600962
Reviewed-on: https://gem5-review.googlesource.com/11389
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: AArch32 execution triggering AArch64 SW Break

AArch32 Software Breakpoint (BKPT) can trigger an AArch64 fault when
interprocessing if the trapping conditions are met.

Change-Id: I485852ed19429f9cd928a6447a95eb6f471f189c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11197
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: BadMode checking if corresponding EL is implemented

The old utility function called badMode was only checking if the mode
passed as an argument was a recognized mode. It was not checking if the
corresponding mode/EL was implemented. That function has been renamed to
unknownMode and a new badMode has been introduced.  This is used by the
cpsrWriteByInstruction function.  In this way any try to change the
execution mode won't succeed if the mode hasn't been implemented.

Change-Id: Ibfe385c5465b904acc0d2eb9647710891d72c9df
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11196
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

base: Add a class which encapsulates Fibers.

This class encapsulates the idea of a Fiber in such a way that other
implementations can be substituted in in the future. This
implementation uses the ucontext family of functions.

This change also adds a new unit test which exercises the new class. It
creates three new fibers which accept a sequence of other fibers to
switch to, one after the other. The main test function switches to
the these fibers which switch with each other and occasionally back to
the main fiber. Each time a test fiber is activated, it checks against
a list which shows the correct order for the fibers to run in. When the
main fiber gets control, it makes sure that list has been progressed
through by the correct amount.

Change-Id: I1fc2afa414b51baaa91e350a4ebc791d989f0b8a
Reviewed-on: https://gem5-review.googlesource.com/10935
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Use the canonical way of iterating over a dictionary

Instead of using a convoluted getattr call, use the conventional
iteritems() interface.

Change-Id: I6d6bbccf865f8a0e8ff0767914157a7460099b09
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10782
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

dev-arm: Use recurseDeviceTree instead of custom in platform

The platform code uses a custom mechanism to traverse the object
hierarchy when generating device trees. This is highly undesirable
since this breaks for common cases such as when SimObjects are stored
in a list.

Change-Id: I1b968e5fa1db62f1456e3c0ac3de47ab1299e58d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10781
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

cpu: Fix bug introduced by RequestPtr type change

Missing buffer allocation in mwaitAtomic.

Change-Id: Ifccb6df2427df8b0daac5ee6a99e5cca0b20825e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11469
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

base: Fix includes in AddrRangeMap header file

Change-Id: I4bdd6cf7c8d22219c0582ab206ec8372a4357759
Reviewed-on: https://gem5-review.googlesource.com/11429
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix TempCacheBlock insert

TempCacheBlock insert() had a different signature than the parent class
which caused an error on clang. This matches the signature with default
zero values.

Change-Id: Ic096914497f3d17e88295c9e65a04d76fdddf365
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/11349
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Use address range to find the right physical address

Previously, we used the start address to determine the right physical
memory while servicing memory requests. This change uses the full
address range to correctly determine the right physical memory and
expose bugs where requests might not fully map to a single physical
memory.

Change-Id: I183d7552918106000f917a62ceb877511ff0ff71
Reviewed-on: https://gem5-review.googlesource.com/11118
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Use address range to find the destination port in the xbar

Previously the xbar used the start address to lookup the port map and
determine the right destination of an incoming packet. This change
uses the full address range to correctly determine the right master.

Change-Id: I5118712c43ae65aba64e71bf030bca5c99770bdd
Reviewed-on: https://gem5-review.googlesource.com/11117
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Use the caching in the AddrRangeMap class in PhysicalMemory

Use it instead of custom implemented caching.

Change-Id: Ie21012a77a3cb6ce57f34f879fa391678913896a
Reviewed-on: https://gem5-review.googlesource.com/5244
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Use the caching built into AddrRangeMap in the xbar

Use that instead of caching built into the crossbar.

Change-Id: If5a5355a0a1a6e532b14efc88a319de4c023f8c1
Reviewed-on: https://gem5-review.googlesource.com/5243
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Build caching into the AddrRangeMap class

Rather than have each consumer of the AddrRangeMap implement caching
lookups on their own, this change adds a centralized mechanism to the
AddrRangeMap class itself.

Some benefits of this approach are that the cache handles deleted
entries correctly/automatically, the cache is maintained by
adding/removing entries from a linked list rather than moving elements
in an array and checking valid bits, and it's easy to enable in places
which might otherwise not bother with caching. The amount of caching
is tunable to balance overhead with improved lookup performance.

Change-Id: Ic25997e23de4eea501e47f039bb52ed0502c58d2
Reviewed-on: https://gem5-review.googlesource.com/5242
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

base, mem: Disambiguate if an addr range is contained or overlaps

We need to determined whether an address range is fully contained or
it overlaps with an address range in the address range in the mmap. As
an example, we use address range maps to associate ports to address
ranges and we determine which port we will forward the request based
on which address range contains the addresses accessed by the
request. We also need to make sure that when we add a new port to the
address range map, its address range does not overlap with any of the
existing ports.

This patch splits the function find() into two functions contains()
and intersects() to implement this distinct functionality. It also
changes the xbar and the physical memory to use the right function.

Change-Id: If3fd3f774a16b27db2df76dc04f1d61824938008
Reviewed-on: https://gem5-review.googlesource.com/11115
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix support for secure blocks in the FALRU cache

Fully associative caches use an unordered map to enable efficient
lookups of existing blocks. Previously this map was indexed using the
tag of the block. Security extentions allow secure and non secure
versions of a block with the same tag to co-exist in the cache. This
patch amends the block map to allow correct lookups for FALRU caches.

Change-Id: Iccf07464deab56d1d270bae14bb3b154047e3556
Reviewed-on: https://gem5-review.googlesource.com/11309
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Initialize CacheBlk data pointer

Initialize CacheBlk's data pointer as a nullptr.

Change-Id: Ice85b4b11495cad4b0a160ccb9efe1be673e57e2
Reviewed-on: https://gem5-review.googlesource.com/11097
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Forward declare ReplaceableEntry

Forward declare ReplaceableEntry where in classes where pointers
to it are used.

Change-Id: I49c08d36442a563d7a6b4c9bcd7eba3591d29b60
Reviewed-on: https://gem5-review.googlesource.com/11096
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

dev-arm: Fix the address range for some I/O devices

Previously, many devices were incorrecty configured to respond to an
address range of size 0xfff. This changes fixes this and sets it to
0x1000.

Change-Id: I4b027a27adf60ceae4859e287d7f34443b398752
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11116
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tests,style: add RISC-V assembly tests

This patch adds a subset (rv64*) of RISC-V assembly tests. The original
riscv-test project can be found here:
https://github.com/riscv/riscv-tests. The riscv-test project is under the
BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE)
and is maintained separately from gem5 project.

The tests have been slightly modified to work in gem5 SE mode:

(1) Removed a trap handler used in riscv-tests for bare-metal systems

(2) Instead of throwing an exception, the tests call the exit syscall
with
the exit code of
    - '0' if SUCCESS
    - Failed test case's number (non-zero) if FAILURE
The exit code can be captured after a simuation completes.

In addition to original RISC-V assembly tests, this patch adds several
assembly tests specifically for AMO, LR, SC and system calls. Those
tests target a multi-core system.

(1) rv64uamt: multi-threaded tests for A-extension instructions

(2) rv64samt: multi-threaded tests for clone and futex system calls

This patch also makes the style checker ignore RISC-V assembly test
directory. The assembly tests are maintained in an external project
that does not follow the gem5 coding conventions.

Please find more details in the README file included in this patch.

Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0
Reviewed-on: https://gem5-review.googlesource.com/6703
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

sim: Add a SimObject python field which overrides the default c++ base.

The base for the c++ version of python SimObject classes is normally
inferred from the c++ version of the python base. There are some
specific cases where that isn't desired. This change makes it possible
to override the default behavior.

Change-Id: I2438dad767e2f56823bad42b3e6c7714ce97ef79
Reviewed-on: https://gem5-review.googlesource.com/10662
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Prevent suspended TimingSimple CPUs from fetching next instructions

In TimingSimpleCPU model, when a CPU is suspended by a syscall (e.g.,
futex(FUTEX_WAIT)), the CPU waits for another CPU to wake it up
(e.g., FUTEX_WAKE operation). While staying Idle, the suspended CPU
should not try to fetch next instructions after the syscall.

This patch added a status check before a CPU schedule a fetch event
after a fault is handled.

Change-Id: I0cc953135686c9b35afe94942aa1d0b245ec60a2
Reviewed-on: https://gem5-review.googlesource.com/8181
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

cpu: add a new instruction type 'Atomic'

This patch adds a new flag named 'Atomic' to support ISA implementations
that use AtomicOpFunctor to handle atomic instructions instead of a
pair of locking load and unlocking store.

Change-Id: I1fbee6e54432396cb49dfc59ad9006b75812d115
Reviewed-on: https://gem5-review.googlesource.com/8187
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch: support issuing Atomic Mem Operation (AMO) requests

This patch adds two new functions named amoMemAtomic used in Atomic CPU
model and initiateMemAMO used in Timing CPU models to issue AMO requests
to the memory system.

Change-Id: I962bdc0e5f25b72c170d96ebc136f29a2b230d5e
Reviewed-on: https://gem5-review.googlesource.com/8186
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

base,mem: Support AtomicOpFunctor in the classic memory system

AtomicOpFunctor can be used to implement atomic memory operations.
AtomicOpFunctor is captured inside a memory request and executed directly
in the memory hierarchy in a single step.

This patch enables AtomicOpFunctor pointers to be included in a memory
request and executed in a single step in the classic cache system.

This patch also makes the copy constructor of Request class do a deep
copy of AtomicOpFunctor object. This prevents a copy of a Request object
from accessing a deleted AtomicOpFunctor object.

Change-Id: I6649532b37f711e55f4552ad26893efeb300dd37
Reviewed-on: https://gem5-review.googlesource.com/8185
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

ruby: Revamp standalone SLICC script

There was some bitrot in the standalone SLICC script (util/slicc and
src/mem/slicc/main.py). Fix the changes to the SLICC interface and also
add some better documentation.

Change-Id: I91c0ec78d5072fba83edf32b661ae67967af7822
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/10561
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Adapting IllegalExecution fault for AArch32

The Illegal Execution fault triggered by the setting of processor state
PSTATE.IL happens in AArch32 as well and takes the form of UNDEFINED
exception fault.  We are hence copying the UndefinedInstruction AArch32
fields into the IllegalInstSetStateFault.

Change-Id: Ibb7424397c2030ea5d010577c530277a27036aea
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10814
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Add Illegal Execution flag to PCState

This patch moves the detection of the Illegal Execution flag (PSTATE.IL)
from the tlb translation stage (fetch) to the decoding stage.  This is
done by adding the illegalExecution field to the PCState.

Change-Id: I9c1c4e9c6bd5ded905c1d56b3034e4e9322582fa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10813
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Read APSR in User Mode

This patch substitutes reads to the CPSR in user mode (MRS CPSR) to
reads to APSR (Application Program Status Register).
This is the user level alias for the CPSR. The APSR is a subset of the
CPSR.

Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10602
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

system-arm: Split the VExpress_GEM5_V1 base dts

With the introduction of the new DPU model, we need different
variations of the VExpress_GEM5_V1 platform. This splits the platform
dtsi file into a separate file for the base platform and the
HDLCD-based platform. This matches the hierarchy in RealView.py.

Change-Id: Id02380122655b5d3aa3548a703fdef178bba17d9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11035
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

dev-arm: Add new VExpress_GEM5_V1_Base Platform

Add a new VExpress_GEM5_V1_Base Platform which configures basic on
chip devices. The original VExpress_GEM5_V1 will inherit the Base and
add more on chip devices (currently only the HDLCD). This change will
make it possible to create variations of the base platform with
different devices.

Change-Id: I21f9bf4f6217d87e811ff777f630122593eef013
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10807
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

cpu-minor: Remove redundant thread startup call

Don't call startup() twice on each of the threads.

Change-Id: Ibe3d1f25c4fdff291ee310abb9bcad3b184bab20
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11037

dev-arm: Remove deprecated GIC test interfaces

Change-Id: I4c5203b216387d9a4f041c7a00caea926e5cfca6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10810

tests: Make "UnitTest"s more like GTest so they can be in other dirs.

The original implementation of UnitTest forced all the output binaries
to live in the unittest directory, effectively forcing a flat
namespace, and seperating the tests from the things they were supposed
to be testing.

This changes makes them work more like the newer GTest tests in that
they can be based out of whatever directory makes sense, although
they're currently all still in unittest for the time being.

This change also gets rid of automatically tagging the sources
associated with a test with the tests name. The first reason for that
was that this also forced a flat namespace, since the tests names
didn't have any reference to the test's path. Second, this way of
pulling in additional files wasn't necessary any more, now that the
UnitTest sources could be source filters like they can be for GTests.

Change-Id: I3d96ed766ac5170842dbd6daee39f2873bcd6c75
Reviewed-on: https://gem5-review.googlesource.com/10701
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Remove unnecessary cast in SectorTags::findVictim

Removes an uneccessary cast that also caused an unused variable
error (due to -Werror) when compiling .fast targets.

Change-Id: Ic043f462925e7eaa7b691455f1d9e08a1c101980
Reviewed-on: https://gem5-review.googlesource.com/11119
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>