r600g/radeonsi: send endian info to format translation functions

Because r600 GPUs can't do swap in their DB unit, we need to disable
endianess swapping for textures that are handled by DB.

There are four format translation functions in r600g driver:

- r600_translate_texformat
- r600_colorformat_endian_swap
- r600_translate_colorformat
- r600_translate_colorswap

This patch adds a new parameters to those functions, called
"do_endian_swap". When running in a big-endian machine, the calling
functions will check whether the texture/color is handled by DB -
"rtex->is_depth && !rtex->is_flushing_texture" - and if so, they will
send FALSE through this parameter. Otherwise, they will send TRUE.

The translation functions, in specific cases, will look at this parameter
and configure the swapping accordingly.

v4:
evergreen_init_color_surface_rat() is only used by compute and don't
handle DB surfaces, so just sent hard-coded FALSE to translation
functions when called by it.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: add ability to use essl 3.20

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>

main: select ES3.2 version when all extensions are available

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>

tgsi: pass a shader type to the machine create and clean up.

There was definitely bugs here mixing up the PIPE_ and TGSI_ defines,
hopefully they didn't cause any problems, since mostly it was special
cases for GEOMETRY.

This clarifies at shader machine create what type of shader this
machine will execute. This is needed also for compute shaders where
we don't want to allocate inputs/outputs.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

gallium/tgsi: move tgsi_exec.h header out of draw_context.h

It gets annoying that changing the tgsi exec rebuilds the state
tracker unnecessarily. Putting this include into draw_gs.h which
uses it causes a lot less rebuilds.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

gallivm: make sampling more robust against bogus coordinates

Some cases (especially these using fract for coord wrapping) did not handle
NaNs (or Infs) correctly - the following code assumed the fract result
could not be outside [0,1], but if the input is a NaN (or +-Inf) the fract
result was NaN - which then could produce out-of-bound offsets.

(Note that the explicit NaN behavior changes for min/max on x86 sse don't
result in actual changes in the generated jit code, but may on other
architectures. Found by looking through all the wrap functions.)

This fixes https://bugs.freedesktop.org/show_bug.cgi?id=94955

No piglit changes.

(v2: fix min/max typo in coord_mirror, add comment)

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Tested-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

radeonsi: fix missing include for Elements.

Since u_blitter.h no longer defines this.

Signed-off-by: Dave Airlie <airlied@redhat.com>

nvc0: bump the amount of shared memory per MP on Maxwell

According to the CUDA compute capability version, GM10x can expose
64KB of shared memory while GM20x can use 96KB.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

r600: fix missing include for Elements macro

This got removed from u_blitter.h and we were taking it from
there, this should just move to ARRAY_SIZE eventually.

Signed-off-by: Dave Airlie <airlied@redhat.com>

gm107/ir: s/invalid load/invalid store/

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a3xx: remove unused fxn

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: convert over to ralloc

The home-grown heap scheme (which is ultra-simple but probably not good
to always allocate and memset such a chunk of memory up front) was a
remnant of fdre (where the ir originally came from).  But since we have
ralloc in mesa, lets just use that instead.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

mesa/st: log some additional invalid-fbo cases

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

freedreno: honor handle->offset

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: disallow cat4 immed src

Normally this would never happen (constant-propagation in NIR would
eliminate the instruction), except it does happen for 'undef' which
we turn into immed 0.0 for bookkeeping purposes.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: add render-target formats

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: update generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: reduce line width for deqp further

See a7eb12d0.. but that wasn't restrictive enough.  Fixes
dEQP-GLES3.functional.rasterization.primitives.line_strip_wide, and
similar

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: fix sin/cos

We seem to need range reduction to get sane results.  Fixes glmark2
jellyfish bench, and a whole bunch of
dEQP-GLES3.functional.shaders.builtin_functions.precision.{sin,cos,tan}.*

v2: squashed in android build fixes from Rob Herring

Signed-off-by: Rob Clark <robclark@freedesktop.org>

i965: Unroll SIMD16 DDY_FINE on Sandybridge.

This fixes 10 dEQP-GLES3 subtests:
dEQP-GLES3.functional.shaders.derivate.dfdy.texture.float_nicest.*.

Matt noticed that our Piglit tests for this use even numbered registers,
while the failing dEQP tests use odd numbered registers.  We believe
that it works for even numbered registers, but not otherwise.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

docs: update the instructions for getting a git account

Reviewed-by: Matt Turner <mattst88@gmail.com>

docs: update link to Intel's graphics website

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa/gles: Allow format GL_RED to be used with MESA_FORMAT_R_UNORM

If the bound framebuffer has a format of MESA_FORMAT_R_UNORM, then
IMPLEMENTATION_COLOR_READ_FORMAT will return GL_RED. This change
applies to OpenGLES contexts where additional restrictions are placed
on the formats that are allowed to be supported.

Fixes OpenGLES 3.1 CTS tests:
 * ES31-CTS.texture_border_clamp.sampling_texture.Texture2DDC16
 * ES31-CTS.texture_border_clamp.sampling_texture.Texture2DDC16Linear
 * ES31-CTS.texture_border_clamp.sampling_texture.Texture2DDC32F
 * ES31-CTS.texture_border_clamp.sampling_texture.Texture2DDC32FLinear

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

svga: eliminiate unnecessary constant buffer updates

Currently if the texture binding is changed, emit_fs_consts()
is triggered to update texture scaling factor for
rectangle texture or texture buffer size in the constant buffer.
But the update is only relevant if the texture binding includes
a rectangle texture or a texture buffer.

To eliminate the unnecessary constant buffer updates due to other texture
binding changes, a new flag SVGA_NEW_TEXTURE_CONSTS will be used
to trigger fragment shader constant buffer update when a rectangle texture
or a texture buffer is bound.

With this patch, the number of constant buffer updates in Lightsmark2008
reduces from hundreds per frame to about 28 per frame.

Reviewed-by: Brian Paul <brianp@vmware.com>

svga: mark the texture dirty for write transfer map only

Instead of unconditionally mark the texture subresource dirty at transfer map,
we'll set the dirty bit for write transfer only.

Tested with lightsmark2008 and glretrace.

Reviewed-by: Brian Paul <brianp@vmware.com>

svga: fix assert with PIPE_QUERY_OCCLUSION_PREDICATE for non-vgpu10

With this patch, when running in hardware version 11, we'll use
SVGA3D_QUERYTYPE_OCCLUSION query type for PIPE_QUERY_OCCLUSION_PREDICATE
and return TRUE if samples-passed count is greater than 0.

Fixes glretrace/solidworks2012_viewport running in hardware version 11.

Reviewed-by: Brian Paul <brianp@vmware.com>

svga: minimize surface flush

Currently, we always do a surface flush when we try to establish
a synchronized write transfer map. But if the subresource has not
been modified, we can skip the surface flush. In other words,
we only need to do a surface flush if the to-be-mapped subresource
has been modified in this command buffer.

With this patch, lightsmark2008 shows about 15% performance improvement.

Reviewed-by: Brian Paul <brianp@vmware.com>

glapi: fix _glapi_get_proc_address() for mangled function names

In the dispatch table, all functions are stored without the "m" prefix.
Modify code so that OSMesaGetProcAddress works both with gl and mgl
prefixes. Similar to
https://lists.freedesktop.org/archives/mesa-dev/2015-September/095251.html

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94994
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

util/blitter: use ARRAY_SIZE macro

And remove local definition of Elements() macro.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

svga: s/Elements/ARRAY_SIZE/

Standardize on the later macro rather than a mix of both.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: whitespace and formatting fixes in svga_pipe_rasterizer.c

svga: whitespace and formatting fixes in svga_pipe_depthstencil.c

svga: whitespace and formatting fixes in svga_pipe_sampler.c

gallium/util: initialize pipe_framebuffer_state to zeros

To silence a valgrind uninitialized memory warning.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94955
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

util/cache: add comments, fix formatting

i965: Mark URB reads as volatile.

They can be affected by URB writes.

In the upcoming scalar TCS backend, this prevents read-modify-write
cycles from being broken by CSE removing reads.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

i965: Make a few tessellation related functions non-static.

Also, move them to brw_shader.cpp so they're in a location for code
used by both the vec4 and fs worlds.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

svga: separate HUD counters for state objects

Count depth/stencil, blend, sampler, etc. state objects separately
but just report the sum for the HUD.  This change lets us use gdb to
see the breakdown of state objects in more detail.

Also, count sampler views too.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

st/omx: Fix resource leak on OMX_ErrorNone

Avoid leaking buffer allocated for task if an error has occured.

Coverity id: 1213929
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

isl: remove ffs function that conflicts with system headers

Remove a wrapper around __builtin_ffs that conflicts with system
headers on OpenBSD and perhaps elsewhere:

isl_priv.h:44: error: conflicting types for 'ffs'

v2: include strings.h to ensure prototype is found

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

gallium: use unreachable instead of asserts

Avoids warnings in release builds.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

anv: fix warnings in release build

Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings
in release build.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

isl: fix warnings in release build

Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings
in release build.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

spirv: fix warning in release build

Mark variable MAYBE_UNUSED to avoid unused-but-set-variable warning in
release build.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

gallium: fix warnings in release build

Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings
in release build.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

glsl: fix warning in release build

Mark variable MAYBE_UNUSED to avoid unused-but-set-variable warning in
release build.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

util: add MAYBE_UNUSED for config dependent variables

This is mostly for variables that are only used in asserts and cause
unused-but-set-variable warnings in release builds. Could just use
UNUSED directly, but MAYBE_UNUSED should be less confusing and is
similar to what the Linux kernel has.

And yes __attribute__((unused)) can be used on variables on both GCC 4.2
(oldest supported by mesa) and clang 3.0 (just some random old version,
not sure what's the minimum for mesa).

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

nouveau: codegen: combineLd/St do not combine indirect loads

combineLd/St would combine, i.e. :

st  u32 # g[$r2+0x0] $r2
st  u32 # g[$r2+0x4] $r3

into:

st  u64 # g[$r2+0x0] $r2d

But this is only valid if r2 contains an 8 byte aligned address,
which is not guaranteed for compute shaders

This commit checks for src0 dim 0 not being indirect when combining
loads / stores as combining indirect loads / stores may break alignment
rules.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/ir3: relax restriction in grouping

Currently we were two restrictive, and would insert an output move in
cases like: MOV OUT[0], IN[0].xyzw

Loosen the restriction to allow the current instruction to appear in the
neighbor list but only at it's current possition.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: fix small memory leak

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: fix small RA bug

Normally the offset in the group would be the same, but not always.  For
example, in a sam(w) which only writes the 4th component.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: better workaround for astc+srgb

This *seems* like a hw bug, and maybe only applies to certain a4xx
variants/revisions.  But setting the SRGB bit in sampler view state
(texconst0) causes invalid alpha for ASTC textures.  Work around this
setting up a second texture state and using that to sample alpha
separately.

This way, srgb->linear conversion happens in hw *prior* to
interpolation.

This fixes 546 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb*

Signed-off-by: Rob Clark <robclark@freedesktop.org>

Revert "freedreno/a4xx: lower srgb in shader for astc textures"

Better workaround in the following patch.

This reverts commit 899bd63acefd49a668e11c42d2ad92fa55aa157d.

freedreno/a4xx: blend state no longer depends on fb state

Signed-off-by: Rob Clark <robclark@freedesktop.org>

Revert "st/dri: add 32-bit RGBX/RGBA formats"

This reverts commit ccdcf91104a5f07127b5b8d8570b5c4bbcf86647.

It breaks most KDE apps, because DRI doesn't support the RGBA component
ordering.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95071

genxml: use PYTHON3

Allows the build to work when the python3 binary is not "python3".

v2: remove x bit from the script at Emil's suggestion

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/tex_image: Flush certain subnormal ASTC channel values

When uploading a linear, void-extent, ASTC LDR block on Skylake, we are
required to flush to zero the UNORM16 channel values that would be
denormalized. This is specifically required for the values: 1, 2, and 3.

Fixes the 14 failing tests in:
   dEQP-GLES3.functional.texture.compressed.astc.void_extent_ldr.*

v2: Split out flushing function (Kristian Høgsberg)
v3: Map with READ instead of INVALIDATE (Kenneth Graunke)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

configure.ac: search for and set PYTHON3

src/intel/genxml/gen_pack_header.py requires python3.

v2: check for python3.5 as well

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp: Enable for buffer resolves

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94181

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp: Enable for normal color clears

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp: Fix clear code for ignoring colormask for XRGB formats on Gen9+

This is equivalent of 73b01e2711ff45a1f313d5372d6c8fa4fe55d4d2
for blorp.

v2 (Ken): No need to call _mesa_format_has_color_component() now
          that the number of components is gotten from
          _mesa_base_format_component_count().

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa/formats: Take luminance into account in component count

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965/blorp: Do not trigger re-emission of base state address

In case blorp needs to configure it will be just as if render or
compute pipeline had configured it.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp: Reconfigure base state address only if needed

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp: Use BRW_NEW_BLORP instead of trashing all state bits

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Make all atoms to track BRW_NEW_BLORP by default

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com

i965: Introduce state flag for blorp

In the past, BLORP has clobbered all BRW_NEW_* state flags, to trigger
re-emission of the entire 3D pipeline on the next draw.  However, there
are some packets BLORP simply leaves alone, so there's no need to
re-emit them.  Trying to reduce the set of dirty bits flagged after
BLORP runs is tricky.

Instead, we introduce a BRW_NEW_BLORP flag.  This should be set on any
atom which emits a packet that BLORP also emits.  When BLORP runs, it
will flag BRW_NEW_BLORP, causing those packets to get re-emitted.

This also makes it easy to avoid re-emitting specific atoms - we can
simply drop the BRW_NEW_BLORP flag on those.

To start, we assume that all packets need to be re-emitted.  This is the
safest approach and closest to the existing code's behavior.  Many of
these are obviously not required, and can be dropped in subsequent
patches.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp/gen6: Use normal base state address setup

This is identical to the blorp version which only differs in case
fragment shader isn't used. In that case blorp would reset batch
buffer address to zero.
This is not really needed, and having blorp to use base state
address setup that is compatible with normal upload allows one to
skip resetting it.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Remove pointers to non-existing atoms

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: Implement ddx/ddy on VI using ds_bpermute

The ds_bpermute instruction allows threads to transfer data directly
to or from the vgprs of other threads.  These instructions use the LDS
hardware to transfer data, but do not read or write LDS memory.

DDX BEFORE:                        |  DDX AFTER:
                                   |
v_mbcnt_lo_u32_b32_e64 v2, -1, 0   |  v_mbcnt_lo_u32_b32_e64 v2, -1, 0
v_mbcnt_hi_u32_b32_e64 v2, -1, v2  |  v_mbcnt_hi_u32_b32_e64 v2, -1, v2
v_lshlrev_b32_e32 v4, 2, v2        |  v_and_b32_e32 v2, 60, v2
v_and_b32_e32 v2, 60, v2           |  v_lshlrev_b32_e32 v2, 2, v2
v_lshlrev_b32_e32 v3, 2, v2        |  ds_bpermute_b32 v3, v2, v0
s_mov_b32 m0, -1                   |  ds_bpermute_b32 v0, v2, v0 offset:4
ds_write_b32 v4, v0                |  s_waitcnt lgkmcnt(0)
s_waitcnt lgkmcnt(0)               |
v_or_b32_e32 v0, 1, v2             |
v_lshlrev_b32_e32 v0, 2, v0        |
ds_read_b32 v1, v3                 |
ds_read_b32 v0, v0                 |
s_waitcnt lgkmcnt(0)               |
                                   |
LDS: 1 blocks                      |  LDS: 0 blocks

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: Use llvm.amdgcn.mbcnt.* intrinsics instead of llvm.SI.tid

We're trying to move to more of the new style intrinsics with include
the correct target name, and map directly to ISA instructions.

v2:
  - Only do this with LLVM 3.8 and newer.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: Set range metadata on calls to llvm.SI.tid

The range metadata tells LLVM the range of expected values for this intrinsic,
so it can do some additional optimizations on the result.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: Create a helper function for computing the thread id

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965: Disable KHR_texture_compression_astc_hdr on Gen9

Although Gen9 samples from most HDR ASTC surfaces of correctly,
there currently are no software workarounds to fix the incorrect
sampling that occurs in others of certain color endpoint modes.

With this change, we are no longer failing the 14 tests from:
   dEQP-GLES3.functional.texture.compressed.astc.endpoint_value_hdr_cem_15.*

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

swr: [rasterizer memory] Constify load tiles

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] CompleteDrawContext changes for gcc

Add explicit inline and non-inline versions of CompleteDrawContext
to make gcc happy.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer] Small cleanups

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer scripts] Knob scripts tweaks

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer] Interpolation utility functions

v2: use _mm_cmpunord_ps for vIsNaN

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] TemplateArgUnroller

Switch boolean template arguments to typename template arguments of type
std::integral_constant<bool, VALUE>.

This allows the template argument unroller to easily be extended to enums.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] Arena: make most allocated blocks the same size

Reduces sorting cost

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] Fix global arena allocator bug

- Plus some minor code refactoring

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] Fix thread binding for 32-bit windows

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer fetch] Add support for fetching non-uniform component formats

For example, R10G10B10A2_UNORM.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] Use CS spill/fill size in core

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: fix memory leaks from vs/fs compilation

v2: varient -> variant

Reviewed by: George Kyriazis <George.Kyriazis@intel.com>

swr: fix clang warnings

v2: use alternate logic version in swr_check_render_cond

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

freedreno/a4xx: fix encoding of blend color state

Fixes a whole bunch of dEQP-GLES3.functional.fragment_ops.random.* (now
they all pass)

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: update generated headers

Pull in RB_BLEND_* fixes.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

vc4: Make sure we recompile when sample_mask changes.

Part of fixing piglit EXT_framebuffer_multisample/sample-coverage inverted
(there is also a bug with RCL tiled blits)

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>

vc4: Fix validation of full res tile offset if used for non-MSAA.

There's no reason we couldn't do non-MSAA full resolution tile buffer
load/stores, but we would have claimed buffer overflow was being
attempted.  Nothing does this currently.

vc4: Only do MSAA FB operations if the FB is MSAA.

I noticed this as a problem with ET:QW traces emitting coverage code when
the framebuffer was supposed to be single sampled.

vc4: Fix tests for format supported with nr_samples == 1.

This was a bug from the MSAA enabling.  Tests for surfaces with
nr_samples==1 instead of 0 (generally GL renderbuffers) would incorrectly
fail out.

Fixes the ARB_framebuffer_sRGB piglit tests other than srgb_conformance.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>

vc4: Don't try to blit from MSAA surfaces with mismatched width to dst.

I had made the previous blit fix non-MSAA only because I was thinking
about how the hardware infers stride from the RENDERING_CONFIG packet.
However, I'm also inferring the stride for both MSAA src and dst in
vc4_render_cl.c from the width argument in the ioctl.

Fixes 15 EXT_framebuffer_multisample piglit tests.

i965: Disable channel expressions for scalar GS, TCS, TES.

On Broadwell, I get the following shader-db statistics:

Tessellation Control Shaders:

   total instructions in shared programs: 57327 -> 57012 (-0.55%)
   instructions in affected programs: 27334 -> 27019 (-1.15%)
   helped: 45
   HURT: 0

   total cycles in shared programs: 265692 -> 255188 (-3.95%)
   cycles in affected programs: 263122 -> 252618 (-3.99%)
   helped: 184
   HURT: 26

Tessellation Evaluation Shaders:

   total instructions in shared programs: 23236 -> 23157 (-0.34%)
   instructions in affected programs: 2791 -> 2712 (-2.83%)
   helped: 27
   HURT: 0

   total cycles in shared programs: 151858 -> 149704 (-1.42%)
   cycles in affected programs: 151858 -> 149704 (-1.42%)
   helped: 101
   HURT: 114

Geometry Shaders:

   Orbital Explorer goes from 6442 -> 6356 instructions.
   Two Shadow of Mordor shaders increase by a single instruction.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/blorp: Add support for 2x msaa

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp: Add support for encoding/decoding interleaved 2x msaa

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: don't lower mod() in glsl ir

NIR will lower it in nir_opt_algebraic.

No change in shader-db.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: fix cross validation for explicit locations on structs and arrays

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: implement TGSI_SEMANTIC_HELPER_INVOCATION

Depends on LLVM support introduced in r267102.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>