mesa.git
6 years agoradeonsi: don't use emit_data->args in load_emit
Marek Olšák [Sat, 4 Aug 2018 06:36:17 +0000 (02:36 -0400)]
radeonsi: don't use emit_data->args in load_emit

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: don't use emit_data->args in store_emit
Marek Olšák [Sat, 4 Aug 2018 06:06:54 +0000 (02:06 -0400)]
radeonsi: don't use emit_data->args in store_emit

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: don't use emit_data->args in atomic_emit
Marek Olšák [Sat, 4 Aug 2018 04:15:18 +0000 (00:15 -0400)]
radeonsi: don't use emit_data->args in atomic_emit

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: don't use emit_data->args in build_interp_intrinsic
Marek Olšák [Sat, 4 Aug 2018 03:24:06 +0000 (23:24 -0400)]
radeonsi: don't use emit_data->args in build_interp_intrinsic

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: inline atomic_fetch_args
Marek Olšák [Sat, 4 Aug 2018 03:19:48 +0000 (23:19 -0400)]
radeonsi: inline atomic_fetch_args

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: inline store_fetch_args
Marek Olšák [Sat, 4 Aug 2018 03:12:13 +0000 (23:12 -0400)]
radeonsi: inline store_fetch_args

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: inline load_fetch_args
Marek Olšák [Sat, 4 Aug 2018 02:36:58 +0000 (22:36 -0400)]
radeonsi: inline load_fetch_args

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: merge txq_emit and resq_emit
Marek Olšák [Sat, 4 Aug 2018 01:25:43 +0000 (21:25 -0400)]
radeonsi: merge txq_emit and resq_emit

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: inline resq_fetch_args
Marek Olšák [Sat, 4 Aug 2018 01:11:06 +0000 (21:11 -0400)]
radeonsi: inline resq_fetch_args

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: inline txq_fetch_args
Marek Olšák [Sat, 4 Aug 2018 00:54:26 +0000 (20:54 -0400)]
radeonsi: inline txq_fetch_args

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: use get_resinfo directly in lower_gather4_integer
Marek Olšák [Sat, 4 Aug 2018 02:25:06 +0000 (22:25 -0400)]
radeonsi: use get_resinfo directly in lower_gather4_integer

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: inline tex_fetch_args into build_tex_intrinsic
Marek Olšák [Sat, 4 Aug 2018 00:39:50 +0000 (20:39 -0400)]
radeonsi: inline tex_fetch_args into build_tex_intrinsic

The diff looks like it moves code that I didn't touch.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: remove fetch_args callbacks for ALU instructions
Marek Olšák [Sat, 4 Aug 2018 00:22:34 +0000 (20:22 -0400)]
radeonsi: remove fetch_args callbacks for ALU instructions

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: move internal TGSI shaders into si_shaderlib_tgsi.c
Marek Olšák [Thu, 2 Aug 2018 21:40:05 +0000 (17:40 -0400)]
radeonsi: move internal TGSI shaders into si_shaderlib_tgsi.c

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi: implement EXT_window_rectangles
Marek Olšák [Mon, 6 Aug 2018 08:20:30 +0000 (04:20 -0400)]
radeonsi: implement EXT_window_rectangles

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agogallium/u_blitter: save/restore window rectangles
Marek Olšák [Mon, 6 Aug 2018 08:16:47 +0000 (04:16 -0400)]
gallium/u_blitter: save/restore window rectangles

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agonoop: implement set_window_rectangles
Marek Olšák [Mon, 6 Aug 2018 08:16:18 +0000 (04:16 -0400)]
noop: implement set_window_rectangles

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoddebug: implement set_window_rectangles
Marek Olšák [Mon, 6 Aug 2018 08:15:47 +0000 (04:15 -0400)]
ddebug: implement set_window_rectangles

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoi965: Add a new CFL PCI ID.
Rodrigo Vivi [Thu, 9 Aug 2018 05:43:00 +0000 (22:43 -0700)]
i965: Add a new CFL PCI ID.

One more CFL ID added to spec.

Align with kernel commit d0e062ebb3a4 ("drm/i915/cfl:
Add a new CFL PCI ID.")

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agofreedreno/ir3: add support for a6xx 'merged' register set
Rob Clark [Sat, 11 Aug 2018 14:30:38 +0000 (10:30 -0400)]
freedreno/ir3: add support for a6xx 'merged' register set

Starting with a6xx, half and full precision registers conflict.  Which
makes things a bit more efficient, ie. if some parts of the shader are
heavy on half-precision and others on full precision, you don't have to
allocate the worst case for both.  But it means we need to setup some
additional conflicts.

Signed-off-by: Rob Clark <robdclark@gmail.com>
6 years agofreedreno/ir3: small RA cleanup
Rob Clark [Fri, 10 Aug 2018 18:16:54 +0000 (14:16 -0400)]
freedreno/ir3: small RA cleanup

Collapse is_temp() into it's only callsite, and pass compiler object as
struct rather than void.  Just cleanups to reduce noise in next patch.

Signed-off-by: Rob Clark <robdclark@gmail.com>
6 years agofreedreno/ir3: stop hard-coding FS input regs
Rob Clark [Fri, 10 Aug 2018 15:57:26 +0000 (11:57 -0400)]
freedreno/ir3: stop hard-coding FS input regs

We originally did this because at the time we didn't know all the
bitfields to configure where various frag shader sysval's went.  But
we do.

So switch to using sysvals for all the frag shader inputs.

Signed-off-by: Rob Clark <robdclark@gmail.com>
6 years agofreedreno/ir3: use r63.x for unused inputs
Rob Clark [Fri, 10 Aug 2018 16:23:47 +0000 (12:23 -0400)]
freedreno/ir3: use r63.x for unused inputs

This way, unused sysval inputs, like frag_vcoord, get the correct regid
value to disable the input.

Signed-off-by: Rob Clark <robdclark@gmail.com>
6 years agofreedreno/ir3: create all inputs in first block
Rob Clark [Fri, 10 Aug 2018 14:39:08 +0000 (10:39 -0400)]
freedreno/ir3: create all inputs in first block

create_input()/create_input_compmask() should take the ctx as arg,
rather than block, to enforce that all inputs are created in the first
block, so that RA sees them as live at the start of the shader.

Signed-off-by: Rob Clark <robdclark@gmail.com>
6 years agofreedreno/ir3: rename s/frag_pos/frag_vcoord/g
Rob Clark [Fri, 10 Aug 2018 13:50:14 +0000 (09:50 -0400)]
freedreno/ir3: rename s/frag_pos/frag_vcoord/g

Make it more clear that this is varying fetch related.  Also fixup some
comments.  Just cleanup for next patches.

Signed-off-by: Rob Clark <robdclark@gmail.com>
6 years agocompiler: add SYSTEM_VALUE_VARYING_COORD
Rob Clark [Fri, 10 Aug 2018 13:13:47 +0000 (09:13 -0400)]
compiler: add SYSTEM_VALUE_VARYING_COORD

Used internally in freedreno/ir3 for the vec2 value that hw passes to
shader to use as coordinate for bary.f (varying fetch) instruction.
This is not the same as SYSTEM_VALUE_FRAG_COORD.

Signed-off-by: Rob Clark <robdclark@gmail.com>
6 years agofreedreno/ir3: move per-generation compiler config
Rob Clark [Fri, 10 Aug 2018 12:48:25 +0000 (08:48 -0400)]
freedreno/ir3: move per-generation compiler config

Move it from the compile ctx to the compiler object, before adding
new things for a6xx.

Signed-off-by: Rob Clark <robdclark@gmail.com>
6 years agoradv: Update to new VK_EXT_vertex_attribute_divisor to version 2.
Bas Nieuwenhuizen [Mon, 23 Jul 2018 14:24:02 +0000 (16:24 +0200)]
radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.

Behavior wrt firstInstance got changed, and a divisor of 0 has been
disallowed.

The new version of the ext got published in specification 1.1.81.

Sending to stable since the only known user is DXVK, which needs
this for correctness.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
CC: 18.2 <mesa-stable@lists.freedesktop.org>
6 years agoradv: Allow ETC2 on RAVEN and VEGA10 instead of all GFX9.
Bas Nieuwenhuizen [Sat, 28 Jul 2018 12:01:42 +0000 (14:01 +0200)]
radv: Allow ETC2 on RAVEN and VEGA10 instead of all GFX9.

Follow radeonsi.

Fixes: 3665f66ef26 "radv: Add support for ETC2 textures."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradv: Fix missing Android platform define.
Bas Nieuwenhuizen [Fri, 10 Aug 2018 00:26:19 +0000 (02:26 +0200)]
radv: Fix missing Android platform define.

CC: <mesa-stable@lists.freedesktop.org>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agofreedreno: move free() into fdN_context_destroy()
Rob Clark [Mon, 30 Jul 2018 12:38:28 +0000 (08:38 -0400)]
freedreno: move free() into fdN_context_destroy()

Following patches will be doing further cleanup after calling
fd_context_destroy() so it is easier if we move the free() into
the per-gen backend code.

Signed-off-by: Rob Clark <robdclark@gmail.com>
6 years agofreedreno: a2xx: ir2 update
Jonathan Marek [Tue, 24 Jul 2018 12:58:24 +0000 (08:58 -0400)]
freedreno: a2xx: ir2 update

this patch brings a number of changes to ir2:
-ir2 now generates CF clauses as necessary during assembly. this simplifies
 fd2_program/fd2_compiler and is necessary to implement optimization passes
-ir2 now has separate vector/scalar instructions. this will make it easier
 to implementing scheduling of scalar+vector instructions together. dst_reg
 is also now seperate from src registers instead of a single list
-ir2 now implements register allocation. this makes it possible to compile
 shaders which have more than 64 TGSI registers
-ir2 now implements the following optimizations: removal of IN/OUT MOV
 instructions generated by TGSI and removal of unused instructions when
 some exports are disabled
-ir2 now allows full 8-bit index for constants
-ir2_alloc no longer allocates 4 times too many bytes

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@gmail.com>
6 years agodocs: update calendar 18.2.0-rc1 and 18.2.0-rc2 are out
Andres Gomez [Tue, 14 Aug 2018 14:06:42 +0000 (17:06 +0300)]
docs: update calendar 18.2.0-rc1 and 18.2.0-rc2 are out

Signed-off-by: Andres Gomez <agomez@igalia.com>
6 years agoradv: Add on-demand compilation of built-in shaders.
Bas Nieuwenhuizen [Mon, 13 Aug 2018 22:07:57 +0000 (00:07 +0200)]
radv: Add on-demand compilation of built-in shaders.

In environments where we cannot cache, e.g. Android (no homedir),
ChromeOS (readonly rootfs) or sandboxes (cannot open cache), the
startup cost of creating a device in radv is rather high, due
to compiling all possible built-in pipelines up front. This meant
depending on the CPU a 1-4 sec cost of creating a Device.

For CTS this cost is unacceptable, and likely for starting random
apps too.

So if there is no cache, with this patch radv will compile shaders
on demand. Once there is a cache from the first run, even if
incomplete, the driver knows that it can likely write the cache
and precompiles everything.

Note that I did not switch the buffer and itob/btoi compute pipelines
to on-demand, since you cannot really do anything in Vulkan without
them and there are only a few.

This reduces the CTS runtime for the no caches scenario on my
threadripper from 32 minutes to 8 minutes.

Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agoradv: Refactor blit pipeline creation.
Bas Nieuwenhuizen [Sun, 12 Aug 2018 23:29:09 +0000 (01:29 +0200)]
radv: Refactor blit pipeline creation.

Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agoradv: Make fs key exemplars ordered to be a reverse fs_key lookup.
Bas Nieuwenhuizen [Sat, 11 Aug 2018 21:26:26 +0000 (23:26 +0200)]
radv: Make fs key exemplars ordered to be a reverse fs_key lookup.

While at it, share the exemplars and account for a non-occurring
fs key.

Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agovirgl: ARB_texture_barrier support
Dave Airlie [Fri, 3 Aug 2018 05:19:41 +0000 (15:19 +1000)]
virgl: ARB_texture_barrier support

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
6 years agodocs: update calendar, add news item and link release notes for 18.1.6
Dylan Baker [Mon, 13 Aug 2018 17:06:45 +0000 (10:06 -0700)]
docs: update calendar, add news item and link release notes for 18.1.6

Signed-off-by: Dylan Baker <dylan@pnwbakers.com>
6 years agodocs: Add sha256 sums for 18.1.6
Dylan Baker [Mon, 13 Aug 2018 16:56:25 +0000 (09:56 -0700)]
docs: Add sha256 sums for 18.1.6

6 years agodocs: Add release notes for 18.1.6
Dylan Baker [Mon, 13 Aug 2018 15:36:16 +0000 (08:36 -0700)]
docs: Add release notes for 18.1.6

6 years agomesa/glspirv: fix compilation with MSVC
Alejandro Piñeiro [Mon, 13 Aug 2018 14:47:11 +0000 (16:47 +0200)]
mesa/glspirv: fix compilation with MSVC

From AppVeyor #8582, it seems that MSVC doesn't like uint, so this
patch replaces it with unsigned.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
6 years agotravis: install correct version of mako for each build system
Eric Engestrom [Mon, 13 Aug 2018 11:10:38 +0000 (12:10 +0100)]
travis: install correct version of mako for each build system

Meson now uses python3, so let's add a block for Autotools, move that
line into the buildsys-specific blocks, and set the correct version for
Meson.

Fixes: 2ee1c86d71bee5ddca2c "meson: Build with Python 3"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
6 years agomesa/st/glsl_to_tgsi: fixup copy-paste mistake
Erik Faye-Lund [Sun, 12 Aug 2018 13:24:38 +0000 (15:24 +0200)]
mesa/st/glsl_to_tgsi: fixup copy-paste mistake

This is clearly a copy-paste error; if we validate the reladdr2-pointer,
we don't want to traverse to the reladdr-pointer. Especially since the
check above shows that reladdr could be NULL here.

Noticed by Coverity.

CID: 14383891438390
Fixes: 568bda2f2d3 ("mesa/st/glsl_to_tgsi: Split arrays whose elements are only accessed directly")
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gert Wollny <gw.fossdev@gmail.com>
6 years agoi965/nir: Use the nir copy of shader_info to handle gl_PatchVerticesIn
Neil Roberts [Tue, 31 Jul 2018 13:44:24 +0000 (15:44 +0200)]
i965/nir: Use the nir copy of shader_info to handle gl_PatchVerticesIn

Instead of using the copy of shader_info stored in gl_program, it now
uses the one in nir_shader. This is needed for SPIR-V because the
info.tess.tcs_vertices_out is filled in via _mesa_spirv_to_nir which
happens much later than with a GLSL shader. The copy of shader_data in
gl_program is only updated later via brw_shader_gather_info but that
is too late.

For GLSL this shouldn't create any problems because the nir copy of
the shader_info is immediately copied from the gl_program in
glsl_to_nir.

v2: updated after commit "i965: Combine both gl_PatchVerticesIn
    lowering passes." (488972) (Alejandro Piñeiro)

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agomesa/glspirv: Set separate_shader on shader_info
Neil Roberts [Mon, 26 Mar 2018 15:12:41 +0000 (17:12 +0200)]
mesa/glspirv: Set separate_shader on shader_info

The value is copied from the gl_program. If we don’t do this then it
will get reset back to zero in brw_shader_gather_info. This isn’t a
problem for GLSL because in that case the nir_shader is initialised
with a copy of the shader_info from the gl_program.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agomesa/glspirv: pick off the only entry point we need
Iago Toral Quiroga [Tue, 31 Jul 2018 13:37:59 +0000 (15:37 +0200)]
mesa/glspirv: pick off the only entry point we need

This is the same we do for vulkan drivers

This is needed to pass the following CTS test:
KHR-GL45.gl_spirv.spirv_modules_shader_binary_multiple_shader_objects_test

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agomesa/glspirv: compute double inputs and remap attributes
Alejandro Piñeiro [Wed, 21 Mar 2018 08:05:51 +0000 (09:05 +0100)]
mesa/glspirv: compute double inputs and remap attributes

input locations used by input attributes are not handled in the same
way in OpenGL vs Vulkan. There is a detailed explanation of such
differences on the following commit:

c2acf97fcc9b32eaa9778771282758e5652a8ad4

So with this commit, the same adjustment that is done after
glsl_to_nir, is being done after spirv_to_nir, when it is used on
OpenGL (ARB_gl_spirv).

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agonir/glsl: make nir_remap_attributes public
Alejandro Piñeiro [Wed, 21 Mar 2018 08:39:32 +0000 (09:39 +0100)]
nir/glsl: make nir_remap_attributes public

As we plan to reuse it for ARB_gl_spirv implementation.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agonir/lower_samplers: don't assume a deref for both texture and sampler srcs
Alejandro Piñeiro [Fri, 13 Jul 2018 10:39:41 +0000 (12:39 +0200)]
nir/lower_samplers: don't assume a deref for both texture and sampler srcs

After commit "nir: Use derefs in nir_lower_samplers"
(75286c2d083cdbdfb202a93349e567df0441d5f7) assumes one deref for both
the texture and the sampler. However there are cases (on OpenGL, using
ARB_gl_spirv) where SPIR-V is not providing a sampler, like for
texture query levels ops. Although we could make spirv_to_nir to
provide a sampler deref for those cases, it is not really needed, and
wrong from the Vulkan point of view.

This patch fixes the following (borrowed) tests run on SPIR-V mode:
  arb_compute_shader/execution/basic-texelFetch.shader_test
  arb_gpu_shader5/execution/sampler_array_indexing/fs-simple-texture-size.shader_test
  arb_texture_query_levels/execution/fs-baselevel.shader_test
  arb_texture_query_levels/execution/fs-maxlevel.shader_test
  arb_texture_query_levels/execution/fs-miptree.shader_test
  arb_texture_query_levels/execution/fs-nomips.shader_test
  arb_texture_query_levels/execution/vs-baselevel.shader_test
  arb_texture_query_levels/execution/vs-maxlevel.shader_test
  arb_texture_query_levels/execution/vs-miptree.shader_test
  arb_texture_query_levels/execution/vs-nomips.shader_test
  glsl-1.30/execution/fs-textureSize-compare.shader_test

v2: merge lower_tex_src_to_offset and calc_sampler_offsets together,
    update texture/sampler index and texture_array_size directly on
    lower_tex_src_to_offset (Jason)
v3: clarify one comment (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agonir/linker: take into account hidden uniforms
Alejandro Piñeiro [Wed, 8 Aug 2018 11:41:58 +0000 (13:41 +0200)]
nir/linker: take into account hidden uniforms

So they are not exposed through the introspection API.

It is worth to note that the number of hidden uniforms of GLSL linking
vs SPIR-V linking would be somewhat different due the differen order
of the nir lowerings/optimizations.

For example: gl_FbWposYTransform. This is introduced as part of
nir_lower_wpos_ytransform. On GLSL that is executed after the IR-based
linking. So that means that on GLSL the UniformStorage will not
include this uniform. With the SPIR-V linking, that uniform is already
present, but marked as hidden. So it will be included on the
UniformStorage, but as hidden.

One alternative would create a special how_declared for that case, but
seemed an overkill. Using hidden should be ok as far as it is used
properly.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agonir: add how_declared to nir_variable.data
Alejandro Piñeiro [Tue, 8 May 2018 06:58:59 +0000 (08:58 +0200)]
nir: add how_declared to nir_variable.data

Equivalent to the already existing how_declared at GLSL IR. The only
difference is that we are not adding all the declaration_type
available on GLSL, only the one that we will use on the short term. We
would add more mode if needed on the future.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agospirv: Make VertexIndex and VertexId both non-zero-based
Neil Roberts [Thu, 19 Apr 2018 15:17:41 +0000 (17:17 +0200)]
spirv: Make VertexIndex and VertexId both non-zero-based

GLSL has gl_VertexID which is supposed to be non-zero-based.

SPIR-V has both VertexIndex and VertexId builtins whose meanings are
defined by the APIs.

Vulkan defines VertexIndex as being non-zero-based. In Vulkan VertexId
and InstanceId have no meaning and are pretty much just reserved for
OpenGL at this point.

GL_ARB_spirv removes VertexIndex and defines VertexId to be the same
as gl_VertexId (which is also non-zero-based).

Previously in Mesa it was treating VertexIndex as non-zero-based and
VertexId as zero-based, so it was breaking for GL. This behaviour was
apparently based on Khronos bug 14255. However that bug doesn’t seem
to have made a final decision for VertexId.

Assuming there really is no other definition for VertexId for Vulkan
it seems better to just make them both have the same value.

v2: update comment and commit descriptions, based on Jason Ekstrand
    explanation of the meaning/rationale behind all those builtins
    (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agospirv: fill info.gs.input_primitive too
Alejandro Piñeiro [Mon, 23 Oct 2017 15:19:34 +0000 (17:19 +0200)]
spirv: fill info.gs.input_primitive too

info.gs.output_primitive was already being filled. Not sure why this
is not needed on Vulkan, but we found to be needed for
ARB_gl_spirv. Specifically, this is needed to get the following test
passing:

KHR-GL45.gl_spirv.spirv_validation_builtin_variable_decorations_test

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agodocs/features: mark GL_EXT_render_snorm as done for i965
Tapani Pälli [Mon, 13 Aug 2018 10:08:22 +0000 (13:08 +0300)]
docs/features: mark GL_EXT_render_snorm as done for i965

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
6 years agoi965: enable EXT_render_snorm
Tapani Pälli [Thu, 14 Jun 2018 10:06:33 +0000 (13:06 +0300)]
i965: enable EXT_render_snorm

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
6 years agomesa: enable EXT_render_snorm extension
Tapani Pälli [Thu, 24 May 2018 11:05:27 +0000 (14:05 +0300)]
mesa: enable EXT_render_snorm extension

Patch sets additional formats renderable and enables the extension
when OpenGL ES 3.1 is supported.

v2: instead of dummy_true, have a separate toggle for extension
    (Eric Anholt)

v3: add missing checks, simplify some existing checks and fix
    glCopyTexImage2D check (Nanley Chery)

    add SHORT and BYTE support in read_pixels_es3_error_check

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
6 years agoblorp: Properly handle Z24X8 blits.
Kenneth Graunke [Fri, 10 Aug 2018 06:28:24 +0000 (23:28 -0700)]
blorp: Properly handle Z24X8 blits.

One of the reasons we didn't notice that R24_UNORM_X8_TYPELESS
destinations were broken was that an earlier layer was swapping it
out for B8G8R8A8_UNORM.  That made Z24X8 -> Z24X8 blits work.

However, R32_FLOAT -> R24_UNORM_X8_TYPELESS was still totally broken.
The old code only considered one format at a time, without thinking
that format conversion may need to occur.

This patch moves the translation out to a place where it can consider
both formats.  If both are Z24X8, we continue using B8G8R8A8_UNORM to
avoid having to do shader math workarounds.  If we have a Z24X8
destination, but a non-matching source, we use our shader hacks to
actually render to it properly.

Fixes: 804856fa5735164cc0733ad0ea62adad39b00ae2 (intel/blorp: Handle more exotic destination formats)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoblorp: Don't try to use R32_UNORM for R24_UNORM_X8_TYPELESS rendering.
Kenneth Graunke [Fri, 10 Aug 2018 06:11:07 +0000 (23:11 -0700)]
blorp: Don't try to use R32_UNORM for R24_UNORM_X8_TYPELESS rendering.

The hardware doesn't support rendering to R24_UNORM_X8_TYPELESS, so
Jason decided to fake it with a bit of shader math and R32_UNORM RTs.

The only problem is that R32_UNORM isn't renderable either...so we've
just traded one bad format for another.

This patch makes us use R32_UINT instead.

Fixes: 804856fa5735164cc0733ad0ea62adad39b00ae2 (intel/blorp: Handle more exotic destination formats)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel: Switch the order of the 2x MSAA sample positions
Jason Ekstrand [Mon, 23 Jul 2018 15:02:46 +0000 (08:02 -0700)]
intel: Switch the order of the 2x MSAA sample positions

The Vulkan 1.1.82 spec flipped the order to better match D3D.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
6 years agomesa/st/tests: Add array life range estimation and renumbering tests
Gert Wollny [Tue, 5 Jun 2018 20:26:49 +0000 (22:26 +0200)]
mesa/st/tests: Add array life range estimation and renumbering tests

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/tests: Add array life range tests infrastructure to common test class
Gert Wollny [Tue, 5 Jun 2018 20:26:48 +0000 (22:26 +0200)]
mesa/st/tests: Add array life range tests infrastructure to common test class

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/glsl_to_tgsi: Expose array live range tracking and merging
Gert Wollny [Tue, 5 Jun 2018 20:26:47 +0000 (22:26 +0200)]
mesa/st/glsl_to_tgsi: Expose array live range tracking and merging

This patch ties in the array split, merge, and interleave code.

shader-db changes in the TGSI code are:

              original code  |  array-merge  |       change
              mean      max  |  mean    max  | best  mean %  worst
      -----------------------------------------------------------
      arrays   0.05       2  |   0.00     0  |  -2   -100      0
total temps    5.05      21  |   4.92    20  | -15   -2.59     1
      instr   55.33     988  |  55.20   988  | -15   -0.24     0

Evaluation:

Run shader-db in single thread mode (otherwise the output is
not ordered and the best and worst column don't make sense) to
get results pre-stats.txt and post-stats.txt. Then using
python pandas:

 import pandas as pd
 old_stats = pd.read_csv('pre-stats.txt')
 new_stats = pd.read_csv('post-stats.txt')
 omean = old_stats.mean()
 omax = old_stats.max()
 nmean = new_stats.mean()
 nmax = new_stats.max()
 delta =  new_stats - old_stats
 pd.concat([omean, omax, nmean, nmax, delta.min(),
            delta.mean()/old_stats.mean()*100, delta.max()],
            axis=1, keys=['mean', 'max', 'mean', 'max', 'best',
            'avg change %', 'worst'])

v4: - Correct typo and add bugs that are fixed by this series.
    - Update stats and describe stats evaluation

Bugzilla:
  https://bugs.freedesktop.org/show_bug.cgi?id=105371
  https://bugs.freedesktop.org/show_bug.cgi?id=100200
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/glsl_to_tgsi: add array life range evaluation into tracking code
Gert Wollny [Tue, 5 Jun 2018 20:26:46 +0000 (22:26 +0200)]
mesa/st/glsl_to_tgsi: add array life range evaluation into tracking code

v4: Also track the register given in inst->resource. (thanks: Benedikt Schemmer
    for testing the patches on radeonsi, which revealed that I was missing
    tracking this)
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/glsl_to_tgsi: add class for array access tracking
Gert Wollny [Tue, 5 Jun 2018 20:26:45 +0000 (22:26 +0200)]
mesa/st/glsl_to_tgsi: add class for array access tracking

Because of the indirect access it is impossible to obtain an accurate per
component and array element tracking. Therefore, the tracking is simplified
to only track whether any element was accessed, whether this happend
conditionally in a loop. In addition, while tracking of temporaries requires
a per-componet tracking that is later fused, for arrays only the components
access mask is neede. The resulting tracking code and evaluation of the array
live range is sufficiently different from the evaluation of the live range of
temporaries to justify implementing this in a different class instead of
adding more complexity to the already existing code for temporary life
range evaluation.

v4: Update commit message to make it clearer why this class is seperate from
    the tracking of temporaries.
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/glsl_to_tgsi: move evaluation of read mask up in the call hierarchy
Gert Wollny [Tue, 5 Jun 2018 20:26:44 +0000 (22:26 +0200)]
mesa/st/glsl_to_tgsi: move evaluation of read mask up in the call hierarchy

In preparation of the array live range tracking the evaluation of the read
mask is moved out the register live range tracking to the enclosing call
of the generalized read access tracking.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/glsl_to_tgsi: rename access_record to register_merge_record and some more...
Gert Wollny [Tue, 5 Jun 2018 20:26:43 +0000 (22:26 +0200)]
mesa/st/glsl_to_tgsi: rename access_record to register_merge_record and some more renames

In preparartion of adding the tracking of the live range the classes that refer
to temporary registers are renamed.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/tests: Add tests for array merge helper classes.
Gert Wollny [Tue, 5 Jun 2018 20:26:42 +0000 (22:26 +0200)]
mesa/st/tests: Add tests for array merge helper classes.

v2: - Define tests also in the meson.build file.
v4: - Check no-op mapping of all bits.
    - Convert tests to the new class layout used in the merge evaulation.
    - remove dependency on llvm in meson build (Thanks Dylan Baker for pointing
       out that this might not needed)
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/glsl_to_tgsi: Add array merge logic
Gert Wollny [Tue, 5 Jun 2018 20:26:41 +0000 (22:26 +0200)]
mesa/st/glsl_to_tgsi: Add array merge logic

v4: - Update the code to use the new merge logic.
    - Use a cleaner, class-based approach for the evaluation of merges.
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/glsl_to_tgsi: Add helper classes to apply array merging and interleaving
Gert Wollny [Tue, 5 Jun 2018 20:26:40 +0000 (22:26 +0200)]
mesa/st/glsl_to_tgsi: Add helper classes to apply array merging and interleaving

v4: - Remove logic for evaluation of swizzles and merges since this
        was moved to array_live_range. This class now only handles the
        actual remapping.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/glsl_to_tgsi: Add helper class for array live range merging and interleaving
Gert Wollny [Tue, 5 Jun 2018 20:26:39 +0000 (22:26 +0200)]
mesa/st/glsl_to_tgsi: Add helper class for array live range merging and interleaving

This class holds the array length, live range, and accessed components, and
it implements the logic for evaluating how arrays are merged and interleaved.

v4: - Add logic to evaluate merge and interleave of a pair of arrays to
      the class array_live_range.
    - document class
    - update commit message

Thanks Nicolai Hähnle for the pointers given.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/glsl_to_tgsi:rename lifetime to register_live_range
Gert Wollny [Tue, 5 Jun 2018 20:26:38 +0000 (22:26 +0200)]
mesa/st/glsl_to_tgsi:rename lifetime to register_live_range

On one hand "live range" is the term used in the literature, and on the
other hand a distinction is needed from the array live ranges.

v4: Fix indentions and white spaces

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v3)
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/glsl_to_tgsi: Properly resolve life times simple if/else + use constructs
Gert Wollny [Tue, 5 Jun 2018 20:26:37 +0000 (22:26 +0200)]
mesa/st/glsl_to_tgsi: Properly resolve life times simple if/else + use constructs

in constructs like below, currently the live range estimation extends the live range
of t unecessarily to the whole loop because it was not detected that t is
unconditional written and later read only in the "if (a)" scope.

  while (foo)  {
    ...
    if (a) {
       ...
       if (b)
         t = ...
       else
         t = ...
       x = t;
       ...
    }
     ...
  }

This patch adds a unit test for this case and corrects the minimal live range estimation
accordingly.

v4: update comments
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/glsl_to_tgsi: Split arrays whose elements are only accessed directly
Gert Wollny [Tue, 5 Jun 2018 20:26:36 +0000 (22:26 +0200)]
mesa/st/glsl_to_tgsi: Split arrays whose elements are only accessed directly

Array whose elements are only accessed directly are replaced by the
according number of temporary registers. By doing so the otherwise
reserved register range becomes subject to further optimizations like
copy propagation and register merging.

Thanks to the resulting reduced register pressure this patch makes
the piglits

  spec/glsl-1.50/execution -
      variable-indexing/vs-output-array-vec3-index-wr-before-gs
      geometry/max-input-components

pass on r600 (barts) where they would fail before with a "GPR limit exceeded"
error (even with the spilling that was recently added).

v2: * rename method dissolve_arrays to split_arrays
    * unify the tracking and remapping methods for src and dst registers
    * also track access to arrays via reladdr*

v3: * enable this optimization only if the driver requests register merge

v4: * Correct comments
    * Also update inst->resource if it is an array element
      (thanks: Benedikt Schemmer for testing the patches on radeonsi, which
       revealed that I was missing tracking this)

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agomesa/st/glsl_to_tgsi: Add method to collect some TGSI statistics
Gert Wollny [Tue, 5 Jun 2018 20:26:35 +0000 (22:26 +0200)]
mesa/st/glsl_to_tgsi: Add method to collect some TGSI statistics

When mesa is compiled in debug mode then this adds the possibility
to print out some statistics about the translated and optimized TGSI
shaders to a file.

The functionality is enabled by setting the environment variable

   GLSL_TO_TGSI_PRINT_STATS

to the file name where the statistics should be collected. The file is
opened in append mode so that statistics from various runs will be
accumulated.

v4: Make accress to log file thread save (thanks for pointing this out Nicolai
    Hähnle)
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
6 years agoGallium/tgsi: Correct signdness of return value of bit operations
Gert Wollny [Fri, 10 Aug 2018 13:04:17 +0000 (15:04 +0200)]
Gallium/tgsi: Correct signdness of return value of bit operations

The GLSL operations findLSB, findMSB, and countBits always return
a signed integer type. Let TGSI reflect this.

v2: Properly set values in infer_(src|dst)_type   (Thanks Roland
    Schneidegger for pointing out problems with my 1st approach)
v2: Set values in the common infer_type code path, and only add
    the correct source type for UMSB (Roland Schneidegger)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
6 years agomeson: Build with Python 3
Mathieu Bridon [Thu, 9 Aug 2018 08:27:26 +0000 (10:27 +0200)]
meson: Build with Python 3

Now that all the build scripts are compatible with both Python 2 and 3,
we can flip the switch and tell Meson to use the latter.

Since Meson already depends on Python 3 anyway, this means we don't need
two different Python stacks to build Mesa.

Signed-off-by: Mathieu Bridon <bochecha@daitauha.fr>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
6 years agopython: Rework bytes/unicode string handling
Mathieu Bridon [Fri, 10 Aug 2018 21:17:08 +0000 (23:17 +0200)]
python: Rework bytes/unicode string handling

In both Python 2 and 3, opening a file without specifying the mode will
open it for reading in text mode ('r').

On Python 2, the read() method of a file object opened in mode 'r' will
return byte strings, while on Python 3 it will return unicode strings.

Explicitly specifying the binary mode ('rb') then decoding the byte
string means we always handle unicode strings on both Python 2 and 3.

Which in turns means all re.match(line) will return unicode strings as
well.

If we also make expandCString return unicode strings, we don't need the
call to the unicode() constructor any more.

We were using the ugettext() method because it always returns unicode
strings in Python 2, contrarily to the gettext() one which returns
byte strings. The ugettext() method doesn't exist on Python 3, so we
must use the right method on each version of Python.

The last hurdles are that Python 3 doesn't let us concatenate unicode
and byte strings directly, and that Python 2's stdout wants encoded byte
strings while Python 3's want unicode strings.

With these changes, the script gives the same output on both Python 2
and 3.

Signed-off-by: Mathieu Bridon <bochecha@daitauha.fr>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
6 years agopython: Fix inequality comparisons
Mathieu Bridon [Thu, 9 Aug 2018 08:27:18 +0000 (10:27 +0200)]
python: Fix inequality comparisons

On Python 3, executing `foo != bar` will first try to call
foo.__ne__(bar), and fallback on the opposite result of foo.__eq__(bar).

Python 2 does not do that.

As a result, those __eq__ methods were never called, when we were
testing for inequality.

Expliclty adding the __ne__ methods fixes this issue, in a way that is
compatible with both Python 2 and 3.

However, this means the __eq__ methods are now called when testing for
`foo != None`, so they need to be guarded correctly.

Signed-off-by: Mathieu Bridon <bochecha@daitauha.fr>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
6 years agomesa/st: ETC2 now uses R8G8B8A8_SRGB as fallback
Gert Wollny [Thu, 9 Aug 2018 10:46:52 +0000 (12:46 +0200)]
mesa/st: ETC2 now uses R8G8B8A8_SRGB as fallback

The check for ETC2 compatibility was not updated when the fallback
format was changed.

Fixes: 71867a0a61cea20bf3f6115692e70b0d60f0b70d
   st/mesa: Fall back to R8G8B8A8_SRGB for ETC2

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agopython: Simplify list sorting
Mathieu Bridon [Thu, 9 Aug 2018 08:27:24 +0000 (10:27 +0200)]
python: Simplify list sorting

Instead of copying the list, then sorting the copy in-place, we can just
get a new sorted copy directly.

Signed-off-by: Mathieu Bridon <bochecha@daitauha.fr>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
6 years agopython: Use key-functions when sorting containers
Mathieu Bridon [Thu, 9 Aug 2018 08:27:23 +0000 (10:27 +0200)]
python: Use key-functions when sorting containers

In Python 2, the traditional way to sort containers was to use a
comparison function (which returned either -1, 0 or 1 when passed two
objects) and pass that as the "cmp" argument to the container's sort()
method.

Python 2.4 introduced key-functions, which instead only operate on a
given item, and return a sorting key for this item.

In general, this runs faster, because the cmp-function has to get run
multiple times for each item of the container.

Python 3 removed the cmp-function, enforcing usage of key-functions
instead.

This change makes the script compatible with Python 2 and Python 3.

Signed-off-by: Mathieu Bridon <bochecha@daitauha.fr>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
6 years agopython: Better check for integer types
Mathieu Bridon [Thu, 9 Aug 2018 08:27:22 +0000 (10:27 +0200)]
python: Better check for integer types

Python 3 lost the long type: now everything is an int, with the right
size.

This commit makes the script compatible with Python 2 (where we check
for both int and long) and Python 3 (where we only check for int).

Signed-off-by: Mathieu Bridon <bochecha@daitauha.fr>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
6 years agopython: Do not mix bytes and unicode strings
Mathieu Bridon [Thu, 9 Aug 2018 08:27:21 +0000 (10:27 +0200)]
python: Do not mix bytes and unicode strings

Mixing the two is a long-standing recipe for errors in Python 2, so much
so that Python 3 now completely separates them.

This commit stops treating both as if they were the same, and in the
process makes the script compatible with both Python 2 and 3.

Signed-off-by: Mathieu Bridon <bochecha@daitauha.fr>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
6 years agopython: Explicitly use a list
Mathieu Bridon [Thu, 9 Aug 2018 08:27:20 +0000 (10:27 +0200)]
python: Explicitly use a list

On Python 2, the builtin functions filter() returns a list.

On Python 3, it returns an iterator.

Since we want to use those objects in contexts where we need lists, we
need to explicitly turn them into lists.

This makes the code compatible with both Python 2 and Python 3.

Signed-off-by: Mathieu Bridon <bochecha@daitauha.fr>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
6 years agopython: Use the right function for the job
Mathieu Bridon [Thu, 9 Aug 2018 08:27:19 +0000 (10:27 +0200)]
python: Use the right function for the job

The code was just reimplementing itertools.combinations_with_replacement
in a less efficient way.

This does change the order of the results slightly, but it should be ok.

Signed-off-by: Mathieu Bridon <bochecha@daitauha.fr>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
6 years agoegl: Fix leak of X11 pixmaps backing pbuffers in DRI3.
Eric Anholt [Tue, 7 Aug 2018 18:37:28 +0000 (11:37 -0700)]
egl: Fix leak of X11 pixmaps backing pbuffers in DRI3.

This is basically copied from the DRI2 destroy path.  Without this,
Raspberry Pi would quickly run out of CMA during the EGL tests in the CTS
due to all the pixmaps laying around.

Fixes: f35198badeb9 ("egl/x11: Implement dri3 support with loader's dri3 helper")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
6 years agointel: Fix SIMD16 unaligned payload GRF reads on Gen4-5.
Kenneth Graunke [Thu, 2 Aug 2018 22:02:18 +0000 (15:02 -0700)]
intel: Fix SIMD16 unaligned payload GRF reads on Gen4-5.

When the SIMD16 Gen4-5 fragment shader payload contains source depth
(g2-3), destination stencil (g4), and destination depth (g5-6), the
single register of stencil makes the destination depth unaligned.

We were generating this instruction in the RT write payload setup:

   mov(16)   m14<1>F   g5<8,8,1>F   { align1 compr };

which is illegal, instructions with a source region spanning more than
one register need to be aligned to even registers.  This is because the
hardware implicitly does (nr | 1) instead of (nr + 1) when splitting the
compressed instruction into two mov(8)'s.

I believe this would cause the hardware to load g5 twice, replicating
subspan 0-1's destination depth to subspan 2-3.  This showed up as 2x2
artifact blocks in both TIS-100 and Reicast.

Normally, we rely on the register allocator to even-align our virtual
GRFs.  But we don't control the payload, so we need to lower SIMD widths
to make it work.  To fix this, we teach lower_simd_width about the
restriction, and then call it again after lower_load_payload (which is
what generates the offending MOV).

Fixes: 8aee87fe4cce0a883867df3546db0e0a36908086 (i965: Use SIMD16 instead of SIMD8 on Gen4 when possible.)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107212
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=13728
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Diego Viola <diego.viola@gmail.com>
6 years agoi965: Only enable depth IZ signals if there's an actual depthbuffer.
Kenneth Graunke [Thu, 2 Aug 2018 18:31:27 +0000 (11:31 -0700)]
i965: Only enable depth IZ signals if there's an actual depthbuffer.

According to the G45 PRM Volume 2 Page 265 we're supposed to only set
these signals when there is an actual depth buffer.  Note that we
already do this for the stencil buffer by virtue of brw->stencil_enabled
invoking _mesa_is_stencil_enabled(ctx) which checks whether the current
drawbuffer's visual has stencil bits (which is updated based on what
buffers are bound).  We just need to do it for depth as well.

Not observed to fix anything.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoglx: GLX_MESA_multithread_makecurrent is direct-only
Adam Jackson [Tue, 5 Dec 2017 16:10:09 +0000 (11:10 -0500)]
glx: GLX_MESA_multithread_makecurrent is direct-only

This extension is not defined for indirect contexts. Marking it as
"client only", as the old code did here, would make the extension
available in indirect contexts, even though the server would certainly
not have it in its extension list.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
6 years agoanv: set error in all failure paths
Eric Engestrom [Wed, 8 Aug 2018 14:42:49 +0000 (15:42 +0100)]
anv: set error in all failure paths

Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Fixes: 5b196f39bddc689742d3 "anv/pipeline: Compile to NIR in compile_graphics"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agointel/tools: add missing variable initialisation
Eric Engestrom [Wed, 8 Aug 2018 14:26:32 +0000 (15:26 +0100)]
intel/tools: add missing variable initialisation

Fixes: 6a60beba4089315685b8 "intel/tools: Add an error state to aub translator"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agodrirc: Allow extension midshader for Metro Redux
vadym.shovkoplias [Mon, 6 Aug 2018 12:52:13 +0000 (15:52 +0300)]
drirc: Allow extension midshader for Metro Redux

This fixes both Metro 2033 Redux and Metro Last Light Redux

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99730
Signed-off-by: Eero Tamminen <eero.t.tamminen@intel.com>
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
6 years agoglsl: handle error case with ast_post_inc, ast_post_dec
Tapani Pälli [Tue, 7 Aug 2018 05:20:29 +0000 (08:20 +0300)]
glsl: handle error case with ast_post_inc, ast_post_dec

Return ir_rvalue::error_value with ast_post_inc, ast_post_dec if
parser error was emitted previously. This way process_array_size
won't see bogus IR generated like with commit 9c676a64273.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98699
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
6 years agovc4: Implement texture_subdata() to directly upload tiled data.
Eric Anholt [Thu, 9 Aug 2018 00:34:42 +0000 (17:34 -0700)]
vc4: Implement texture_subdata() to directly upload tiled data.

This avoids a memcpy into a temporary in the upload path.

Improves x11perf -putimage100 performance by 12.1586% +/- 1.38155% (n=145)

6 years agovc4: Handle partial loads/stores of tiled textures.
Eric Anholt [Wed, 4 Jan 2017 22:08:10 +0000 (14:08 -0800)]
vc4: Handle partial loads/stores of tiled textures.

Previously, we would load out the tile-aligned area, update the raster
copy, and store it back.  This was a huge cost for XPutImage calls to the
screen under glamor.

Instead, implement a general load/store path that walks over the source
x/y writing into the corresponding pixel of the destination (using clever
math from
https://fgiesen.wordpress.com/2011/01/17/texture-tiling-and-swizzling/).
If things are aligned, we go through the previous utile-at-a-time loop.

Improves x11perf -putimage10 performance by 139.777% +/- 2.83464% (n=5)
Improves x11perf -putimage100 performance by 383.908% +/- 22.6297% (n=11)
Improves x11perf -getimage10 performance by 2.75731% +/- 0.585054% (n=145)

6 years agovc4: Compile the LT image helper per cpp we might load/store.
Eric Anholt [Wed, 8 Aug 2018 00:53:24 +0000 (17:53 -0700)]
vc4: Compile the LT image helper per cpp we might load/store.

For the partial load/store support I'm about to add, we want the memcpy to
be compiled out to a single load/store.  This should also eliminate the
calls to vc4_utile_width/height().

Improves x11perf -putimage100 performance by  3.76344% +/- 1.16978% (n=15)

6 years agovc4: Refactor to reuse the LT tile walking code.
Eric Anholt [Wed, 1 Mar 2017 01:39:23 +0000 (17:39 -0800)]
vc4: Refactor to reuse the LT tile walking code.

6 years agowayland/egl: update surface size on window resize
Juan A. Suarez Romero [Wed, 6 Jun 2018 10:13:05 +0000 (10:13 +0000)]
wayland/egl: update surface size on window resize

According to EGL 1.5 spec, section 3.10.1.1 ("Native Window Resizing"):

  "If the native window corresponding to _surface_ has been resized
   prior to the swap, _surface_ must be resized to match. _surface_ will
   normally be resized by the EGL implementation at the time the native
   window is resized. If the implementation cannot do this transparently
   to the client, then *eglSwapBuffers* must detect the change and
   resize surface prior to copying its pixels to the native window."

So far, resizing a native window in Wayland/EGL was interpreted in Mesa
as a request to resize, which is not executed until the first draw call.
And hence, surface size is not updated until executing it. Thus,
querying the surface size with eglQuerySurface() after a window resize
still returns the old values.

This commit updates the surface size values as soon as the resize is
done, even when the real resize is done in the draw call. This makes the
semantics that any native window resize request take effect inmediately,
and if user calls eglQuerySurface() it will return the new resized
values.

v2: update surface size if there isn't a back surface (Daniel)

CC: Daniel Stone <daniel@fooishbar.org>
CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Daniel Stone <daniels@collabora.com>
6 years agowayland/egl: initialize window surface size to window size
Juan A. Suarez Romero [Mon, 4 Jun 2018 10:22:49 +0000 (10:22 +0000)]
wayland/egl: initialize window surface size to window size

When creating a windows surface with eglCreateWindowSurface(), the
width and height returned by eglQuerySurface(EGL_{WIDTH,HEIGHT}) is
invalid until buffers are updated (like calling glClear()).

But according to EGL 1.5 spec, section 3.5.6 ("Surface Attributes"):

  "Querying EGL_WIDTH and EGL_HEIGHT returns respectively the width and
   height, in pixels, of the surface. For a window or pixmap surface,
   these values are initially equal to the width and height of the
   native window or pixmap with respect to which the surface was
   created"

This fixes dEQP-EGL.functional.color_clears.* CTS tests

v2:
- Do not modify attached_{width,height} (Daniel)
- Do not update size on resizing window (Brendan)

CC: Daniel Stone <daniel@fooishbar.org>
CC: Brendan King <brendan.king@imgtec.com>
CC: mesa-stable@lists.freedesktop.org
Tested-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Daniel Stone <daniels@collabora.com>
6 years agotravis: make drivers explicit in Meson targets
Juan A. Suarez Romero [Wed, 8 Aug 2018 11:27:32 +0000 (13:27 +0200)]
travis: make drivers explicit in Meson targets

Like in the autotools target, make the list of drivers to be built in
each of the Meson targets explicit.

This will help to identify missing dependencies and other issues more
easily.

CC: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>