i965: Only enable depth IZ signals if there's an actual depthbuffer.

According to the G45 PRM Volume 2 Page 265 we're supposed to only set
these signals when there is an actual depth buffer.  Note that we
already do this for the stencil buffer by virtue of brw->stencil_enabled
invoking _mesa_is_stencil_enabled(ctx) which checks whether the current
drawbuffer's visual has stencil bits (which is updated based on what
buffers are bound).  We just need to do it for depth as well.

Not observed to fix anything.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 70fe38444429d380810de38ad38edf53c3cefe89..db632ed15e1be9b472f755b9b75f9103f1e0dae3 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -35,6 +35,7 @@
 #include "program/program.h"
 #include "intel_mipmap_tree.h"
 #include "intel_image.h"
+#include "intel_fbo.h"
 #include "compiler/brw_nir.h"
 #include "brw_program.h"
 
@@ -456,6 +457,9 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key)
    /* Build the index for table lookup
     */
    if (devinfo->gen < 6) {
+      struct intel_renderbuffer *depth_irb =
+         intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
+
       /* _NEW_COLOR */
       if (prog->info.fs.uses_discard || ctx->Color.AlphaEnabled) {
          lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT;
@@ -466,11 +470,12 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key)
       }
 
       /* _NEW_DEPTH */
-      if (ctx->Depth.Test)
+      if (depth_irb && ctx->Depth.Test) {
          lookup |= BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT;
 
-      if (brw_depth_writes_enabled(brw))
-         lookup |= BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT;
+         if (brw_depth_writes_enabled(brw))
+            lookup |= BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT;
+      }
 
       /* _NEW_STENCIL | _NEW_BUFFERS */
       if (brw->stencil_enabled) {