clover/device: Move device_version into core and add device_clc_version

The device version is the maximum CL version that the device supports.

device_version and device_clc_version are not necessarily the same for
devices that support CL 1.0, but have a 1.1 compiler and the necessary
extensions.

Eventually, this will be based on the features/extensions of the actual
device, but for now move it a bit closer to its eventual destination.

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Jan Vesey <jan.vesely@rutgers.edu>

radv: avoid GPU hangs if someone does a resolve with non-multisample src (v2)

This is a bug in the app, but I'd rather avoid hanging the GPU,
esp if someone is running in validation and it takes out their
development environment.

v2: get it right, reverse the polarity.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

loader: drop the [gs]et_swap_interval callbacks

Having two callbacks to manage a single int seems like an overkill.
Use a cached copy and update that when needed.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
---
Might want to look if the dimensions dance in .query_surface ...
speaking of which close to nobody implements that ...

egl/x11: don't leak xfixes_query in the error path

If we get a xfixes v1.x we'll error out, without freeing the
xfixes_query reply.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

loader: rework xmlconfig dependency

Currently xmlconfig is conditionally used, only when --enable-dri is
available.

As the library has moved to src/util and has wider wisebase, this guard
is no longer correct. Strictly speaking - it wasn't since the
introduction of xmlconfig into st/nine a while ago.

Unconditionally enable xmlconfig and drop the linking. As said before
there's other users of the library, so depending on the configure
options we will get multiple definitions of said symbols.

NOTE: To avoid breaking other combinations, this commit adds the
xmlconfig link to the required places - throughout gallium and the DRI
loaders.

Cc: Aaron Watry <awatry@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

i965: Reduce passing 2x32b of reloc_domains to 2 bits

The kernel only cares about whether the object is to be written to or
not, only reduces (reloc.read_domains, reloc.write_domain) down to just
!!reloc.write_domain. When we use NO_RELOC, the kernel doesn't even read
those relocs and instead userspace has to pass that information in the
execobject.flags. We can simplify our reloc api by also removing the
unused read/write domains and only pass the resultant flags.

The caveat to the above are when we need to make the kernel aware that
certain objects need to take into account different work arounds.
Previously, this was done using the magic (INSTRUCTION, INSTRUCTION)
reloc domains. NO_RELOC requires this to be passed in the execobject
flags as well, and now we push that up the callstack.

The API is more compact, more expressive of what happens underneath, but
unfortunately requires more knowledge of the system at the point of use.
Conversely it also means that knowledge is specific and not generally
applied and so not overused.

   text    data     bss     dec     hex filename
8502991  356912  424944 9284847  8dacef lib/i965_dri.so (before)
8500455  356912  424944 9282311  8da307 lib/i965_dri.so (after)

v2: (by Ken) Rebase.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Convert reloc.target_handle into an index for I915_EXEC_HANDLE_LUT

Based on a patch by Chris Wilson (who also wrote this commit message).

Passing the index of the target buffer via the reloc.target_handle is
marginally more efficient for the kernel (it can avoid some allocations,
and can use a direct lookup rather than a hash or search). It is also
useful for ourselves as we can use the index into our exec_bos for other
tasks.

v2: Only enable HANDLE_LUT if we can use BATCH_FIRST and thereby avoid
a post-processing loop to fixup the relocations.
v3: Move kernel probing from context creation to screen init.
Use batch->use_exec_lut as it more descriptive of what's going on (Daniel)
v4: Kernel features already exists, use it for BATCH_FIRST
Rename locals to preserve current flavouring
v5: Squash in "always insert batch bo first"
v6: (by Ken) Split out BATCH_FIRST from HANDLE_LUT.

i965: Use a C99 initializer for new validation list entries.

More succinct - we can skip a bunch of = 0 lines.

Extracted from a patch by Chris Wilson.

i965: Simplify some bo != batch->bo special cases.

Extracted from a patch by Chris Wilson.

Now that the batch is always at the front of the validation list,
we don't need to special case it - the usual "go find an existing BO"
code will work just fine.

i965: Use I915_EXEC_BATCH_FIRST when available.

This will make it easier to use I915_EXEC_HANDLE_LUT.

Based on a patch by Chris Wilson.

i965: Move add_exec_bo()

To avoid a forward declaration in the next patch, move the definition of
add_exec_bo() earlier.

v2: (by Ken) redo move.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Ignore reloc read/write domains

Since before the kernel supported I915_EXEC_NO_RELOC, long before our
minimum kernel requirement, the kernel unconditionally invalidated all
GPU TLBs before a batch and flushed all GPU caches after a batch. At
that moment, the only use for read/write domain was for activity
tracking, ensuring that future reads waited for the last writer and
future writes waited for all reads. This only requires a single bit in
the execbuf interface which can be supplied via the NO_RELOC interface,
making the use of relocation domains entirely redundant.

Trimming the excess writes into the array allows the compiler to be much
more frugal:

   text    data     bss     dec     hex filename
8493790  357184  424944 9275918  8d8a0e i965_dri.baseline
8493758  357184  424944 9275886  8d89ee i965_dri.so

(This text improvement really does come from dropping domains, not from
the new use of C99 initializers.)

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Use I915_EXEC_NO_RELOC

If we correctly fill the batch with the right relocation value, and that
matches the expected location of the object, we can then tell the kernel
it can forgo checking each individual relocation by only checking
whether the object moved.

v2: Rebase to apply ahead of I915_EXEC_HANDLE_LUT

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Initialize flags to 0 and |= in new flags.

This makes it a bit easier to add new unconditional flags.

i965: Make add_exec_bo return the validation list index.

This will be useful for I915_EXEC_HANDLE_LUT and I915_EXEC_NO_RELOC.

i965: Track last location of bo used for the batch

Borrow a trick from anv, and use the last known index for the bo to skip
a search of the batch->exec_bo when adding a new relocation. In defence
against the bo being used in multiple batches simultaneously, we check
that this slot exists and points back to us.

v2: Also update brw_batch_references()
v3: Reset bo->index on creation (Daniel)
v4: Improved explanation of bo->index (Kenneth)

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Always use the pre-computed offset for the relocation entry

We must be careful to only compute the address once based on the
per-context information (rather than accessing the unlocked global
bo->offset64) so that the value in the batch does match the
reloc.presumed_offset we declare to the kernel. Otherwise, highly
unlikely, but we may see GPU hangs in multithreaded users.

The only real complication here is isl_surf_fill_state() which needs to
adjust the reloc.delta to both general a tile offset and to encode state
into the lower 12 bits.

(Rebased on ISL changes by Ken.)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Make brw_emit_reloc assert that the target BO is non-NULL.

You need an actual BO to emit a relocation to it.

Suggested by me, authored by Chris, split out of a larger patch.

configure.ac: drop manual detection of expat header/library

Use the .pc file, as provided by version prior 2.1.0 onward and dropping
the manual header/library check.

Version 2.1.0 was released back in Mar 2012 and all major distributions
use it.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (IRC)

configure.ac: unconditionally check for expat

Earlier commits moved the xmlconfig library to a wider userbase.
Thus having the check within --enable-dri is insufficient.

Upon closer look, nine needed it from it's early days - 948e6c52282
("nine: Add drirc options (v2)")

Fixes: 601093f95ddf ("xmlconfig: move into src/util")
Cc: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (IRC)

android: radeonsi: add nir include paths

Android build changes to avoid the following building error:

target  C: libmesa_pipe_radeonsi <= external/mesa/src/gallium/drivers/radeonsi/si_pipe.c
...
In file included from external/mesa/src/gallium/drivers/radeonsi/si_pipe.c:38:
external/mesa/src/compiler/nir/nir.h:48:10: fatal error: 'nir_opcodes.h' file not found
         ^
1 error generated.

Fixes: da62a31c5b "radeonsi: add nir include paths"
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

i965: Prefer using streaming reads from WC mmaps

For buffer objects, where we primarily expect to be writing to them and
so already have a WC mmap (for !llc access) reusing the existing mmap
and keeping the buffer out of the CPU cache seems preferable.

Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Matt Turner <mattst88@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

pipe-loader: fix swrast probing

Missed updating this caller of pipe_loader_find_module.

Fixes: 0d7d60b7ea ("pipe-loader: pass only the driver_name to pipe_loader_find_module")
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

pipe-loader: remove config from pipe_loader_create_screen

The config passed into the screen should be independent from the state
tracker, because at least in the case of radeonsi, the screen structure
can be shared between different state trackers.

Incidentally, this also fixes crashes that were recently introduced.

Fixes: a35a9e7c ("gallium: add driconf options to pipe_screen_config")
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: get rid of pipe_screen_config::flags

They were set only by the DRI state tracker, which is problematic
when radeonsi is used with different state trackers in the same
process.

Also, we don't need them anymore.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: set drirc compiler options before calling common screen init

Also, access the options directly, allowing us to get rid of the
PIPE_SCREEN_xxx flags.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

util: Makefile.am: add merge_driinfo.py in extra dist

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

radeonsi: Makefile.sources: include driinfo_radeonsi.h

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

anv: Makefile.vulkan.am: ICD json files are now generated with python

Commit 0ab04ba979b7 (anv: Use python to generate ICD json files) changed
the way ICD json files are created.

Remove the old .in files from extra dist, and add the python script.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

radv: also fix texture image descriptors for mipmap tile swizzle

This fixes the image descriptors for mipmapped tile swizzle

Fixes: 2b7e8556 (ac/surface: enable tile swizzle for mipmapped textures)
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: fix tile swizzle regression on mipmaps.

When Marek enabled mipmapped swizzle, radv didn't
have the code in place to handle it. This fixes the
regression.

I'll look more into GFX9 once I have a vega card (soon).
Fixes: 2b7e8556 (ac/surface: enable tile swizzle for mipmapped textures)
Signed-off-by: Dave Airlie <airlied@redhat.com>

pipe-loader: Add driver build directory for si_driinfo.h include path

Fixes out-of-tree build failure:

.../src/gallium/targets/pipe-loader/pipe_radeonsi.c: In function ‘drm_configuration’:
.../src/gallium/targets/pipe-loader/pipe_radeonsi.c:38:33: fatal error: radeonsi/si_driinfo.h: No such file or directory
 #include "radeonsi/si_driinfo.h"
                                 ^
compilation terminated.
Makefile:994: recipe for target 'pipe_radeonsi.lo' failed
make[4]: *** [pipe_radeonsi.lo] Error 1

Trivial.

Fixes: 0f8c5de8690e7c ("radeonsi: prepare for driver-specific driconf
                        options")

clover: Fix build after llvm r309911

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

radeonsi: program tile swizzle for color and FMASK surfaces for GFX & SDMA

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: if FMASK is disabled, set CB_COLORi_FMASK = CB_COLORi_BASE properly

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: reallocate textures with non-zero tile_swizzle on export

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: enable computation of tile swizzle

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface: align DCC size for surfaces that use tile swizzle

Note that dcc_alignment = pipe_interleave_bytes * num_pipes * num_banks,
which is greater than the previous open-coded alignment.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface: limit tile swizzle to non-mipmaps on SI

Mipmapping with tile swizzle doesn't work.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface: enable tile swizzle for mipmapped textures

The tile swizzle computation was done after the whole miptree was computed,
but that was too late, because at that point AddrSurfInfoOut contained
information about the smallest miplevel, which is never 2D-tiled.

The correct way is to do the computation before the second level is computed.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface: set structure size and handle errors for AddrComputeBaseSwizzle

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface: increment surf_index only when tile swizzle is allowed

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface: compute tile swizzle only when it's allowed

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface: add RADEON_SURF_SHAREABLE

Shareable textures won't use tile swizzle.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface: remove RADEON_SURF_HAS_TILE_MODE_INDEX

it's useless

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface: move tile_swizzle to ac_surface and document it

Gfx9 will use it too.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/mesa: fix handling of NumSamples=1 (v2)

In Mesa we use the convention that if gl_renderbuffer::NumSamples
or gl_texture_image::NumSamples is zero, it's a non-MSAA surface.
Otherwise, it's an MSAA surface.  But in gallium nr_samples=1 is a
non-MSAA surface.

Before, if the user called glRenderbufferStorageMultisample() or
glTexImage2DMultisample() with samples=1 we skipped the search for the
next higher number of supported samples and asked the gallium driver to
create a surface with nr_samples=1.  So we got a non-MSAA surface.
This failed to meet the expection of the user making those calls.

This patch changes the sample count checks in st_AllocTextureStorage()
and st_renderbuffer_alloc_storage() to test for samples > 0 instead of > 1.
And we now start querying for MSAA support at samples=2 since gallium has
no concept of a 1x MSAA surface.

A specific example of this problem is the Piglit arb_framebuffer_srgb-blit
test.  It calls glRenderbufferStorageMultisample() with samples=1 to
request an MSAA renderbuffer with the minimum supported number of MSAA
samples.  Instead of creating a 4x or 8x, etc. MSAA surface, we wound up
creating a non-MSAA surface.

Finally, add a comment on the gl_renderbuffer::NumSamples field.

There is one piglit regression with the VMware driver:
ext_framebuffer_multisample-blit-mismatched-formats fails because
now we're actually creating 4x MSAA surfaces (the requested sample
count is 1) and we're hitting some sort of bug in the blitter code.  That
will have to be fixed separately.  Other drivers may find regressions
too now that MSAA surfaces are really being created.

v2: start quering for MSAA support with samples=2 instead of 1.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/docs: add more info about TXF and MSAA textures

If the texture is multisampled, the coord.w component indicates which
sample to fetch.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: minor clean-ups in st_atom_msaa.c

Whitespace, formatting, combine nr_bits assignment with declaration.
Trivial.

gallium/docs: document automatic per-sample FS execution

Both the GLSL 4.00 specs and DX10.1 specs specify that if a fragment
shader uses the sample ID or sample position inputs, the shader is
automatically run at per sample frequency.  Document that expectation
for gallium fragment shaders.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: init more msaa fields

The default values for GL_SAMPLE_SHADING and GL_MIN_SAMPLE_SHADING_VALUE
are missing from the state tables in the GL spec, but they're supposed
to be GL_FALSE and 0.0, per the GL_ARB_sample_shading spec.

Add code for that, just to be explicit.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

swr: Add arch flags to support Cray and PGI compilers

Note that the Cray flags (-target-cpu=) need to come first since the
cray programming environment uses wappers around other compilers.  By
checking the wrapper flags first, you can be sure to match the wrapper
flag instead of the underlying compiler (gcc, intel, pgi, etc.) flags.

Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

st/osmesa: add osmesa framebuffer iface hash table per st manager

Commit bbc29393d3 didn't include osmesa state_tracker.  This patch adds
necessary initialization.

Fixes crash in OSMesa initialization.

Created-by: Charmaine Lee <charmainel@vmware.com>
Tested-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Cc: 17.2 <mesa-stable@lists.freedesktop.org>

anv: put anv_extensions.c in gitignore

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

pipe-loader: fix build of dynamic pipe-drivers

v2: add libxmlconfig.la to the dynamic pipe_radeonsi driver
v3: add libxmlconfig.la to targets/opencl build
v4: add EXPAT_LIBS to opencl build
    (note: for only-opencl builds, Emil's configure.ac changes
     are also needed)

Fixes: bc7f41e11d3 ("gallium: add pipe_screen_config to screen_create functions")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102014
Tested-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (v1)

android: anv_extensions.c is generated to libmesa_vulkan_common

Fixes build error with anv_extensions.c not found for
libmesa_anv_entrypoints.

Fixes: d62063c "anv: Autogenerate extension query and lookup"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

android: radeonsi: prepare for driver-specific driconf options

Android build changes to avoid the following building error:

In file included from external/mesa/src/gallium/targets/dri/target.c:1:
external/mesa/src/gallium/auxiliary/target-helpers/drm_helper.h:185:10:
fatal error: 'radeonsi/si_driinfo.h' file not found
         ^
1 error generated.

Fixes: 0f8c5de869 "radeonsi: prepare for driver-specific driconf options"
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

android: ac/common: always build NIR translation

Android build changes to avoid the following building error:

external/mesa/src/gallium/drivers/radeonsi/si_shader_nir.c:505:
error: undefined reference to 'ac_nir_translate'

Fixes: 86d4b46d66 "ac/common: always build NIR translation"
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

mesa: only check errors when the state change in glLogicOp()

When this GL call is a no-op, it should be a little faster.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: only check errors when the state change in glBlendEquationSeparateiARB()

When this GL call is a no-op, it should be a little faster.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

i965: Drop unnecessary I915_PARAM_HAS_EXEC_CAPTURE defines

These were only here to keep building without needing to update libdrm.
Now that we include i915_drm.h in Mesa, we don't need this - our copy
is new enough and has the #define.

Trivial.

ac: add ac_shader_abi.h in distcheck

Fixes:

  CXXLD    addrlib/libamdgpu_addrlib.la
ar: `u' modifier ignored since `D' is the default (see `U')
../../../../src/amd/common/ac_nir_to_llvm.c:33:27: fatal error:
ac_shader_abi.h: No such file or directory
 #include "ac_shader_abi.h"
                           ^
compilation terminated.
Makefile:985: recipe for target
'common/common_libamd_common_la-ac_nir_to_llvm.lo' failed

When running `make distcheck`

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

intel/vec4/gs: reset nr_pull_param if DUAL_INSTANCED compile failed.

If dual object compile fails (as seems to happen with virgl a
fair bit, and does piglit even have any tests for it?), we end up
not restarting the pull params, so we call
vec4_visitor::move_uniform_array_access_to_pull_constant
a second time and it runs over the ends of the alloc.

Fixes: tests/spec/glsl-1.50/execution/geometry/max-input-components.shader_test
running inside virgl on ivybridge.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

st/dri2 Plumb the flush_swapbuffer functionality through to dri3

Implement the state tracker manager drawable interface flush_swapbuffer
method by plumbing it through to dri3 if available.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>

gallium/st: Add a method to flush outstanding swapbuffers

Add a state tracker interface method to flush outstanding swapbuffers, and
add a call to it from the mesa state tracker during glFinish().
This doesn't strictly mean the outstanding swapbuffers have actually finished
executing but is sufficient for glFinish()
to be able to be used as a replacement for glXWaitGL().

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>

glx/dri3: Implement the flush_swapbuffers method

Provide a dri3 implementation for the image loader extension method.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

dri: Add a flushSwapBuffers method to the image loader extension

This method may be used by dri drivers to make sure all outstanding
buffer swaps have been flushed to hardware.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

gallium: introduce PIPE_CAP_MEMOBJ

This can be used to guard support for EXT_memory_object and related
extensions.

v2: update gallium docs

v3 (Timothy Arceri):
 - add cap to nv50

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

i965/blit: Remember to include miptree buffer offset in relocs

Remember to add the offset to the start of the buffer in the relocation
or else we write 0xff into random bytes elsewhere.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org

i965: Fix indentation

radv: Add suballocation for shaders.

This reduces the number of BOs that we need for the BO lists during
a submission.

Currently uses a fairly simple linear search for finding free space,
that could eventually be improved to a binary tree, which with some
per-node info could make a check for space O(1) and finding it O(log n),
in the number of buffers in that slab.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

docs: Add Vulkan to features.txt

To get the extension list:

$ git grep -hE "extension name=\"VK_KHR" src/vulkan/registry/vk.xml | \
  grep -v disabled | awk '{print $2}' | sed -E 's/(name=)?"//g' | sort

To find anv(il) and radv supported extensions:

$ git grep -hE "'VK_([A-Z]+)_[a-z]" src/intel/

$ git grep -hE "'VK_([A-Z]+)_[a-z]" src/amd/

v2:
 * Add radv to Vulkan 1.0 list (Bas)
 * 'started' => 'in progress'
 * Drop KHX and EXT extensions (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

i965: Set "Subslice Hashing Mode" to 16x16 on Apollolake.

As of 4.11, the kernel isn't bothering to set the subslice hashing mode
on Apollolake, leaving it at the default of 8x8.  (It initializes it to
16x4 on most platforms.)

Performance data for GPUTest Triangle on Apollolake at 1024x640:

   X-tiled RT:
   -----------
   8x8 -> 16x4:   2.4325%  +/- 0.383683% (n=107)
   8x8 -> 8x4:   -3.75105% +/- 0.592491% (n=40)
   8x8 -> 16x16:  6.17238% +/- 0.67157%  (n=30)

   Y-tiled RT:
   -----------
   8x8 -> 16x4:   1.30307%  +/- 0.297292% (n=205)
   8x8 -> 8x4:   -0.769282% +/- 0.729557% (n=35)
   8x8 -> 16x16:  3.00254%  +/- 0.715503% (n=40)

   8x MSAA RT (INTEL_FORCE_MSAA=8):
   --------------------------------
   8x8 -> 16x4:   1.38889% +/- 0.93729%  (n=7)
   8x8 -> 8x4:   -2.10643% +/- 1.15153%  (n=3)
   8x8 -> 16x16:  3.87183% +/- 1.08851%  (n=5)

Based on this, we choose 16x16 for Apollolake.

Skylake GT2 with X-tiled buffers appears to be a toss-up between 16x4
and 16x16, and with Y-tiled buffers it doesn't seem to really matter.
So we'll leave Skylake alone for now.

The hashing mode doesn't seem to make a measurable impact on more
complex benchmarks.

Acked-by: Matt Turner <mattst88@gmail.com>

mesa/dri: drop unneeded mm.h include

This isn't used in any of these drivers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r300: drop u_mm.h include.

This is not used in any of these files.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

util: use cannonical form of ARRAY_SIZE

Namely sizeof(foo)/sizeof((foo)[0])

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

i965: simplify intel_image_format_lookup()

Drop the local variable and return directly.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: annotate struct intel_image_format as const

Already used as such througout the code.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

st/dri: NULL check before deref DRI loader .getCapability

One could have vX+1 which introduces another entrypoint without
implementing older ones.

v2: Rebase, while keeping loaderPrivate

Fixes: 1bf703e4ea5 ("dri_interface,egl,gallium: only expose RGBA visuals
on Android")
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

egl: check the correct function pointer

`.swap_interval` != `.SwapInterval`...

Fixes: 991ec1b81a76de24fd01 "egl: make platform's SwapInterval() optional"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102015
Cc: Cedric Sodhi <manday@openmail.cc>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Tested-by: Cedric Sodhi <manday@openmail.cc>

i965: Delete pitch alignment assertion in get_blit_intratile_offset_el.

The cacheline alignment restriction is on the base address; the pitch
can be anything.

Fixes assertion failures when using primus (say, on glxgears, which
creates a 300x300 linear BGRX surface with a pitch of 1200):

intel_blit.c:190: get_blit_intratile_offset_el: Assertion `mt->surf.row_pitch % 64 == 0' failed.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

swr/rast: fix core / knights split of AVX512 intrinsics

Move AVX512BW specific intrinics to be Core-only.

Move some AVX512F intrinsics back to common implementation file.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: simplify knob default value setup

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: split gen_knobs templates into .h/.cpp

Switch to a 1:1 mapping template:generated for future maintenance.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: gen_knobs template code style

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: switch gen_knobs.cpp license

Unintentionally added with an apache2 license; relicense to match
the rest of the tree.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: fix scons gen_knobs.h dependency

Copy/paste error was duplicating a gen_knobs.cpp rule.

Fixes: 5079c277b57 ("swr: [scons] Fix windows build")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: constify swr rasterizer

Add "const" as appropriate in method/function signatures.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 shaders - widen fetch and vertex shaders

Work in progress, disabled by default.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: vmask() implementations for KNL

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: rename frontend pVertexStore

Rename to reflect global nature.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: fix movemask_ps / movemask_pd on AVX512

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: stop using MSFT types in platform independent code

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: enable USE_SIMD16_FRONTEND by default

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: disable AVX512 optimization of SSE / AVX code

Disable an optimization which implemented sse/avx operations on avx512
using avx512 intrinsics (to avoid switching between lane widths).

Compile with SIMD_OPT_128_AVX512 / SIMD_OPT_256_AVX512 defined to enable
these optimizations.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: fix USE_SIMD16_FRONTEND issues

Fix problems found when enabling USE_SIMD16_FRONTEND, mostly related to
vMask / movemask_ps(pd).

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: simdlib better separation of core vs knights avx512

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: threadID via portable std::this_thread::get_id()

Replace use of Win32 GetCurrentThreadId() with portable
std::this_thread::get_id().

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

spirv: Fix SpvImageFormatR16ui

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "17.1 17.2" <mesa-stable@lists.freedesktop.org>

anv: Advertise VK_KHR_relaxed_block_layout

There is literally no work for us to do here.  It already just works in
our driver.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>