radeon/uvd: add and manage render picture list

Create a list in decoder to store all render picture buffer pointers that
currently being used in reference picture lists.

During get message buffer call, check each pointer in render_pic_list[]
within given pic->ref[] list, remove pointer that no longer being used by
pic->ref[]. Then add current render surface pointer to the render_pic_list[]
and assign the associated index to result.curr_idx.

As a result, result.curr_idx will have the correct index to represent the
current render picture, instead of the previous increamenting values.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: add and manage render picture list

Create a list in decoder to store all render picture buffer pointers that
currently being used in reference picture lists.

During get message buffer call, check each pointer in render_pic_list[]
within given pic->ref[] list, remove pointer that no longer being used by
pic->ref[]. Then add current render surface pointer to the render_pic_list[]
and assign the associated index to result.curr_idx.

As a result, result.curr_idx will have the correct index to represent the
current render picture, instead of the previous increamenting values.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

vl: remove is idr flag

Remove is_idr flag since not being used anymore.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: directly use idr pic flag

Remove is_idr flag, and use idr_pic_flag provided by vaapi directly

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vce: determine idr by pic type

Vaapi encode interface provides idr frame flags, where omx interface doesn't.
Therefore, change to use picture type to determine idr frame, which will
work for both interfaces.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

radeon/vcn: determine idr by pic type

Vaapi encode interface provides idr frame flags, where omx interface doesn't.
Therefore, change to use picture type to determine idr frame, which will
work for both interfaces.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

util: scons: wire up the sha1 test

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

swr/rast: Move more RTAI handling out of binner

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: EXTRACT2 changed from vextract/vinsert to vshuffle

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Fix cache of API thread event manager

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Replace VPSRL with LSHR

Replace use of x86 intrinsic with general llvm IR instruction.

Generates the same final assembly.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Rework thread binding parameters for machine partitioning

Add BASE_NUMA_NODE, BASE_CORE, BASE_THREAD parameters to
SwrCreateContext.

Add optional SWR_API_THREADING_INFO parameter to SwrCreateContext to
control reservation of API threads.

Add SwrBindApiThread() function to allow binding of API threads to
reserved HW threads.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Pull of RTAI gather & offset out of clip/bin code

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Remove no-op VBROADCAST of vID

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 Fetch - Fully widen 32-bit integer vertex components

Also widen the 16-bit a 8-bit integer vertex component gathers to SIMD16.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Replace INSERT2 vextract/vinsert with JOIN2 vshuffle

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 Fetch - Fully widen 16-bit float vertex components

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 Fetch - Fully widen 32-bit float vertex components

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Pass prim to ClipSimd

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Pull most of the VPAI manipulation out of the binner/clipper

Move out of binner/clipper; hand them down from the frontend code instead.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Move GatherScissors to header

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Rewrite Shuffle8bpcGatherd using shuffle

Ease future code maintenance, prepare for folding simd8 and simd16 versions.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Convert gather masks to Nx1bit

Simplifies calling code, gets gather function interface closer to llvm's
masked_gather.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: WIP - Widen fetch shader to SIMD16

Widen vertex gather/storage to SIMD16 for all component types.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Corrections to multi-scissor handling

binner's GatherScissors() will be turned into a real gather in the not
too distant future.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Binner fixes for viewport index offset handling

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Remove unneeded copy of gather mask

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

i965: Allow old begin/end queryobj for gen4/5 with HW contexts

Since we have HW contexts on gen4/5, we could take advantage of them, as
done for gen6+ in commit e32cd5ffbb72 ("i965: Rely on hardware contexts
for query objects on Gen6+."), to only emit a pair of counters at
begin/end queryobj, rather than around every primitive. However, to keep
queryobj working in the meantime as we bringup support for HW ctx on
gen4/5, we can keep using the existing code.

References: e32cd5ffbb72 ("i965: Rely on hardware contexts for query objects on Gen6+.")
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

freedreno: use u_transfer_helper

Signed-off-by: Rob Clark <robdclark@gmail.com>

gallium/util: add u_transfer_helper

Add a new helper that drivers can use to emulate various things that
need special handling in particular in transfer_map:

 1) z32_s8x24.. gl/gallium treats this as a single buffer with depth
    and stencil interleaved but hardware frequently treats this as
    separate z32 and s8 buffers.  Special pack/unpack handling is
    needed in transfer_map/unmap to pack/unpack the exposed buffer

 2) fake RGTC.. GPUs designed with GLES in mind, but which can other-
    wise do GL3, if native RGTC is not supported it can be emulated
    by converting to uncompressed internally, but needs pack/unpack
    in transfer_map/unmap

 3) MSAA resolves in the transfer_map() case

v2: add MSAA resolve based on Eric's "gallium: Add helpers for MSAA
    resolves in pipe_transfer_map()/unmap()." patch; avoid wrapping
    pipe_resource, to make it possible for drivers to use both this
    and threaded_context.

Signed-off-by: Rob Clark <robdclark@gmail.com>

i965: enable EXT_disjoint_timer_query extension

Following dEQP cases pass:
   dEQP-EGL.functional.get_proc_address.extension.gl_ext_disjoint_timer_query
   dEQP-EGL.functional.client_extensions.disjoint

Piglit test 'ext_disjoint_timer_query-simple' passes with these changes.

No changes/regression observed in Intel CI.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: GL_EXT_disjoint_timer_query extension API bits

Patch adds GL_GPU_DISJOINT_EXT and enables to use timer queries when
EXT_disjoint_timer_query is enabled.

v2: enable extension only when EXT_disjoint_timer_query set

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glapi: add GL_EXT_disjoint_timer_query

Most entrypoints already available via other extensions like
GL_EXT_occlusion_query_boolean, GL_EXT_timer_query.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: add DisjointOperation to gl_shared_state

This state will be used by EXT_disjoint_timer_query. As first
usage, patch sets DisjointOperation true when gpu reset happens.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

broadcom/vc5: Fix a typo in memcmp for sig unpack checking.

This shockingly ended up working out, because only the first byte of *sig
is used and (sizeof(*sig) != 0) == 1.  Fixes a compiler warning.

Link: https://bugs.freedesktop.org/show_bug.cgi?id=104183

broadcom/vc5: Enable NIR txd lowering on all txd instructions.

Fixes almost all of piglit's arb_shader_texture_lod grad tests, except for
the base -texgrad/texgradcube ones which fail on what appear to be
precision problems.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nir: Add a new lowering option to lower all txd to txl.

VC5 requires that all txd are lowered in the shader.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nir: Fix interaction of GL_CLAMP lowering with texture offsets.

We want the clamping of the coordinate to apply after the offset, so we
need to do math to lower the offset out of the instruction.  Fixes texwrap
offset cases for GL_CLAMP with GL_NEAREST on vc5.

Note: I moved the get_texture_size() verbatim, so that it was defined
before use.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

broadcom/vc5: Fix shader input/outputs for gallium's new NIR linking.

gallivm: implement accurate corner behavior for textureGather with cube maps

The spec says the missing texel (when we wrap around both x and y axis)
should be synthesized as the average of the 3 other texels. For bilinear
filtering however we instead adjusted the filter weights (because, while
the complexity looks similar, there would be 4 times as many color values
to fix up than weights). Obviously this could not work for gather (hence
accurate corner filtering was disabled with gather).
Implement this by just doing it as the spec implies - calculate the 4th
texel as the average of the other 3. With gather of course there's only
one color to worry about, so it's not all that many instructions neither
(albeit surely the whole cube map filtering is hilariously complex).

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

gallivm: fix an issue with NaNs with seamless cube filtering

Cube texture wrapping is a bit special since the values (post face
projection) always are within [0,1], so we took advantage of that and
omitted some clamps.
However, we can still get NaNs (either because the coords already had NaNs,
or the face projection generated them), and in fact we didn't handle them
quite safely. I've seen -INT_MAX + 1 been propagated through as the final int
coord value, albeit I didn't observe a crash. (Not quite a coincidence, since
any stride mul with -INT_MAX or -INT_MAX+1 will turn up as a small positive
number - nevertheless, I'd rather not try my luck, I'm not entirely sure it
can't really turn up negative neither due to seamless coord swapping, plus
ifloor of a NaN is not guaranteed to return -INT_MAX by any standard. And
we kill off NaNs similarly with ordinary texture wrapping too.)
So kill off the NaNs by using the common max against zero method.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

intel/tools: Convert aubinator over to the common framework

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: Decode registers

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: Decode dynamic state

Unfortunately, in aubinator and aubinator_error_decode we don't always
know how many of a given state we have, so we must guess.  One day,
we'll come up with a way to annotate the batch to solve this problem.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: Decode constants, binding tables, and samplers

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/tools: Switch aubinator_error_decode over to the gen_print_batch

The shared framework can now do everything that aubinator_error_decode
ever did and more.  It's time to make the switch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: Decode graphics shaders

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: Decode vertex and index buffers

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: Decode MEDIA_INTERFACE_DESCRIPTOR_LOAD

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/tools: Add the start of a generic batch decoder

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/decoder: Expose the raw field value in the iterator

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/disasm: Take a devinfo in gen_disasm_create

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/decoder: Take a bit offset in gen_print_group

Previously, if a group was nested in another group such that it didn't
start on a dword boundary, we would decode it as if it started at the
start of its first dword.  This changes things to work even more in
terms of bits so that we can properly decode these structs.  This
affects MOCS, attribute swizzles, and several other things.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/decoder: Stop rounding down to the nearest dword

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/decoder: Convert the iterator to work entirely in bits

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/decoder: Drop gen_field_decode helper

It's unused

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

amd/common: add ac_build_waitcnt()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

amd/common: more use of i32_1

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

amd/common: more use of i32_0

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radeonsi: make use of ac_build_fdiv()

And move the comment to amd/common.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: export SampleMask from pixel shaders at full rate

Use 16_ABGR instead of 32_ABGR if Z isn't written.

Ported from RadeonSI.

No CTS regressions on Polaris.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radeonsi: make use of ac_get_spi_shader_z_format()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

amd/common: add ac_get_spi_shader_z_format()

ac_shader_util.c will contain shader helpers for RadeonSI
and RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: do not load the local invocation index when it's unused

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components

We should also not load the input SGPRs and VGPRS, but
let's start with this for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

amd/common: scan which components of gl_LocalInvocationID are used

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

amd/common: scan which components of gl_WorkGroupID are used

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: set FORCE_SIMD_DIST(1) for compute when profitable

Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: calculate best compute resource limits

Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: store the dispatch initiator into the device

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: replace grid_components_used by uses_grid_size

Use a boolean instead because the number of needed SGPRs
is always 3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: always emit all compute block components

The number of grid components is always 3 when gl_NumWorkGroups
is declared, because it relies on the number of components of
nir_instrinsic_load_num_work_groups.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

docs: update calendar, add news item and link release notes for 17.2.7

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add sha256 checksums for 17.2.7

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add release notes for 17.2.7

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

egl/android: Provide an option for the backend to expose KHR_image

From android cts 8.0_r4, a new test case checks if all the required egl
extensions are exposed. In the current implementation we expose KHR_image
if KHR_image_base and KHR_image_pixmap are supported but KHR_image spec
does not mandate the existence of both the extensions.
This patch preserves the current check and also provides the backend
with an option to expose the KHR_image extension.

Test: run cts -m CtsOpenGLTestCases -t \
android.opengl.cts.OpenGlEsVersionTest#testRequiredEglExtensions

Signed-off-by: Harish Krupo <harish.krupo.kps@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

radv: Don't advertise VK_EXT_debug_report.

We never supported it. Missed during copy and pasting.

Fixes: 17201a2eb0b "radv: port to using updated anv entrypoint/extension generator."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

i965: Don't allocate an MCS for 16x MSAA and width > 8192.

The hardware doesn't support this, and isl_surf_get_mcs_surf will fail.

I feel a bit bad replicating this logic, but we want to decide up front.

This fixes the following test when run with --deqp-surface-width=16384:
- GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_framebuffers_different_sample_count

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

Android: fix missing generation of vtn_gather_types.c

Commit bb1e6ff161c9 ("spirv: Add a prepass to set types on vtn_values")
added generation of vtn_gather_types.c, but forgot to add it to the
Android build files.

Fixes: bb1e6ff161c9 ("spirv: Add a prepass to set types on vtn_values")
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Rob Herring <robh@kernel.org>

mesa: Add glSpecializeShaderARB to common_desktop_functions

CC: Nicolai Hähnle <nicolai.haehnle@amd.com>
CC: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104231
Fixes: 46b21b8f906 ("mesa: add GL_ARB_gl_spirv boilerplate")
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

egl/android: Partially handle HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED

There is no API available to properly query the IMPLEMENTATION_DEFINED
format. As a workaround we rely here on gralloc allocating either
an arbitrary YCbCr 4:2:0 or RGBX_8888, with the latter being recognized
by lock_ycbcr failing.

Reviewed-on: https://chromium-review.googlesource.com/566793

Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>

swr: Correct texture allocation and limit max size to 2GB

This patch fixes piglit tex3d-maxsize by correcting 4 things:

The total_size calculation was using 32-bit math, therefore a >4GB
allocation request overflowed and was not returning false (unsupported).

Changed AlignedMalloc arguments from "unsigned int" to size_t, to handle
>4GB allocations.

Added error checking on texture allocations to fail gracefully.

Finally, temporarily decreased supported max texture size from 4GB to 2GB.
The gallivm texture-sampler needs some additional work to correctly handle
larger than 2GB textures (offsets to LLVMBuildGEP are signed).

I'm working on a follow-on patch to allow up to 4GB textures, as this is
useful in HPC visualization applications.

Fixes piglit tex3d-maxsize.

v2: Updated patch description to clarify ">4GB".

Reviewed-By: George Kyriazis <george.kyriazis@intel.com>

swr: Fix KNOB_MAX_WORKER_THREADS thread creation override.

Environment variable KNOB_MAX_WORKER_THREADS allows the user to override
default thread creation and thread binding.  Previous commit to adjust
linux cpu topology caused setting this KNOB to bind all threads to a single
core.

This patch restores correct functionality of override.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

meson: fix glx-test race

This test should rely on dispatch.h being generated, but it doesn't.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

gallium/docs: document behavior of set_sample_mask()

The sample mask is used even if msaa is not explicity enabled when we
have a framebuffer with multisampled surfaces.  That's DX behavior and
what the Radeon drivers do.  Not sure about other drivers at this point.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

glsl: trivial whitespace fixes in link_varyings.cpp

program: Don't reset SamplersValidated when restoring from shader cache

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103988
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: remove second include of errors.h in src/mesa/main/glspirv.c

Fixes: 5bc03d2508 ("mesa: implement SPIR-V loading in glShaderBinary")
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

radeonsi: create get_tcs_tes_buffer_address helper

This will be shared between the NIR and TGSI backends.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: fix nir_op_f2f64

Without this we get the error "FPExt only operates on FP" when
converting the following:

   vec1 32 ssa_5 = b2f ssa_4
   vec1 64 ssa_6 = f2f64 ssa_5

Which results in:

   %44 = and i32 %43, 1065353216
   %45 = fpext i32 %44 to double

With this patch we now get:

   %44 = and i32 %43, 1065353216
   %45 = bitcast i32 %44 to float
   %46 = fpext float %45 to double

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

nir: fix shift for uint64_t

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/glsl_to_nir: skip forced array splitting for tcs

nir_lower_io_to_temporaries() does not support tcs so we cannot
assume there are no indirects here. Also the radeonsi backend
(the only backend to support tess) has support for tcs indirects
so there is no need to lower them anyway.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

intel/fs/bank_conflicts: Don't touch Gen7 MRF hack registers.

Fixes: af2c320190f3c731 "intel/fs: Implement GRF bank conflict mitigation pass."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104199
Reported-by: Darius Spitznagel <d.spitznagel@goodbytez.de>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: compute scratch space size correctly for Gen9+

Fixes: 8ecdbb61360 "i965: Pretend there are 4 subslices for compute shader threads on Gen9+."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104005
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>

i965: Program MEDIA_VFE_STATE in a more readable fashion.

This patch is purely for readability improvements when programming
the MEDIA_VFE_STATE.

Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

cso: add point rasterization sanity check assertion

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium/u_blitter: replace tabs with spaces

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

xlib: call _mesa_warning() instead of fprintf()

We use _mesa_warning() everywhere else in this code.  Change requested
by Rick Irons of Mathworks.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

gallium/util: don't pass a pipe_resource to util_resource_is_array_texture()

No need to pass a pipe_resource when we can just pass the target.
This makes the function potentially more usable.  Rename it too.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/aux: include nr_samples in util_resource_size() computation

This function is only used in two places:
1. VMware driver, but only for HUD reporting
2. st/nine state tracker, used for texture memory accounting

Fixes: a69efa9482d ("util: add new util_resource_size() function in
u_resource.[ch]")

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>