mesa.git
8 years agomesa: fix build error
Timothy Arceri [Tue, 5 Jul 2016 08:40:30 +0000 (18:40 +1000)]
mesa: fix build error

Fix build error cased by 6a524c76f5.

8 years agomesa: faster validation of sampler unit mapping for SSO
Gregory Hainaut [Fri, 24 Jun 2016 08:07:02 +0000 (10:07 +0200)]
mesa: faster validation of sampler unit mapping for SSO

Code was inspired from _mesa_update_shader_textures_used

However unlike _mesa_update_shader_textures_used that only check for a single
stage, it will check all stages.

It avoids to loop on all uniforms, only active samplers are checked.

For my use case: high FS frequency switches with few samplers.
Perf event (relative to nouveau_dri.so) goes from 5.01% to 1.68% for
the _mesa_sampler_uniforms_pipeline_are_valid function.

Signed-off-by: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
8 years agoRevert "st/glsl_to_tgsi: don't increase immediate index by 1."
Dave Airlie [Tue, 5 Jul 2016 00:22:21 +0000 (10:22 +1000)]
Revert "st/glsl_to_tgsi: don't increase immediate index by 1."

This reverts commit 27d456cc87a01998c6fe1dbf45937e2ca6128495.

DOH, what seems right and what is right with fp64 are always
two different things.

This regressed:
spec@arb_gpu_shader_fp64@shader_storage@layout-std140-fp64-mixed-shader
on radeonsi

Reported-by: Michel Dänzer <michel@daenzer.net>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agonvc0/ir: rename NVE4_SU_INFO_XXX to NVC0_SU_INFO_XXX
Samuel Pitoiset [Mon, 4 Jul 2016 22:20:00 +0000 (00:20 +0200)]
nvc0/ir: rename NVE4_SU_INFO_XXX to NVC0_SU_INFO_XXX

While we are at it, fix a typo inside the comment which describes
what those constants are for.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonvc0/ir: reset the base offset for indirect images accesses
Samuel Pitoiset [Mon, 4 Jul 2016 22:08:03 +0000 (00:08 +0200)]
nvc0/ir: reset the base offset for indirect images accesses

In presence of an indirect image access, the base offset should be
zeroed because the stride will be computed twice. This is a pretty
rare situation but it can happen when tex.r > 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
8 years agogm107/ir: fix sign bit emission for FADD32I
Samuel Pitoiset [Mon, 4 Jul 2016 11:12:20 +0000 (13:12 +0200)]
gm107/ir: fix sign bit emission for FADD32I

When emitting OP_SUB, the sign bit for FADD and FADD32I is not
at the same position. It's at position 45 for FADD but 51 for FADD32I.

This fixes the following piglit test:
tests/spec/arb_fragment_program/fdo30337b.shader_test

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
8 years agovc4: Regularize instruction emit macros
Eric Anholt [Sun, 26 Jun 2016 02:49:07 +0000 (19:49 -0700)]
vc4: Regularize instruction emit macros

ALU0 didn't have the _dest variant, and ALU2 didn't unset the def the way
ALU1 did.  This should make the ALU[012] macros much clearer, by moving
most of their contents to vc4_qir.c

8 years agovc4: Enable dead CF elimination.
Eric Anholt [Sun, 26 Jun 2016 01:45:28 +0000 (18:45 -0700)]
vc4: Enable dead CF elimination.

Now that we're about to start generating control flow in our NIR, we want
this in place.  It optimizes things frequently in the CS, when the GL VS
has control flow that doesn't affect the vertex position.

8 years agovc4: Optimize out redundant SF updates.
Eric Anholt [Sat, 4 Jun 2016 00:09:14 +0000 (17:09 -0700)]
vc4: Optimize out redundant SF updates.

Tiny change on shader-db currently, but it will be important when we start
emitting a lot of SFs from the same variable as part of control flow
support.

total instructions in shared programs: 89463 -> 89430 (-0.04%)
instructions in affected programs:     1522 -> 1489 (-2.17%)
total estimated cycles in shared programs: 250060 -> 250015 (-0.02%)
estimated cycles in affected programs:     8568 -> 8523 (-0.53%)

8 years agovc4: Move SF removal to a separate peephole pass.
Eric Anholt [Fri, 3 Jun 2016 21:36:04 +0000 (14:36 -0700)]
vc4: Move SF removal to a separate peephole pass.

The DCE pass is going to change significantly to handle control flow,
while we don't really need to change it for the SF handling.  We also need
to add some more SF peephole optimization for SF updates generated by
control flow support.

No change on shader-db.

8 years agovc4: DCE instructions with a NULL destination.
Eric Anholt [Fri, 3 Jun 2016 22:06:52 +0000 (15:06 -0700)]
vc4: DCE instructions with a NULL destination.

I'm going to add an optimization for redundant SF update removal, which
will just remove the SF and leave us (in many cases) with an instruction
with a NULL destination and no side effects.  Rather than teaching that
pass whether the whole instruction can be removed, leave that
responsibility to this pass.

8 years agovc4: Mark texturing setup instructions as having side effects.
Eric Anholt [Fri, 3 Jun 2016 22:04:57 +0000 (15:04 -0700)]
vc4: Mark texturing setup instructions as having side effects.

We need to not DCE them even though they don't have a destination in QIR.
We also shouldn't relocate them in vc4_opt_vpm.  Neither of these things
happen, but I'm about to make DCE consider instructions with a NULL
destination.

8 years agovc4: Fix a pasteo in scheduling condition flag usage.
Eric Anholt [Sat, 2 Jul 2016 22:08:27 +0000 (15:08 -0700)]
vc4: Fix a pasteo in scheduling condition flag usage.

Noticed by code inspection.  This hasn't been too big of a deal, because
our cond usages all start out as adder ops, either MOVs or the FTOI for Z
writes.  MOVs *can* get converted to mul ops during scheduling, but
apparently we hadn't hit this.

8 years agovc4: Drop the dead QIR_PACK() macro.
Eric Anholt [Sun, 26 Jun 2016 02:39:05 +0000 (19:39 -0700)]
vc4: Drop the dead QIR_PACK() macro.

This isn't used since we switched to using the dst.pack field instead of
custom instructions.

8 years agoradeonsi: do compilation from si_create_shader_selector asynchronously
Marek Olšák [Sat, 11 Jun 2016 17:57:40 +0000 (19:57 +0200)]
radeonsi: do compilation from si_create_shader_selector asynchronously

Main shader parts and geometry shaders are compiled asynchronously
by util_queue. si_create_shader_selector doesn't wait and returns.
si_draw_vbo(si_shader_select) waits for completion.

This has the best effect when shaders are compiled at app-loading time.
It doesn't help much for shaders compiled on demand, even though
VS+PS compilation should take as much as time as the bigger one of the two.

If an app creates more shaders, at most 4 threads will be used to compile
them.

Debug output disables this for shader stats to be printed in the correct
order.

(We could go even further and build variants asynchronously too, then emit
draw calls without waiting and emit incomplete shader states, then force IB
chaining to give the compiler more time, then sync the compilation at the IB
flush and patch the IB with correct shader states. This is great for
compilation before draw calls, but there are some difficulties such as
scratch and tess states requiring the compiler output, and an on-disk shader
cache will likely be a much better and simpler solution.)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: don't lock shader cache mutex during compilation
Marek Olšák [Sat, 11 Jun 2016 17:32:53 +0000 (19:32 +0200)]
radeonsi: don't lock shader cache mutex during compilation

to allow multiple shaders to be compiled simultaneously.

ALso, shader-db can again use all 4 cores.

v2: Remove the pipe_mutex_unlock call in the error path.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
8 years agoradeonsi: separate the compilation chunk of si_create_shader_selector
Marek Olšák [Sat, 11 Jun 2016 16:59:26 +0000 (18:59 +0200)]
radeonsi: separate the compilation chunk of si_create_shader_selector

The function interface is ready to be used by util_queue.
Also, si_shader_select_with_key can no longer accept si_context.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: move LLVMTargetMachineRef creation to a separate function
Marek Olšák [Sat, 11 Jun 2016 16:53:15 +0000 (18:53 +0200)]
radeonsi: move LLVMTargetMachineRef creation to a separate function

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agogallium/radeon: add and use radeon_info::max_alloc_size (v2)
Marek Olšák [Thu, 30 Jun 2016 22:17:36 +0000 (00:17 +0200)]
gallium/radeon: add and use radeon_info::max_alloc_size (v2)

v2: - squashed the patches
    - use INT_MAX
    - clamp max_const_buffer_size
    - check the DRM version in radeon

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
8 years agoradeonsi: print LLVM IRs to ddebug logs
Marek Olšák [Thu, 30 Jun 2016 22:10:15 +0000 (00:10 +0200)]
radeonsi: print LLVM IRs to ddebug logs

Getting LLVM IRs of hanging shaders have never been easier.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: enable string markers and record apitrace call numbers
Marek Olšák [Wed, 29 Jun 2016 23:15:19 +0000 (01:15 +0200)]
radeonsi: enable string markers and record apitrace call numbers

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoddebug: add an option to dump info about a specific apitrace call
Marek Olšák [Thu, 30 Jun 2016 00:11:04 +0000 (02:11 +0200)]
ddebug: add an option to dump info about a specific apitrace call

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoddebug: implement pipe_context::generate_mipmap
Marek Olšák [Wed, 29 Jun 2016 23:53:04 +0000 (01:53 +0200)]
ddebug: implement pipe_context::generate_mipmap

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoddebug: record and dump apitrace call numbers
Marek Olšák [Wed, 29 Jun 2016 22:40:01 +0000 (00:40 +0200)]
ddebug: record and dump apitrace call numbers

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoddebug: implement emit_string_marker
Marek Olšák [Wed, 29 Jun 2016 21:30:12 +0000 (23:30 +0200)]
ddebug: implement emit_string_marker

and remove some obsolete comments

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agogallium/radeon: remove unused code - radeon_llvm_util.*
Marek Olšák [Thu, 30 Jun 2016 18:01:26 +0000 (20:01 +0200)]
gallium/radeon: remove unused code - radeon_llvm_util.*

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: keep using v_rcp_f32 for division in future LLVM (v2)
Marek Olšák [Wed, 22 Jun 2016 20:24:52 +0000 (22:24 +0200)]
radeonsi: keep using v_rcp_f32 for division in future LLVM (v2)

This will be needed after some LLVM changes that haven't landed yet.

v2: - use LLVMIsConstant to fix an LLVM assertion failure.
      LLVMSetMetadata doesn't work with constants.
    - don't set float metadata as string

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: remove an obsolete comment
Marek Olšák [Thu, 30 Jun 2016 22:58:19 +0000 (00:58 +0200)]
radeonsi: remove an obsolete comment

It's not true.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: don't interpolate colors if flatshading is enabled
Marek Olšák [Thu, 30 Jun 2016 11:28:49 +0000 (13:28 +0200)]
radeonsi: don't interpolate colors if flatshading is enabled

use v_interp_mov for those

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: enable the barycentric optimization in all cases
Marek Olšák [Thu, 30 Jun 2016 00:16:16 +0000 (02:16 +0200)]
radeonsi: enable the barycentric optimization in all cases

Handle the bc_optimize SGPR bit if both CENTER and CENTROID are enabled.
This should increase the PS launch rate for big primitives with MSAA.
Based on discussion with SPI guys.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: compute only one set of interpolation (i,j) when MSAA is disabled
Marek Olšák [Thu, 30 Jun 2016 08:57:34 +0000 (10:57 +0200)]
radeonsi: compute only one set of interpolation (i,j) when MSAA is disabled

This should increase the PS launch rate for shaders using at least 2 pairs
of perspective (i,j) and same for linear.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: split ps.prolog.force_persample_interp into persp and linear bits
Marek Olšák [Thu, 30 Jun 2016 08:50:26 +0000 (10:50 +0200)]
radeonsi: split ps.prolog.force_persample_interp into persp and linear bits

This reduces the number of v_mov's in the prolog.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: don't dump the shader key for non-monolithic shaders early
Marek Olšák [Thu, 30 Jun 2016 09:10:21 +0000 (11:10 +0200)]
radeonsi: don't dump the shader key for non-monolithic shaders early

It's always zero.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agor600g: Add double precision FMA ops
Jan Vesely [Sat, 2 Jul 2016 20:14:54 +0000 (16:14 -0400)]
r600g: Add double precision FMA ops

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96782
Fixes: 54c4d525da7c7fc1e103d7a3e6db015abb132d5d ("r600g: Enable FMA on chips that support it")
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Tested-by: James Harvey <lothmordor@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
8 years agor600: fix duplicate 'const' declaration
Francesco Ansanelli [Sun, 3 Jul 2016 19:03:04 +0000 (21:03 +0200)]
r600: fix duplicate 'const' declaration

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoi965/urb: Allow blorp to record current settings
Topi Pohjolainen [Mon, 23 May 2016 06:22:01 +0000 (09:22 +0300)]
i965/urb: Allow blorp to record current settings

This makes it possible to skip urb re-configuration if the
subsequent renders agree with the settings.

Also allows blorp to allocate the maximun amount of vs entries
available. Core upload logic already knows how to calculate this.
Helps one synthetic benchmark.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/blorp/gen7+: Do not trigger push constant space reconfig
Topi Pohjolainen [Wed, 18 May 2016 19:07:05 +0000 (22:07 +0300)]
i965/blorp/gen7+: Do not trigger push constant space reconfig

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965/blorp/gen7+: Stop trashing push constant allocation
Topi Pohjolainen [Fri, 20 May 2016 08:15:35 +0000 (11:15 +0300)]
i965/blorp/gen7+: Stop trashing push constant allocation

Packet 3DSTATE_CONSTANT_PS is still emitted explicitly as ps stage
itself is enabled and hardware may try to prefetch constants from
the buffer. From the BSpec: 3D Pipeline - Windower -
3DSTATE_PUSH_CONSTANT_ALLOC_PS

  "Specifies the size of the PS constant buffer. This value will
   determine the amount of data the command stream can pre-fetch
   before the buffer is full."

This is not possible on gen6. From the BSpec about 3DSTATE_CONSTANT_PS:

"This packet must be followed by WM_STATE."

Binding table emissions for stages other than PS can be now dropped,
they were only needed for the 3DSTATE_CONSTANT_XS to be effective:

From the BSpec:

  "The 3DSTATE_CONSTANT_* command is not committed to the shader unit
   until the corresponding (same shader) 3DSTATE_BINDING_TABLE_POINTER_*
   command is parsed."

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965/blorp: Remove support for push constants
Topi Pohjolainen [Wed, 18 May 2016 19:01:17 +0000 (22:01 +0300)]
i965/blorp: Remove support for push constants

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965/blorp: Use flat inputs instead of uniforms
Topi Pohjolainen [Sun, 15 May 2016 04:43:39 +0000 (07:43 +0300)]
i965/blorp: Use flat inputs instead of uniforms

v2 (Jason): Use LOAD_INPUT() macro

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965/blorp: Fix the size requirement for vertex elements
Topi Pohjolainen [Wed, 18 May 2016 04:30:00 +0000 (07:30 +0300)]
i965/blorp: Fix the size requirement for vertex elements

v2: Rebased as this is needed before flat inputs are enabled

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/blorp: Load tranformation coordinates as vec4
Topi Pohjolainen [Tue, 17 May 2016 13:41:23 +0000 (16:41 +0300)]
i965/blorp: Load tranformation coordinates as vec4

In preparation for loading as flat vertex input.

v2: Use LOAD_INPUT() macro

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965/blorp: Rename LOAD_UNIFORM to LOAD_INPUT
Topi Pohjolainen [Sun, 3 Jul 2016 07:19:25 +0000 (10:19 +0300)]
i965/blorp: Rename LOAD_UNIFORM to LOAD_INPUT

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965/blorp: Organize pixel kill and blend/scaled inputs into vec4s
Topi Pohjolainen [Tue, 17 May 2016 06:27:49 +0000 (09:27 +0300)]
i965/blorp: Organize pixel kill and blend/scaled inputs into vec4s

In addition, as these are never used in parallel, add a few
assertions.

v2 (Jason): Skip some complexity by putting them into a union but
            pad rectangle grid into a vec4 instead. Also keep the
            LOAD_UNIFORM macro.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoanv/wsi: create swapchain images using specified image usage
Lionel Landwerlin [Mon, 4 Jul 2016 17:06:58 +0000 (18:06 +0100)]
anv/wsi: create swapchain images using specified image usage

The image usage specified by the caller of vkCreateSwapchainKHR should be
passed onto the internal image creation. Otherwise the driver might later
crash when the user tries to use the image as a combined sampler even though
the creation was explicitly created with VK_IMAGE_USAGE_TRANSFER_SRC_BIT.

Leaving the previous VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT as this might be
expected even if the swapchain is created without any flag.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96791
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
8 years agoradeon/uvd: fix overflow error while calculating bit stream buffer size
Indrajit Das [Fri, 27 May 2016 12:57:15 +0000 (18:27 +0530)]
radeon/uvd: fix overflow error while calculating bit stream buffer size

Reviewed-by: Christian König <christian.koenig@amd.com>
8 years agoi965/blorp: Prepare for more than two vertex attributes
Topi Pohjolainen [Wed, 18 May 2016 16:25:33 +0000 (19:25 +0300)]
i965/blorp: Prepare for more than two vertex attributes

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965/blorp: Tell vertex fetcher about flat inputs
Topi Pohjolainen [Sun, 15 May 2016 08:10:05 +0000 (11:10 +0300)]
i965/blorp: Tell vertex fetcher about flat inputs

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965/blorp: Add support for flat input buffer
Topi Pohjolainen [Sun, 15 May 2016 05:33:16 +0000 (08:33 +0300)]
i965/blorp: Add support for flat input buffer

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965/blorp: Store input read mask
Topi Pohjolainen [Wed, 1 Jun 2016 09:27:56 +0000 (12:27 +0300)]
i965/blorp: Store input read mask

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965/blorp: Rename push constants to inputs
Topi Pohjolainen [Tue, 17 May 2016 12:44:39 +0000 (15:44 +0300)]
i965/blorp: Rename push constants to inputs

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965/blorp: Use core vertex buffer state setup
Topi Pohjolainen [Sun, 15 May 2016 06:48:58 +0000 (09:48 +0300)]
i965/blorp: Use core vertex buffer state setup

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965/blorp: Split vertex data and element setup
Topi Pohjolainen [Thu, 23 Jun 2016 06:35:57 +0000 (09:35 +0300)]
i965/blorp: Split vertex data and element setup

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965: Unify vertex buffer setup
Topi Pohjolainen [Sun, 15 May 2016 06:42:39 +0000 (09:42 +0300)]
i965: Unify vertex buffer setup

On gen >= 8 one doesn't provide ending address but number of bytes
available. This is relative to the given offset.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoi965/draw: Expose vertex buffer state setup
Topi Pohjolainen [Sun, 15 May 2016 05:48:13 +0000 (08:48 +0300)]
i965/draw: Expose vertex buffer state setup

Also change the interface to use start and end offsets.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agofreedreno: fix crash on smaller gpus and higher resolutions
Rob Clark [Sun, 3 Jul 2016 15:16:28 +0000 (11:16 -0400)]
freedreno: fix crash on smaller gpus and higher resolutions

Devices with smaller GMEM size need more tiles.  On db410c at 2048x1152,
glmark2 shadow needed ~330 tiles for fullscreen.  Lets bump it up to
512.  (Maybe with MRT you could end up needing more, but at that point
things are probably going to be painfully slow.)

Signed-off-by: Rob Clark <robdclark@gmail.com>
8 years agoi965: don't drop const initializers in vector splitting
Rob Clark [Sat, 25 Jun 2016 00:03:37 +0000 (20:03 -0400)]
i965: don't drop const initializers in vector splitting

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoglsl: add driconf to zero-init unintialized vars
Rob Clark [Fri, 24 Jun 2016 18:28:51 +0000 (14:28 -0400)]
glsl: add driconf to zero-init unintialized vars

Some games are sloppy.. perhaps because it is defined behavior for DX or
perhaps because nv blob driver defaults things to zero.

So add driconf param to force uninitialized variables to default to zero.

This issue was observed with rust, from steam store.  But has surfaced
elsewhere in the past.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agofreedreno/ir3: support glsl linking for cmdline compiler
Rob Clark [Fri, 24 Jun 2016 19:17:27 +0000 (15:17 -0400)]
freedreno/ir3: support glsl linking for cmdline compiler

For .vert/.frag, now multiple can be specified on the cmdline for
purposes of linking, and the last one specified is the one that is
fed into the ir3 backend (and dumped along the way if --verbose is
specified)

Without this, varyings in frag shaders would appear as undefined.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agoglsl/standalone: initialize MaxUserAssignableUniformLocations
Rob Clark [Fri, 24 Jun 2016 19:11:02 +0000 (15:11 -0400)]
glsl/standalone: initialize MaxUserAssignableUniformLocations

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno: update valid_buffer_range for SO buffers
Rob Clark [Fri, 1 Jul 2016 02:52:23 +0000 (22:52 -0400)]
freedreno: update valid_buffer_range for SO buffers

Signed-off-by: Rob Clark <robdclark@gmail.com>
8 years agofreedreno/ir3: support non-user_buffer consts
Rob Clark [Wed, 22 Jun 2016 18:45:25 +0000 (14:45 -0400)]
freedreno/ir3: support non-user_buffer consts

Signed-off-by: Rob Clark <robdclark@gmail.com>
8 years agofreedreno/a2xx: move setup/restore cmds into binning pass
Rob Clark [Fri, 20 May 2016 20:00:26 +0000 (16:00 -0400)]
freedreno/a2xx: move setup/restore cmds into binning pass

Rather than doing a separate submit at context create, move these cmds
to before first tile, as is done on a3xx/a4xx.  Otherwise state can
be overwritten by other contexts.

Signed-off-by: Rob Clark <robdclark@gmail.com>
8 years agofreedreno: pass index buffer as a pipe_resource
Rob Clark [Fri, 20 May 2016 17:41:44 +0000 (13:41 -0400)]
freedreno: pass index buffer as a pipe_resource

This will be useful in a following patch.

Signed-off-by: Rob Clark <robdclark@gmail.com>
8 years agofreedreno: switch emit_const_bo() to take prsc's
Rob Clark [Fri, 20 May 2016 16:54:29 +0000 (12:54 -0400)]
freedreno: switch emit_const_bo() to take prsc's

We can push the unwrap of pipe_resource down.

Signed-off-by: Rob Clark <robdclark@gmail.com>
8 years agonv30: Fix "array subscript is below array bounds" compiler warning
Hans de Goede [Wed, 29 Jun 2016 12:32:19 +0000 (14:32 +0200)]
nv30: Fix "array subscript is below array bounds" compiler warning

gcc6 does not like the trick where we point to one entry before the
array start and then start a while with a pre-increment.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonouveau: Fix a couple of "foo may be used uninitialized' compiler warnings
Hans de Goede [Wed, 29 Jun 2016 12:23:23 +0000 (14:23 +0200)]
nouveau: Fix a couple of "foo may be used uninitialized' compiler warnings

These are all new false positives with gcc6.

In nouveau_compiler.c: gcc6 no longer assumes that passing a pointer
to a variable into a function initialises that variable.

In nv50_ir_from_tgsi.cpp op and mode are not set if there are 0
enabled dst channels, this never happens, but gcc cannot know this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonouveau: Fix gcc6 / c++11 auto_ptr deprecation compiler warnings
Hans de Goede [Wed, 29 Jun 2016 11:09:11 +0000 (13:09 +0200)]
nouveau: Fix gcc6 / c++11 auto_ptr deprecation compiler warnings

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
8 years agonouveau: Add support for SV_WORK_DIM
Hans de Goede [Mon, 25 Apr 2016 09:42:12 +0000 (11:42 +0200)]
nouveau: Add support for SV_WORK_DIM

Add support for SV_WORK_DIM for nvc0 and nve4.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
8 years agonvc0: Make NVC0_CB_AUX_GRID_INFO take an index argument
Hans de Goede [Wed, 29 Jun 2016 09:23:45 +0000 (11:23 +0200)]
nvc0: Make NVC0_CB_AUX_GRID_INFO take an index argument

This brings it inline with the other macros like NVC0_CB_AUX_UBO_INFO
and NVC0_CB_AUX_TEX_INFO.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
8 years agoclover: Pass work_dim parameter of clEnqueueNDRangeKernel() to driver
Hans de Goede [Fri, 22 Apr 2016 12:47:05 +0000 (14:47 +0200)]
clover: Pass work_dim parameter of clEnqueueNDRangeKernel() to driver

In order to implement get_work_dim() the driver may need to know the
clEnqueueNDRangeKernel() work_dim parameter, so pass it to the driver.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
8 years agotgsi: Add WORK_DIM System Value
Hans de Goede [Fri, 22 Apr 2016 12:26:50 +0000 (14:26 +0200)]
tgsi: Add WORK_DIM System Value

Add a new WORK_DIM SV type, this is will return the grid dimensions
(1-4) for compute (opencl) kernels.

This is necessary to implement the opencl get_work_dim() function.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
8 years agomesa/main: fix error checking logic on CopyImageSubData
Alejandro Piñeiro [Thu, 30 Jun 2016 12:41:01 +0000 (14:41 +0200)]
mesa/main: fix error checking logic on CopyImageSubData

For the case (both src or dst) where we had a texobject, but the
texobject target was not the same that the method target, this spec
paragraph was appplied:

 /* Section 18.3.2 (Copying Between Images) of the OpenGL 4.5 Core
  * Profile spec says:
  *
  *     "An INVALID_VALUE error is generated if either name does not
  *     correspond to a valid renderbuffer or texture object according
  *     to the corresponding target parameter."
  */

But for that case, the correct spec paragraph should be:
 /* Section 18.3.2 (Copying Between Images) of the OpenGL 4.5 Core
  * Profile spec says:
  *
  *     "An INVALID_ENUM error is generated if either target is
  *      not RENDERBUFFER or a valid non-proxy texture target;
  *      is TEXTURE_BUFFER or one of the cubemap face selectors
  *      described in table 8.18; or if the target does not
  *      match the type of the object."
  */

specifically the last sentence: "or if the target does not match the
type of the object".

This patch fixes the error returned (s/INVALID/ENUM) for that case,
and moves up the INVALID_VALUE spec paragraph, as that case (invalid
texture object) was handled before.

Fixes:
GL44-CTS.copy_image.target_miss_match

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agost/glsl_to_tgsi: don't increase immediate index by 1.
Dave Airlie [Mon, 6 Jun 2016 23:39:55 +0000 (09:39 +1000)]
st/glsl_to_tgsi: don't increase immediate index by 1.

Immediates are stored into a separate table, and are
consolidated, so if we get an immediate we don't need
to offset it as the index it has is correct.

Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agost/mesa: get max supported number of image samples from driver
Ilia Mirkin [Wed, 29 Jun 2016 04:11:57 +0000 (00:11 -0400)]
st/mesa: get max supported number of image samples from driver

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agonvc0: fix up image support for allowing multiple samples
Ilia Mirkin [Wed, 29 Jun 2016 04:08:01 +0000 (00:08 -0400)]
nvc0: fix up image support for allowing multiple samples

Basically we just have to scale up the coordinates and then add the
relevant sample offset. The code to handle this was already largely
present from Christoph's earlier attempts to pipe images through back in
the dark ages, this just hooks it all up.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agost/mesa: check the texture image level in st_texture_match_image
Nicolai Hähnle [Fri, 24 Jun 2016 15:54:51 +0000 (17:54 +0200)]
st/mesa: check the texture image level in st_texture_match_image

Otherwise, 1x1 images of arbitrarily high level are accepted.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96639#add_comment
Cc: 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agost/mesa: an incomplete texture may have a zero-size first image
Nicolai Hähnle [Fri, 24 Jun 2016 14:35:36 +0000 (16:35 +0200)]
st/mesa: an incomplete texture may have a zero-size first image

Fixes a regression introduced by commit 42624ea83 which triggered
an assertion in
dEQP-GLES2.functional.texture.completeness.cube.not_positive_level_0

While stImage must have a non-zero size as verified by the caller, we also
look at the size of the base image in an attempt to make a better guess at
the level0 size (this is important when the base image size is odd). However,
the base image may have a zero size even when it exists.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96629
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agost/vdpau: use bicubic filter for scaling(v6.1)
Nayan Deshmukh [Wed, 29 Jun 2016 13:24:01 +0000 (18:54 +0530)]
st/vdpau: use bicubic filter for scaling(v6.1)

use bicubic filtering as high quality scaling L1.

v2: fix a typo and add a newline to code
v3: -render the unscaled image on a temporary surface (Christian)
    -apply noise reduction and sharpness filter on
     unscaled surface
    -render the final scaled surface using bicubic
     interpolation
v4: support high quality scaling
v5: set dst_area and dst_clip in bicubic filter
v6: set buffer layer before setting dst_area
v6.1: add PIPE_BIND_LINEAR when creating resource

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
8 years agovl: add a bicubic interpolation filter(v5)
Nayan Deshmukh [Wed, 29 Jun 2016 13:24:00 +0000 (18:54 +0530)]
vl: add a bicubic interpolation filter(v5)

This is a shader based bicubic interpolater which uses cubic
Hermite spline algorithm.

v2: set dst_area and dst_clip during scaling (Christian)
v3: clear the render target before rendering
v4: intialize offsets while initializing shaders
    use a constant buffer to send dst_size to frag shader
    small changes to reduce calculation in shader
v5: send half pixel offset instead of sending dst_size

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
8 years agomesa/st: Use 'struct nir_shader' instead of 'nir_shader'.
Vinson Lee [Thu, 30 Jun 2016 03:15:03 +0000 (20:15 -0700)]
mesa/st: Use 'struct nir_shader' instead of 'nir_shader'.

Fix this build error with GCC 4.4.

  CC     state_tracker/st_nir_lower_builtin.lo
In file included from state_tracker/st_nir_lower_builtin.c:61:
state_tracker/st_nir.h:34: error: redefinition of typedef ‘nir_shader’
../../src/compiler/nir/nir.h:1830: note: previous declaration of ‘nir_shader’ was here

Suggested-by: Rob Clark <robdclark@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96235
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
8 years agodocs: update MESA_DEBUG envvar documentation.
Alejandro Piñeiro [Mon, 27 Jun 2016 08:00:58 +0000 (10:00 +0200)]
docs: update MESA_DEBUG envvar documentation.

silent, flush, incomplete_tex and incomplete_fbo flags were not
documented (see src/mesa/main.debug.c for more info).

FP is not checked anymore.

v2 (Brian Paul):
 * MESA_DEBUG accepts a comma-separated list of parameters.
 * Clarify how MESA_DEBUG behaves with mesa debug and release builds.
 * Updated wording.

v3: Better wording for one paragraph (Brian Paul)

Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agoi965: intel_texture_barrier reimplemented
Alejandro Piñeiro [Tue, 28 Jun 2016 11:16:33 +0000 (13:16 +0200)]
i965: intel_texture_barrier reimplemented

Fixes:
GL44-CTS.texture_barrier_ARB.same-texel-rw-multipass

On Haswell, Broadwell and Skylake (note that in order to execute that
test, it is needed to override GL and GLSL versions).

On gen6 this test was already working without this change. It keeps
working after it.

This commit replaces the call to brw_emit_mi_flush for gen6+ with two
calls to brw_emit_pipe_control_flush:

 * The first one with RENDER_TARGET_FLUSH and CS_STALL set to initiate
   a render cache flush after any concurrent rendering completes and
   cause the CS to stop parsing commands until the render cache
   becomes coherent with memory.

 * The second one have TEXTURE_CACHE_INVALIDATE set (and no CS stall)
   to clean up any stale data from the sampler caches before rendering
   continues.

Didn't touch gen4-5, basically because I don't have a way to test
them.

More info on commits:
0aa4f99f562a05880a779707cbcd46be459863bf
72473658c51d5e074ce219c1e6385a4cce29f467

Thanks to Curro to help to tracking this down, as the root case was a
hw race condition.

v2: use two calls to pipe_control_flush instead of a combination of
    gen7_emit_cs_stall_flush and brw_emit_mi_flush calls (Curro)
v3: no need to const cache invalidation (Curro)

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agonv30: go back to not using viewport validate function for swtnl
Ilia Mirkin [Fri, 1 Jul 2016 04:59:58 +0000 (00:59 -0400)]
nv30: go back to not using viewport validate function for swtnl

The output of draw requires a null viewport transform, which the regular
code is ill-equiped to do. Reinstate the original settings in the render
path, and add setting of the viewport clip polygon based on fb
width/height (as that is all taken care of by draw).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv30: fix viewport clipping settings to be based on viewport, not rt
Ilia Mirkin [Wed, 22 Jun 2016 02:51:36 +0000 (22:51 -0400)]
nv30: fix viewport clipping settings to be based on viewport, not rt

This fixes a ton of "*clip*" dEQP GLES2 tests, as well as
triangle-guardband-viewport in piglit.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agogallium/util: check for window cliprects in util_can_blit_via_copy_region()
Brian Paul [Fri, 1 Jul 2016 00:15:19 +0000 (18:15 -0600)]
gallium/util: check for window cliprects in util_can_blit_via_copy_region()

We can't blit with resource_copy_region() if there are window clip rects.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
8 years agogallium: Force blend color to 16-byte alignment
Chuck Atkins [Wed, 29 Jun 2016 02:32:02 +0000 (22:32 -0400)]
gallium: Force blend color to 16-byte alignment

This aligns the 4-element color float array to 16 byte boundaries.  This
should allow compiler vectorizers to generate better optimizations.
Also fixes broken vectorization generated by Intel compiler.

v2: Fixed indentation and added a lengthy comment explaining the
    reason for the alignment.

Cc: <mesa-stable@lists.freedesktop.org>
Reported-by: Tim Rowley <timothy.o.rowley@intel.com>
Tested-by: Tim Rowley <timothy.o.rowley@intel.com>
Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
8 years agoswr: Refactor checks for compiler feature flags
Chuck Atkins [Tue, 28 Jun 2016 19:50:47 +0000 (15:50 -0400)]
swr: Refactor checks for compiler feature flags

Encapsulate the test for which flags are needed to get a compiler to
support certain features.  Along with this, give various options to try
for AVX and AVX2 support.  Ideally we want to use specific instruction
set feature flags, like -mavx2 for instance instead of -march=haswell,
but the flags required for certain compilers are different.  This
allows, for AVX2 for instance, GCC to use -mavx2 -mfma -mbmi2 -mf16c
while the Intel compiler which doesn't support those flags can fall
back to using -march=core-avx2.

This addresses a bug where the Intel compiler will silently ignore the
AVX2 instruction feature flags and then potentially fail to build.

v2: Pass preprocessor-check argument as true-state instead of
    false-state for clarity.
v3: Reduce AVX2 define test to just __AVX2__.  Additional defines suchas
    __FMA__, __BMI2__, and __F16C__ appear to be inconsistently defined
    w.r.t thier availability.
v4: Fix C++11 flags being added globally and add more logic to
    swr_require_cxx_feature_flags

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Tested-by: Tim Rowley <timothy.o.rowley@Intel.com>
Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
8 years agost/wgl: make own_mutex() non-static
Brian Paul [Wed, 11 May 2016 15:20:04 +0000 (09:20 -0600)]
st/wgl: make own_mutex() non-static

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
8 years agoglsl: atomic counters are different than their uniforms
Andres Gomez [Thu, 30 Jun 2016 13:37:25 +0000 (16:37 +0300)]
glsl: atomic counters are different than their uniforms

The linker deals with atomic counters in terms of uniforms but the
data structure are called after the atomic counters.

Renamed the data structures used in the linker for disambiguation.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
8 years agoglsl: count atomic counters correctly
Andres Gomez [Thu, 30 Jun 2016 13:37:11 +0000 (16:37 +0300)]
glsl: count atomic counters correctly

Currently the linker uses the uniform count for the total number of
atomic counters. However uniforms don't include the innermost array
dimension in their count, but atomic counters are expected to include
them.

Although the spec doesn't directly state this, it's clear how offsets
will be assigned for arrays.

From OpenGL 4.2 (Core Profile), page 98:

  "  * Arrays of type atomic_uint are stored in memory by element
       order, with array element member zero at the lowest offset. The
       difference in offsets between each pair of elements in the
       array in basic machine units is referred to as the array
       stride, and is constant across the entire array. The stride can
       be queried by calling GetIntegerv with a pname of
       ATOMIC_COUNTER_- ARRAY_STRIDE after a program is linked."

From that it is clear how arrays of atomic counters will interact with
GL_MAX_ATOMIC_COUNTER_BUFFER_SIZE.

For other kinds of uniforms it's also clear that each entry in an
array counts against the relevant limits.

Hence, although inferred, this is the expected behavior.

Fixes GL44-CTS.arrays_of_arrays_gl.AtomicDeclaration

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
8 years agosvga: use SVGA3D_vgpu10_BufferCopy() for buffer copies
Brian Paul [Tue, 28 Jun 2016 23:15:57 +0000 (17:15 -0600)]
svga: use SVGA3D_vgpu10_BufferCopy() for buffer copies

So that we do copies host-side rather than in the guest with map/memcpy.

Tested with piglit arb_copy_buffer-subdata-sync test and new
arb_copy_buffer-intra-buffer-copy test.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
8 years agosvga: add SVGA3D_vgpu10_BufferCopy()
Brian Paul [Thu, 23 Jun 2016 02:38:06 +0000 (20:38 -0600)]
svga: add SVGA3D_vgpu10_BufferCopy()

Acked-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
8 years agosvga: flush buffers when mapping for reading
Brian Paul [Thu, 30 Jun 2016 19:27:57 +0000 (13:27 -0600)]
svga: flush buffers when mapping for reading

With host-side buffer copies (via SVGA3D_vgpu10_BufferCopy()) we have
to make sure any pending map-write operations are completed before reading
if the buffer is dirty.  Otherwise the ReadbackSubResource operation could
get stale data from the host buffer.

This allows the piglit arb_copy_buffer-subdata-sync test to pass when
we start using the SVGA3D_vgpu10_BufferCopy command.

v2: check the sbuf->dirty flag in the outer conditional, per Charmaine.

Acked-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
8 years agosvga: enable ARB_copy_image extension in the driver
Neha Bhende [Thu, 23 Jun 2016 17:21:31 +0000 (11:21 -0600)]
svga: enable ARB_copy_image extension in the driver

Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
8 years agosvga: try blitting with copy region in more cases
Brian Paul [Tue, 28 Jun 2016 23:13:57 +0000 (17:13 -0600)]
svga: try blitting with copy region in more cases

We previously could do blits with util_resource_copy_region() when doing
'loose' format checking.  Also do blits with util_resource_copy_region()
when the blit src/dst formats (not the underlying resources) exactly
match.  Needed for GL_ARB_copy_image.

Acked-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
8 years agosvga: use copy_region_vgpu10() for region copies when possible
Brian Paul [Thu, 23 Jun 2016 17:57:08 +0000 (11:57 -0600)]
svga: use copy_region_vgpu10() for region copies when possible

v2: remove extra svga_define_texture_level() call, per Charmaine.

Acked-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
8 years agosvga: use vgpu10 CopyRegion command when possible
Neha Bhende [Tue, 28 Jun 2016 23:20:43 +0000 (17:20 -0600)]
svga: use vgpu10 CopyRegion command when possible

Do texture->texture copies host-side with this command when possible.
Use the previous software fallback otherwise.

Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
8 years agosvga: set render target flag for snorm surfaces
Brian Paul [Mon, 27 Jun 2016 17:18:10 +0000 (11:18 -0600)]
svga: set render target flag for snorm surfaces

We don't normally support rendering to SNORM surfaces, but with
GL_ARB_copy_image we can copy to them if we treat them as typeless
and use a UNORM surface view.

Acked-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
8 years agosvga: add new svga_format_is_uncompressed_snorm() helper
Brian Paul [Mon, 27 Jun 2016 17:17:45 +0000 (11:17 -0600)]
svga: add new svga_format_is_uncompressed_snorm() helper

Acked-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>