Vasily Khoruzhick [Wed, 11 Sep 2019 03:06:15 +0000 (20:06 -0700)]
lima: set .out_sync field of req in lima_submit_start()
Looks like .out_sync wasn't set in lima_submit_start(), as result
submit completion fence was never signalled.
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Anuj Phogat [Fri, 16 Aug 2019 19:45:52 +0000 (12:45 -0700)]
intel: Add few Ice Lake brand strings
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Mon, 9 Sep 2019 14:23:22 +0000 (07:23 -0700)]
gallium: Fix util_format_get_depth_only
This is a pipe format, not a boolean.
Fixes: 5849e0612cc ("gallium/auxiliary: Add util_format_get_depth_only() helper.")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Rob Clark [Tue, 10 Sep 2019 18:28:31 +0000 (19:28 +0100)]
freedreno/a6xx: fix 3d tex layout
Fixes dEQP-GLES3.functional.texture.specification.texstorage3d.size.3d_2x2x2_2_levels
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Rob Clark [Mon, 9 Sep 2019 23:19:40 +0000 (16:19 -0700)]
freedreno/a6xx: don't tile things that are too small
If the lowest (largest) mipmap level is too small to tile, then don't
bother pretending.
Note that this requires initializing pipe->screen before
fd_resource_level_linear() is called.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Caio Marcelo de Oliveira Filho [Mon, 5 Aug 2019 23:56:42 +0000 (16:56 -0700)]
iris: Enable ARB_gl_spirv and ARB_spirv_extensions
This will also "unlock" OpenGL 4.6 for Iris!
v2: Also enable PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [v1]
Caio Marcelo de Oliveira Filho [Fri, 23 Aug 2019 13:50:11 +0000 (06:50 -0700)]
glsl/nir: Add and use a gl_nir_link() function
Perform all the NIR linking steps in order. Change iris and i965 to
use it. Suggested by Alejandro.
v2: Add gl_nir_linker_options struct.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [v1]
Caio Marcelo de Oliveira Filho [Mon, 5 Aug 2019 23:25:11 +0000 (16:25 -0700)]
gallium: Add ARB_gl_spirv support
The PIPE_CAP_GL_SPIRV capability enables ARB_gl_spirv and
ARB_spirv_extensions, and will make sure the corresponding SPIR-V
capabilities and extensions lists are initialized.
The additional PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS capability enables
the support for Variable Pointers in SPIR-V shaders. This depends on
the driver and is not mandatory for ARB_gl_spirv support.
v2: Add a PIPE_CAP for Variable Pointers. (Marek)
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [v1]
Caio Marcelo de Oliveira Filho [Thu, 22 Aug 2019 17:19:49 +0000 (10:19 -0700)]
mesa/spirv: Set a few more extensions
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Caio Marcelo de Oliveira Filho [Thu, 22 Aug 2019 18:23:51 +0000 (11:23 -0700)]
mesa/st: Don't expect prog->nir to already exist
There's no such case, if we load prog->nir from the shader cache, we
shouldn't hit this path.
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Caio Marcelo de Oliveira Filho [Thu, 22 Aug 2019 13:43:28 +0000 (06:43 -0700)]
mesa/st: Add support for SPIR-V shaders
The SPIR-V codepath uses NIR linking, so we have to preprocess after
the linking steps, which makes things slightly different than GLSL.
To make more clear when the preprocess is happening, I've ended up
inlining st_nir_get_mesa_program() into its caller.
The goal was to make both GLSL and SPIR-V to use the same preprocess
function, the exceptions are:
- SPIR-V codepath don't support NIR state slots yet;
- GLSL lowers shared memory early, so we don't do the deref lowering
for those.
For now I didn't bother to rename other functions and files (now that
many of them apply to both GLSL and SPIR-V), but we should do this in
further patches.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Caio Marcelo de Oliveira Filho [Thu, 22 Aug 2019 14:10:32 +0000 (07:10 -0700)]
mesa/st: Extract preprocessing NIR steps
Refactor to split the glsl_to_nir conversion from the preprocessing
NIR passes into separate functions, so we can use them in SPIR-V.
Unlike in GLSL, there we'll need to perform a few passes with the NIR
linker before doing the individual preprocess calls.
No behavior should change with this patch.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Caio Marcelo de Oliveira Filho [Thu, 22 Aug 2019 04:04:27 +0000 (21:04 -0700)]
mesa/st: Lookup parameters without using names
Use the new MainUniformStorageIndex field in Parameter instead. It
was added so we could match those in the SPIR-V case, where names are
optional.
v2: Use MainUniformStorageIndex for all cases.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [v1]
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Caio Marcelo de Oliveira Filho [Wed, 21 Aug 2019 19:16:29 +0000 (12:16 -0700)]
mesa/program: Associate uniform storage without using names
Use the new UniformStorageIndex field in Parameter instead. This
mechanism was added so we could match those in the SPIR-V case, where
names are optional.
v2: Use UniformStorageIndex for all cases. (Timothy)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Caio Marcelo de Oliveira Filho [Wed, 4 Sep 2019 16:28:54 +0000 (09:28 -0700)]
mesa: Fill Parameter storage indices even when not using SPIR-V
When creating Parameters, fill in the associated uniform storage
indices, like it is done with the NIR linker used for SPIR-V. This
will allow later code to not rely on names (which would never work for
SPIR-V where names are optional).
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Caio Marcelo de Oliveira Filho [Wed, 21 Aug 2019 18:08:48 +0000 (11:08 -0700)]
glsl/nir: Fill in the Parameters in NIR linker
The parameter lists were not being created nor filled since i965
doesn't use them. In Gallium they are used for uniform handling, so
add a way to fill them.
The gl_uniform_storage struct got two new fields that let us go
- from a Parameter to the matching UniformStorage and,
- from the variable to the *first* UniformStorage
without relying on names -- since they are optional for ARB_gl_spirv.
Later patches will make use of them.
v2: Do not fill parameters for i965. (Timothy)
Use uint32_t for the new attributes. (Marek)
v3: Serialize the new fields. (Timothy)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Caio Marcelo de Oliveira Filho [Wed, 4 Sep 2019 00:10:52 +0000 (17:10 -0700)]
mesa: Pack gl_program_parameter struct
The gl_register_file doesn't need 16 bits, so shorten it and use the
extra room for 'Padded' (also mark it as a single bit). This shrinks
the struct size from 32 bytes to 24 bytes.
See also
4794fbc86e3 ("mesa: reduce the size of gl_program_parameter")
that shrinked from 40 to 24 and later
7536af670b7 ("glsl: fix shader
cache for packed param list") that added `Padded`.
v2: Use just 5 bits for gl_register_file. (Timothy)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Caio Marcelo de Oliveira Filho [Wed, 21 Aug 2019 16:06:14 +0000 (09:06 -0700)]
compiler: Add glsl_contains_opaque() helper
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Caio Marcelo de Oliveira Filho [Wed, 21 Aug 2019 16:38:10 +0000 (09:38 -0700)]
mesa/st: Do not rely on name to identify special uniforms
Every uniform that have the "gl_" name also have some state slots. So
use the state_slots like we did in
57b61849310 ("i965: account for NIR
uniforms without name").
This removes the dependency on names, which are optional when using
ARB_gl_spirv.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Caio Marcelo de Oliveira Filho [Wed, 21 Aug 2019 17:04:56 +0000 (10:04 -0700)]
glsl/nir: Avoid overflow when setting max_uniform_location
Don't use the UNMAPPED_UNIFORM_LOC (-1) to set the unsigned
max_uniform_location. Those unmapped uniforms don't have to be
accounted at this point.
Fixes: 7a9e5cdfbb9 ("nir/linker: Add gl_nir_link_uniforms()")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Dylan Baker [Wed, 18 Apr 2018 20:19:20 +0000 (13:19 -0700)]
meson: don't allow glvnd on windows
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Wed, 18 Apr 2018 20:17:50 +0000 (13:17 -0700)]
meson: don't build glx or dri by default on windows
v5: - Move is windows check down to make code more robust
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Wed, 18 Apr 2018 20:17:20 +0000 (13:17 -0700)]
meson: Add a platform for windows
This mirrors the haiku build which uses a platform.
v2: - Fix some rebase problems
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Thu, 8 Feb 2018 21:10:12 +0000 (13:10 -0800)]
meson: build getopt when using msvc
v4: - Don't wrap a single file in a list to match mesa style
- Use null_dep instead of empty list
Reviewed-by: Eric Anholt <eric@anholt.net> (v3)
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Thu, 5 Apr 2018 23:12:51 +0000 (16:12 -0700)]
meson: fix dl detection on non cygwin windows
v4: - Don't run checks on Windows that will always fail
Reviewed-by: Eric Anholt <eric@anholt.net> (v3)
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Wed, 18 Apr 2018 15:33:03 +0000 (08:33 -0700)]
glapi: export glapi_destroy_multithread when building shared-glapi on windows
Which will allow meson to build a shared glapi build with mingw.
v2: - Add symbol to symbol check test
Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Wed, 18 Apr 2018 20:01:09 +0000 (13:01 -0700)]
meson: add a expat subproject
For Windows
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Thu, 5 Apr 2018 23:14:07 +0000 (16:14 -0700)]
meson: add a zlib subproject
To help windows build
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Fri, 6 Apr 2018 21:10:00 +0000 (14:10 -0700)]
add a git ignore for subprojects
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Fri, 31 May 2019 23:20:35 +0000 (16:20 -0700)]
meson: don't build glapi_static_check_table on windows
It doesn't compile due to undefined symbols, which are in
libglapi_static, so I don't understand the problem.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Fri, 31 May 2019 23:16:22 +0000 (16:16 -0700)]
meson: Make shared-glapi a combo
So it can auto off for windows, but on elsewhere.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Fri, 31 May 2019 23:13:11 +0000 (16:13 -0700)]
meson: don't try to generate i18n translations on windows
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Fri, 31 May 2019 17:13:55 +0000 (10:13 -0700)]
glsl/tests: Handle windows \r\n new lines
Currently the praser for s expressions assumes that newlines will be \n,
resulting in incorrect parsing on windows, where the newline is \r\n.
This patch just adds \r? to the regular expression used to parse the s
expressions, which fixes at 1 test on windows.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Kenneth Graunke [Tue, 10 Sep 2019 16:04:20 +0000 (09:04 -0700)]
iris: Fix constant buffer sizes for non-UBOs
Since the system value refactor, we've accidentally only been setting
cbuf->buffer_size in the UBO case, and not in the uploaded-constants
case. We use cbuf->buffer_size to fill out the SURFACE_STATE entry,
so it needs to be initialized in both cases.
Fixes: 3b6d787e404 ("iris: move sysvals to their own constant buffer")
Lionel Landwerlin [Tue, 10 Sep 2019 09:45:50 +0000 (12:45 +0300)]
intel: update product names for WHL
Documentation list all of those as "UHD".
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111629
BSpec: 33266
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Samuel Pitoiset [Tue, 3 Sep 2019 11:01:54 +0000 (13:01 +0200)]
radv/gfx10: declare a LDS symbol for the NGG emit space
This fixes some interactions when NGG GS is enabled. It fixes:
- dEQP-VK.clipping.user_defined.clip_cull_distance_dynamic_index.*geom*
- dEQP-VK.tessellation.geometry_interaction.passthrough.*
For some reasons, using the computed ESGS ring size randomly hangs
with CTS. For now, just use the maximum LDS size for ESGS.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Sep 2019 10:46:55 +0000 (12:46 +0200)]
radv: calculate GFX9 GS and GFX10 NGG states before compiling shader variants
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Sep 2019 09:34:42 +0000 (11:34 +0200)]
radv: store the ESGS ring size as part of gfx10_ngg_info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Sep 2019 09:20:54 +0000 (11:20 +0200)]
radv: store GFX10 NGG state as part of the shader info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Sep 2019 09:14:18 +0000 (11:14 +0200)]
radv: store GFX9 GS state as part of the shader info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Sep 2019 08:29:19 +0000 (10:29 +0200)]
radv: fill shader info for all stages in the pipeline
This shouldn't be in NIR->LLVM because ACO also needs the shader
info. This will also help for computing some NGG values that are
necessary for declaring LDS symbols.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Sep 2019 07:49:14 +0000 (09:49 +0200)]
radv: do not pass all compiler options to the shader info pass
Only the pipeline layout and the shader keys are needed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Marek Olšák [Thu, 29 Aug 2019 01:27:05 +0000 (21:27 -0400)]
radeonsi: remove redundant si_texture offset and size fields
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Wed, 28 Aug 2019 01:18:20 +0000 (21:18 -0400)]
radeonsi: move texture storage allocation outside of radeonsi
possible code sharing with radv
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Wed, 28 Aug 2019 01:07:41 +0000 (21:07 -0400)]
radeonsi: move HTILE allocation outside of radeonsi
ac_surface computes it for amdgpu.
radeon_drm_surface computes it for radeon.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Wed, 28 Aug 2019 00:32:46 +0000 (20:32 -0400)]
radeonsi: handle NO_DCC early
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Wed, 28 Aug 2019 00:29:11 +0000 (20:29 -0400)]
ac/surface: add RADEON_SURF_NO_FMASK
This controls FMASK and CMASK computation for MSAA.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Tue, 27 Aug 2019 23:35:25 +0000 (19:35 -0400)]
r300,r600,radeonsi: set winsys_handle::stride,offset in drivers, not winsyses
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Tue, 27 Aug 2019 23:35:25 +0000 (19:35 -0400)]
r300,r600,radeonsi: read winsys_handle::stride,offset in drivers, not winsyses
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Wed, 28 Aug 2019 21:38:50 +0000 (17:38 -0400)]
radeonsi/gfx10: fix wave occupancy computations
Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Tue, 27 Aug 2019 21:39:02 +0000 (17:39 -0400)]
radeonsi: only support at most 1024 threads per block
LLVM 10 won't support 2048.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Tue, 27 Aug 2019 18:37:24 +0000 (14:37 -0400)]
radeonsi: disable DCC when importing a texture from an incompatible driver
and unify the code.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Fri, 23 Aug 2019 23:17:05 +0000 (19:17 -0400)]
radeonsi/gfx10: don't call gfx10_destroy_query with compute-only contexts
This fixes a crash.
Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Mon, 26 Aug 2019 20:20:44 +0000 (16:20 -0400)]
radeonsi/gfx10: use fma for TGSI_OPCODE_FMA
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Mon, 26 Aug 2019 20:19:31 +0000 (16:19 -0400)]
ac: use fma on gfx10
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Thu, 15 Aug 2019 20:53:34 +0000 (16:53 -0400)]
ac: enable LLVM atomic optimizations
Lepton Wu [Tue, 10 Sep 2019 03:42:55 +0000 (03:42 +0000)]
virgl: Fix pipe_resource leaks under multi-sample.
Fixes: 900a80f9e4f ("virgl: virgl_transfer should own its virgl_resource")
Signed-off-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Kenneth Graunke [Sun, 8 Sep 2019 05:51:15 +0000 (22:51 -0700)]
iris: Avoid flushing for cache history on transfer range flushes
The VBO module maps a buffer with GL_MAP_FLUSH_EXPLICIT, and keeps
appending data, and calling glFlushMappedBufferRange(). We were
invalidating the VF cache each time it flushed a new range, which
results in a ton of VF flushes.
If the contents of the destination in the target range are undefined
(never even possibly written), this patch makes us assume that it's
likely not in the cache and so cache invalidations are required. If
the destination range is defined, we continue cache flushing as we may
need to expunge stale data.
This eliminates 88% of the VF cache invalidates on Manhattan 3.0.
Improves performance in Manhattan 3.0 on my Icelake 8x8 with the GPU
frequency locked to 700Mhz by 0.376724% +/- 0.
0989183% (n=10).
Kenneth Graunke [Sun, 8 Sep 2019 05:30:02 +0000 (22:30 -0700)]
iris: Optimize out redundant sampler state binds
This cuts roughly 85% of the 3DSTATE_SAMPLER_STATE_POINTERS_PS calls in
the J2DBench images test. For some reason, the state tracker is calling
bind_sampler_state with the same sampler state in a bunch of cases.
Kenneth Graunke [Sun, 8 Sep 2019 04:18:51 +0000 (21:18 -0700)]
iris: Add support for the always_flush_cache=true debug option.
This can be useful for debugging missing flushes.
Adam Jackson [Fri, 6 Sep 2019 16:30:19 +0000 (12:30 -0400)]
mesa: Eliminate gl_config::rgbMode
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Adam Jackson [Fri, 6 Sep 2019 15:51:23 +0000 (11:51 -0400)]
mesa: Eliminate gl_config::have{Accum,Depth,Stencil}Buffer
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Adam Jackson [Fri, 6 Sep 2019 15:43:19 +0000 (11:43 -0400)]
mesa: Remove unused gl_config::indexBits
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Adam Jackson [Mon, 9 Sep 2019 17:59:34 +0000 (13:59 -0400)]
gallium/xlib: Fix an obvious thinko
x == !GLX_DIRECT_COLOR is a fancy way of writing x == 0, which is
clearly not what was meant.
Kenneth Graunke [Sun, 8 Sep 2019 06:43:05 +0000 (23:43 -0700)]
iris: Ignore line stipple information if it's disabled
The line stipple pattern and factor only matter if line stippling is
actually enabled. Otherwise, we can safely ignore it.
PBO upload may give us zero for line stipple information, while normal
drawing tends to give us an actual stipple pattern such as 0xffff. This
was causing us to flag IRIS_DIRTY_LINE_STIPPLE way too often, leading to
useless 3DSTATE_LINE_STIPPLE commands, which are non-pipelined and thus
very expensive.
Improves performance in Manhattan 3.0 on Skylake GT4e by
0.149261% +/- 0.
0380796% (n=210). On an Icelake 8x8 with the GPU
frequency locked at 700Mhz, improves by 0.423756% +/- 0.222843% (n=3).
Vasily Khoruzhick [Wed, 4 Sep 2019 05:58:05 +0000 (22:58 -0700)]
lima/ppir: drop fge/flt/feq/fne options
These are supposed to be lowered into sge/slt/seq/sne equivalents.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Vasily Khoruzhick [Wed, 4 Sep 2019 05:55:48 +0000 (22:55 -0700)]
lima: run opt_algebraic between int_to_float and boot_to_float for vs
int_to_float emits ftrunc and ftrunc lowering generates bool ops.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Vasily Khoruzhick [Sun, 1 Sep 2019 21:38:08 +0000 (14:38 -0700)]
lima/gpir: fix warning in gpir disassembler
Fixes following warning:
../src/gallium/drivers/lima/ir/gp/disasm.c: In function ‘print_src’:
../src/gallium/drivers/lima/ir/gp/disasm.c:241:20: warning: array subscript 28 is above array bounds of ‘char[5]’ [-Warray-bounds]
241 | "xyzw"[src - gpir_codegen_src_attrib_x]);
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Vasily Khoruzhick [Sun, 1 Sep 2019 21:37:23 +0000 (14:37 -0700)]
lima/gpir: lower fceil
GP doesn't support fceil so we need to lower it.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Connor Abbott [Sun, 8 Sep 2019 16:48:35 +0000 (18:48 +0200)]
lima/gpir: Disallow moves for schedule_first nodes
The entire point of schedule_first is that the node has to be scheduled
as soon as possible without any moves because it doesn't produce a
proper floating-point value, or its value changes depending on where you
read it. We were still introducing a move for preexp2 in some cases
though, even if it got scheduled as soon as possible, which broke some
exp() tests. Fix that.
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Connor Abbott [Sat, 7 Sep 2019 14:40:14 +0000 (16:40 +0200)]
lima/gpir: Fix fake dep handling for schedule_first nodes
The whole point of schedule_first nodes is that they need to be
scheduled as soon as possible, so if a schedule_first node is the
successor in a fake dependency that prevents it from being scheduled
after its parent, that can cause problems. We need to add these fake
dependencies to the parent as well, and we need to guarantee that the
pre-RA scheduler puts schedule_first nodes right before their parents in
order to prevent this from adding cycles to the dependency graph.
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Connor Abbott [Mon, 2 Sep 2019 20:31:00 +0000 (22:31 +0200)]
lima/gpir: Fix schedule_first insertion logic
The idea was to make sure schedule_first nodes were always first in the
ready list. I made sure they were inserted first, but not that other
nodes wouldn't later be scheduled ahead of them. Fixes
spec@glsl-1.10@execution@built-in-functions@vs-exp-float and probably
others.
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Connor Abbott [Mon, 2 Sep 2019 07:48:54 +0000 (09:48 +0200)]
lima/gpir: Ignore unscheduled successors in can_use_complex()
The point of the function is to avoid creating a complex move which is
used by certain slots in the next instruction, but unscheduled
successors will never be in the next instruction. Found while debugging
a crash that the previous commit fixed.
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Connor Abbott [Sun, 1 Sep 2019 17:33:06 +0000 (19:33 +0200)]
lima/gpir: Do all lowerings before rsched
The scheduler assumes that load nodes are always duplicated so that they
can always be scheduled eventually and therefore they never need to be
spilled. But some lowerings were running after the pre-RA scheduler,
whereas duplication has to happen before then since it's needed for the
scheduler to do a better job reducing register pressure. This meant
that lowerings were introducing multiple uses of a load instruction,
which broke the scheduler's expectation and resulted in infinite loops
in situations where the only nodes available to spill were load nodes.
Spilling load nodes would be silly, so we want to fix the lowerings
rather than the scheduler. Just do all lowerings before the pre-RA
scheduler, which also helps with reducing pressure since the scheduler
can more accurately compute the pressure.
Fixes lima/mesa#104.
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Mauro Rossi [Sun, 8 Sep 2019 15:35:22 +0000 (17:35 +0200)]
android: anv: libmesa_vulkan_common: add libmesa_util static dependency
Change needed to fix the following building error:
In file included from external/mesa/src/intel/vulkan/anv_device.c:43:
external/mesa/src/util/xmlpool.h:115:10: fatal error: 'xmlpool/options.h' file not found
^~~~~~~~~~~~~~~~~~~
1 error generated.
Fixes: 4dcb1ff ("anv: add support for driconf")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Boris Brezillon [Thu, 5 Sep 2019 19:41:33 +0000 (21:41 +0200)]
panfrost: Rename pan_bo_cache.c into pan_bo.c
So we can move all the BO logic into this file instead of having it
spread over pan_resource.c, pan_drm.c and pan_bo_cache.c.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Boris Brezillon [Thu, 5 Sep 2019 19:41:32 +0000 (21:41 +0200)]
panfrost: Get rid of the now unused SLAB allocator
The last users have been converted to use plain BOs. Let's get rid of
this abstraction. We can always consider adding it back if we need it
at some point.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Boris Brezillon [Thu, 5 Sep 2019 19:41:31 +0000 (21:41 +0200)]
panfrost: Get rid of unused panfrost_context fields
Some fields in panfrost_context are unused (probably leftovers from
previous refactor). Let's get rid of them.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Boris Brezillon [Thu, 5 Sep 2019 19:41:30 +0000 (21:41 +0200)]
panfrost: Convert ctx->{scratchpad, tiler_heap, tiler_dummy} to plain BOs
ctx->{scratchpad,tiler_heap,tiler_dummy} are allocated using
panfrost_drm_allocate_slab() but they never any of the SLAB-based
allocation logic. Let's convert those fields to plain BOs.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Boris Brezillon [Thu, 5 Sep 2019 19:41:29 +0000 (21:41 +0200)]
panfrost: Make transient allocation rely on the BO cache
Right now, the transient memory allocator implements its own BO caching
mechanism, which is not really needed since we already have a generic
BO cache. Let's simplify things a bit.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Boris Brezillon [Thu, 5 Sep 2019 19:41:28 +0000 (21:41 +0200)]
panfrost: Stop passing a ctx to functions being passed a batch
The context can be retrieved from batch->ctx.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Boris Brezillon [Thu, 5 Sep 2019 19:41:27 +0000 (21:41 +0200)]
panfrost: Pass a batch to panfrost_drm_submit_vs_fs_batch()
Given the function name it makes more sense to pass it a job batch
directly.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Boris Brezillon [Thu, 5 Sep 2019 19:41:26 +0000 (21:41 +0200)]
panfrost: s/job/batch/
What we currently call a job is actually a batch containing several jobs
all attached to a rendering operation targeting a specific FBO.
Let's rename structs, functions, variables and fields to reflect this
fact.
Suggested-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Heinrich Fink [Tue, 30 Jul 2019 13:58:20 +0000 (15:58 +0200)]
egl: Add GL_MESA_EGL_sync support
This commit follow OES_EGL_sync to universially enable use of EGL sync
objects with desktop OpenGL contexts.
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Heinrich Fink [Tue, 30 Jul 2019 14:14:07 +0000 (16:14 +0200)]
headers: Add GL_MESA_EGL_sync token to GL
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Heinrich Fink [Tue, 30 Jul 2019 14:12:20 +0000 (16:12 +0200)]
registry: update gl.xml with GL_MESA_EGL_sync token
As added by upstream GL registry changes
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Heinrich Fink [Mon, 29 Jul 2019 14:47:20 +0000 (16:47 +0200)]
specs: Add GL_MESA_EGL_sync
Adds GL_MESA_EGL_sync as defined in upstream OpenGL registry
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tapani Pälli [Fri, 6 Sep 2019 05:05:02 +0000 (08:05 +0300)]
android: fix linking issues with liblog
Fixes Android build errors observed in Intel CI.
Fixes: f9f7cbc1aa3 "util: android logging support"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Kenneth Graunke [Thu, 5 Sep 2019 08:52:17 +0000 (01:52 -0700)]
iris: Support the disable_throttling=true driconf option.
Jason Ekstrand [Fri, 30 Aug 2019 16:35:26 +0000 (11:35 -0500)]
nir/dead_cf: Repair SSA if the pass makes progress
The dead_cf pass calls into the CF manipulation helpers which attempt to
keep NIR's SSA form sane. However, when the only break is removed from
a loop, dominance gets messed up anyway because the CF SSA clean-up code
only looks at phis and doesn't consider the case of code becoming
unreachable. One solution to this would be to put the loop into LCSSA
form before we modify any of its contents. Another (and the approach
taken by this pass) is to just run the repair_ssa pass afterwards
because the CF manipulation helpers are smart enough to keep all the
use/def stuff sane; they just don't always preserve dominance
properties.
While we're here, we clean up some bogus indentation.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111405
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111069
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 30 Aug 2019 19:16:07 +0000 (14:16 -0500)]
nir/repair_ssa: Insert deref casts when needed
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Mon, 2 Sep 2019 17:54:31 +0000 (12:54 -0500)]
nir/repair_ssa: Repair dominance for unreachable blocks
NIR currently assumes that unreachable blocks are trivially dominated by
everything. However, when considering well-formed SSA, there is no path
from any block to an unreachable block. Therefore, we can break any
use-def chains where the use is in an unreachable block. This removes
any dependencies on code created by uses in unreachable blocks and lets
DCE do a better job of cleaning it up.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Mon, 2 Sep 2019 17:53:16 +0000 (12:53 -0500)]
nir: Add a block_is_unreachable helper
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 30 Aug 2019 18:55:02 +0000 (13:55 -0500)]
nir: Don't infinitely recurse in lower_ssa_defs_to_regs_block
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 30 Aug 2019 18:21:00 +0000 (13:21 -0500)]
nir: Handle complex derefs in nir_split_array_vars
We already bail and don't split the vars but we were passing a NULL to
_mesa_hash_table_search which is not allowed.
Fixes: f1cb3348f1 "nir/split_vars: Properly bail in the presence of ..."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sat, 3 Feb 2018 17:12:15 +0000 (09:12 -0800)]
intel/blorp: Use wide formats for nicely aligned stencil clears
In the case where the stencil clear is nicely aligned, we can clear
stencil much more efficiently by mapping it as a wide format (say
RGBA32_UINT) and blasting out the stencil clear value with a repclear.
On Unigine Heaven, this makes one stencil clear go from non-trivial to
unnoticeable when looking at per-draw timings.
In order for this change to work properly, ANV needs to do a bit more
flushing around depth and stencil clears. i965 and iris already have
the cache tracking logic to handle this so no changes are required
there.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Sun, 1 Sep 2019 14:07:38 +0000 (09:07 -0500)]
intel/blorp: Expose surf_fake_interleaved_msaa internally
Jason Ekstrand [Sat, 3 Feb 2018 19:46:04 +0000 (11:46 -0800)]
intel/blorp: Expose surf_retile_w_to_y internally
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Sat, 31 Aug 2019 04:57:52 +0000 (23:57 -0500)]
blorp: Memset surface info to zero when initializing it
This isn't known to fix any current bugs but it does prevent a
regression in a subsequent commit.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Sat, 31 Aug 2019 19:11:49 +0000 (14:11 -0500)]
intel/tools: Decode PS kernels on SNB
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>