i965: Port Gen6+ 3DSTATE_CLIP state to genxml.

Emit clip state on Gen6+ using brw_batch_emit helper, using pack structs
from genxml.

v3:
   - Lots style fixes (Ken)
   - Do not set CullTestEnableBitMask on Gen8+ (Ken)
v4:
   - Do not include brw_defines_common.h.
v5 (Ken): s/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Port Gen6+ DEPTH_STENCIL state to genxml.

This emits 3DSTATE_WM_DEPTH_STENCIL on Gen8+ or DEPTH_STENCIL_STATE
(and the relevant pointer packets) on Gen6-7.5 from a single function.

v3:
   - Watch for BRW_NEW_BATCH too on gen < 8 (Ken)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Get real per-gen atom lists

Make atoms initalization compile conditionally based on the target
platform.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>

i965: Add genxml related plumbing in a new genX_state_upload.c file.

v3 (Rafael): Drop aub parameter
v4 (Ken): Squash in gen4/g45 automake fixes

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>

i965: Drop "Destination Element Offset" from Ironlake SGVs.

The Ironlake documentation is terrible, so it's unclear whether or not
this field exists there.  It definitely doesn't exist on Sandybridge
and later.  It definitely does exist on G45.

We haven't been setting it for our normal vertex attributes - just
the SGVs (VertexID, InstanceID, BaseVertex, BaseInstance, DrawID).
We should be consistent.  My guess is that it isn't necessary and
doesn't exist - this patch drops it from the SGVs elements, making
them follow the behavior of most attributes.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

genxml: Fix 3DSTATE_DEPTH_BUFFER length on gen5.

The hardware docs are wrong, but the length used in the xml is also
wrong.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: constify a bunch of the perfcounter structs.

This moves the structs from the data segment to the rodata segment,
which seems like the more correct place for them.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

st/glsl_to_tgsi: remove unrequired tgsi_get_opcode_info() call

This is already set for the instruction at initialisation.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: make _mesa_accum() static

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa: tidy up accum.h

These were unused.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa/varray: make use of dispatch KHR_no_error support

Make use of dispatch KHR_no_error support for varray functions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

glapi: add KHR_no_error support to dispatch table generation

This will allows us to create no error versions of functions
noted by a _no_error suffix. We also need to set a no_error
attribute equal to "true" in the xml.

V3: stop the no_error attribute being overwritten when functions
    alias another.
V2: tidy up suggested by Nicolai.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radv: Don't use FLAT_SHADE for constants.

Setting both offset to 0x20 and flat shade results in passthrough
mode instead of the constant.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: f205e19e4f8 "radv/ac: eliminate unused vertex shader outputs. (v2)"

i965: Move MOCS macros to brw_context.h.

These macros are defined in brw_defines.h, which contains a lot of
macros that conflict with autogenerated code from genxml. But we need to
use them (the MOCS macros) in some of that same genxml code.

Moving them to brw_context.h solves that problem and we don't have to
include brw_defines.h.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv: Use BRW_BARYCENTRIC_NONPERSPECTIVE_BITS from common header.

In a previous patch some enums were split out from brw_eu_defines.h, so
they could be used by genxml based code. anv can also benefit from this.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Move enums to brw_compiler.h.

These enums live inside struct brw_wm_prog_data, so it makes sense to
keep them in the same header. It also allows to use them without
including brw_eu_defines.h.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Update 3DSTATE_LINE_STIPPLE xml on gen6.

From the PRM, Line Stipple Inverse Repeat Count is on dw2, bits 31:16,
format U1.13.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS.

   - "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid"
   - "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer"
   - "BackFace" -> "Backface"

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Normalize xml for 3DSTATE_MULTISAMPLE.

Name the options to "Pixel Location":
   - PIXLOC_CENTER -> CENTER
   - PIXLOC_UL_CORNER -> UL_CORNER

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Rename "Function Enable" to "Enable".

Rename that field name on genxml for:
   - 3DSTATE_GS - gen6+
   - 3DSTATE_DS - gen7+
   - 3DSTATE_HS - gen7+

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Clip guardbands are float, not int.

This makes genxml create the right struct types, and generate the right
batch commands.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: 3DSTATE_VS rename Function Enable to Enable.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Make "Reorder Mode" fields consistent.

Both GS and SOL have these fields.  Some were ReorderEnable = true,
some were ReorderMode = REORDER_TRAILING, and some were just TRAILING.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

genxml: Add alias for MOCS.

Use an alias, so we can set the same value as the #define's.

v3:
   - Call it "SO Buffer MOCS" to follow the most common naming scheme.
   - Add alias for gen7 and gen75 too (Ken).

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Add missing field values to 3DSTATE_SBE.

Fill out "Attribute Active Component Format" possible values.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Update xml for 3DSTATE_SF.

 - Normalize "Anti-Aliasing Enable"
 - Add "Multisample Rasterization Mode" constants
 - Rename "Use Point Width on Vertex" to "Vertex"
 - Rename "Use Point Width from State" to "State"

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Rename clip enable property.

There are two variants:
   - Clip Enable
   - CLIP Enable (on gen6)

Rename everything to Clip Enable.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Fill out Gen4, Gen45 and Gen5 XML

Add some more details to Gen4 and Gen45 and add what is needed
in Gen5 XML. This commit overwrite the previous work done on Gen4
and Gen45 as it contains more instructions and fixes some mistakes.
However, comments (dword boundaries) are lost in the process.

v3:
   - Set the type of some fields, instead of prefix. Also fix the
     SAMPLER_BORDER_COLOR_STATE fields of gen5.xml.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

anv: Implement VK_KHX_external_semaphore_fd

This implementation allocates a 4k BO for each semaphore that can be
exported using OPAQUE_FD and uses the kernel's already-existing
synchronization mechanism on BOs.

Reviewed-by: Chad Versace <chadversary@chromium.org>

anv: Pull the guts of cmd_buffer_execbuf into a helper

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

anv: Implement VK_KHX_external_semaphore

Reviewed-by: Chad Versace <chadversary@chromium.org>

anv: Implement VK_KHX_external_semaphore_capabilities

This just stubs things out.  Real external semaphore support will come
with VK_KHX_external_semaphore_fd.

Reviewed-by: Chad Versace <chadversary@chromium.org>

anv: Add a real semaphore struct

It's just a dummy for now, but we'll flesh it out as needed for external
semaphores.

Reviewed-by: Chad Versace <chadversary@chromium.org>

radeonsi/gfx9: fix gl_ViewportIndex

v2: remove unnecessary LLVMBuildAnd calls

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set VGT_REUSE_OFF = 0

same as Vulkan

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

etnaviv: add L8A8_UNORM texture format

No piglit regressions.

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

glsl: Corrected some typos and error messages

v2: left code style/formatting corrections out.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

radv: don't leak DRM devices

After successful drmGetDevices2() call, drmFreeDevices() needs to be called.

Fixes: 743315f2 "radv: do not open random render node(s)"
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: fix possible stack corruption

drmGetDevices2 takes count and not size. Probably hasn't caused problems
yet in practice and was missed as setups with more than 8 DRM devices
are not very common.

Fixes: 743315f2 "radv: do not open random render node(s)"
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: eliminate duplicated VS exports

Only very few shaders have them (from 48486 shaders):

shaders/private/left_4_dead_2/765.shader_test - ac: 1 matches 2
shaders/private/left_4_dead_2/877.shader_test - ac: 1 matches 6
shaders/private/left_4_dead_2/2141.shader_test - ac: 1 matches 6
shaders/private/ue4_effects_cave/11.shader_test - ac: 4 matches 5
shaders/private/ue4_effects_cave/14.shader_test - ac: 5 matches 6
shaders/private/ue4_effects_cave/46.shader_test - ac: 5 matches 6
shaders/private/ue4_effects_cave/42.shader_test - ac: 4 matches 5
shaders/private/ue4_effects_cave/104.shader_test - ac: 4 matches 5
shaders/private/f1-2015/336.shader_test - ac: 3 matches 4
shaders/private/f1-2015/948.shader_test - ac: 6 matches 7
shaders/private/f1-2015/602.shader_test - ac: 0 matches 3
shaders/private/f1-2015/600.shader_test - ac: 0 matches 3
shaders/private/f1-2015/1214.shader_test - ac: 0 matches 1
shaders/private/f1-2015/988.shader_test - ac: 4 matches 5
shaders/private/ue4_elemental/149.shader_test - ac: 3 matches 4
shaders/private/ue4_elemental/346.shader_test - ac: 4 matches 5
shaders/private/ue4_elemental/178.shader_test - ac: 3 matches 4
shaders/private/ue4_elemental/136.shader_test - ac: 4 matches 5
shaders/private/ue4_elemental/168.shader_test - ac: 4 matches 5
shaders/private/ue4_elemental/690.shader_test - ac: 3 matches 4
shaders/private/ue4_elemental/19.shader_test - ac: 5 matches 6
shaders/private/dota2/1901.shader_test - ac: 0 matches 5
shaders/private/dota2/1357.shader_test - ac: 0 matches 5
shaders/private/dota2/1375.shader_test - ac: 0 matches 5
shaders/private/dota2/1369.shader_test - ac: 0 matches 5
shaders/private/dota2/1583.shader_test - ac: 0 matches 5
shaders/private/dota2/1811.shader_test - ac: 0 matches 5
shaders/private/dota2/1893.shader_test - ac: 0 matches 5
shaders/private/dota2/1533.shader_test - ac: 0 matches 5
shaders/private/dota2/1951.shader_test - ac: 0 matches 5
shaders/private/dota2/1361.shader_test - ac: 0 matches 5
shaders/private/mad_max/2792.shader_test - ac: 0 matches 1
shaders/private/mad_max/2794.shader_test - ac: 0 matches 1
shaders/private/mad_max/2780.shader_test - ac: 0 matches 1
shaders/private/mad_max/2902.shader_test - ac: 0 matches 1
shaders/private/bioshock-infinite/3050.shader_test - ac: 3 matches 7
shaders/private/bioshock-infinite/2544.shader_test - ac: 3 matches 6
shaders/private/bioshock-infinite/3062.shader_test - ac: 3 matches 8
shaders/private/bioshock-infinite/2012.shader_test - ac: 3 matches 7
shaders/private/bioshock-infinite/3058.shader_test - ac: 3 matches 7
shaders/private/bioshock-infinite/3270.shader_test - ac: 3 matches 7
shaders/private/bioshock-infinite/732.shader_test - ac: 3 matches 7
shaders/private/bioshock-infinite/3026.shader_test - ac: 3 matches 7
shaders/private/bioshock-infinite/3258.shader_test - ac: 3 matches 6
shaders/private/bioshock-infinite/3198.shader_test - ac: 3 matches 6
shaders/private/bioshock-infinite/3046.shader_test - ac: 3 matches 7
shaders/private/bioshock-infinite/3168.shader_test - ac: 3 matches 6
shaders/private/bioshock-infinite/2550.shader_test - ac: 3 matches 6
shaders/private/bioshock-infinite/3210.shader_test - ac: 3 matches 6
shaders/private/bioshock-infinite/3032.shader_test - ac: 3 matches 6
shaders/private/bioshock-infinite/668.shader_test - ac: 3 matches 7

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: rename ac_eliminate_const_vs_outputs -> ac_optimize_vs_outputs

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: first parse VS exports before eliminating constant ones

A later commit will make use of this.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

anv: Trivially implement multiDrawIndirect

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv: Enable VK_KHX_multiview and SPV_KHR_multiview

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv/cmd_buffer: Emit instanced draws for multiple views

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv/cmd_buffer: Pull indirect draw parameter loading into a helper

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv/pipeline: Add shader lowering for multiview

v2 (Jason Ekstrand):
 - Take a view_mask rather than a whole subpass
 - Build the view mask into the VS shader key

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv/pipeline: Add a subpass field to anv_pipeline

This simplifies the code a variety of places.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv/pipeline: Call nir_gather_info later

We want to insert more lowering code that may insert system values and
we need to gather info after that lowering.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv: Move shader hashing to anv_pipeline

Shader hashing is very closely related to shader compilation.  Putting
them right next to each other in anv_pipeline makes it easier to verify
that we're actually hashing everything we need to be hashing.  The only
real change (other than the order of hashing) is that we now hash in the
shader stage.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv/pass: Store the per-subpass view mask

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv: Add the KHX_multiview boilerplate

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv/nir: Delete the apply_dynamic_offsets prototype

That pass hasn't existed since dd4db84640bbb694f180dd50850c3388f67228be
but the prototype stuck around for no reason.

Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

spirv: Add support for SPV_KHR_multiview

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

spirv: Bump the SPIR-V header to the latest public version

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

compiler: Add a system value and varying for ViewIndex

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

mesa/vbo: reduce prim array size

We always use only single element.

v2: Change single element arrays to variables

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add const qualifier on _mesa_valid_to_render()

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965/vec4: don't modify regioning parameters to the sources of DF align1 instructions

The regioning parameters are now properly set by convert_to_hw_regs()
and we don't need to fix them in the generator. That latter fix
previously done in the generator was strictly speaking wrong for any
non-identity regions.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/vec4: fix register width for DF VGRF and UNIFORM

On gen7, the swizzles used in DF align16 instructions works for element
size of 32 bits, so we can address only 2 consecutive DFs. As we assumed that
in the rest of the code and prepare the instructions for this (scalarize_df()),
we need to set it to two again.

However, for DF align1 instructions, a width of 2 is wrong as we are not
reading the data we want. For example, an uniform would have a region of
<0, 2, 1> so it would repeat the first 2 DFs, when we wanted to access
to the first 4.

This patch sets the default one to 4 and then modifies the width of
align16 instruction's DF sources when we translate the logical swizzle
to the physical one.

v2:
- Remove conditional (Curro).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/vec4: fix vertical stride to avoid breaking region parameter rule

From IVB PRM, vol4, part3, "General Restrictions on Regioning
Parameters":

  "If ExecSize = Width and HorzStride ≠ 0, VertStride must
   be set to Width * HorzStride."

In next patch, we are going to modify the region parameter for
uniforms and vgrf. For uniforms that are the source of
DF align1 instructions, they will have <0, 4, 1> regioning and
the execsize for those instructions will be 4, so they will break
the regioning rule. This will be the same for VGRF sources where
we use the vstride == 0 exploit.

As we know we are not going to cross the GRF boundary with that
execsize and parameters (not even with the exploit), we just fix
the vstride here.

v2:
- Move is_align1_df() (Curro)
- Refactor exec_size == width calculation (Curro)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

radv/ac: canonicalize the output for 32-bit float min/max.

This fixes:
dEQP-VK.glsl.builtin.precision.min.*
dEQP-VK.glsl.builtin.precision.max.*
dEQP-VK.glsl.builtin.precision.clamp.*

The problem is the hw doesn't compare denorms properly,
so we have to flush them, even though the spec says
flushing is optional, if you don't flush the results
should be correct.

The -pro driver changes the shader float mode,
it would be nice if llvm could grow that perhaps.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: flush f32->f16 conversion denormals to zero. (v2)

SPIR-V defines the f32->f16 operation as flushing denormals to 0,
this compares the class using amd class opcode.

Thanks to Matt Arsenault for figuring it out.

This fix is VI+ only, add a TODO for SI/CIK.

This fixes:
dEQP-VK.spirv_assembly.instruction.compute.opquantize.flush_to_zero

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Add userspace fence buffer per context.

Having it in the winsys didn't work when multiple devices use
the same winsys, as we then have multiple contexts per queue,
and each context counts separately.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: 7b9963a28f4 "radv: Enable userspace fence checking."

radv: enable lower_sub to fix loop unrolling.

Loop unroll asserts if it hits a sub, we don't really want
to lower subs as llvm handles these things, but do this for
now, until we can fix loop unroll to work with subs.

Fixes: 14ae0bfa5 (radv: Add NIR loop unrolling)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Don't set dynamic state for pipelines with rasterizer dicard.

All of the dynamic states apply to rasterization & fragment processing,
so we don't need to set them if we don't rasterize.

We don't clear the dirty flags for them though, so we don't miss any
updates for the next pipeline with rasterization.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: 76603aa90b8 "radv: Drop the default viewport when 0 viewports are given."

radv: flush more stages when semaphore are waiting.

This still doesn't give us complete pWaitDstStageMask support,
but it should provide enough to be correct if not as efficent as
possible.

If we have wait semaphores we must flush between submits and
flush the shaders as well.

This fixes the remaining fails in:
dEQP-VK.synchronization.op.single_queue.semaphore.*ssbo*

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

glsl: set vector_elements to 1 for samplers

I don't see any reasons why vector_elements is 1 for images and
0 for samplers. This increases consistency and allows to clean
up some code a bit.

This will also help for ARB_bindless_texture.

No piglit regressions with RadeonSI.

This time the Intel CI system doesn't report any failures.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

vc4: Use runtime CPU detection for whether NEON is available.

This will allow Raspbian's ARMv6 builds to take advantage of the new NEON
code, and could prevent problems if vc4 ends up getting used on a v7 CPU
without NEON.

v2: Drop dead NEON_SUFFIX (noted by Erik Faye-Lund)

vc4: Use a wrapper file to set VC4_BUILD_NEON instead of CFLAGS.

Android.mk was setting the flag across the entire driver, so we didn't
have non-NEON versions getting built.  This was going to be a problem with
the next commit, when I start auto-detecting NEON support and use the
non-NEON version when appropriate.

Reviewed-by: Rob Herring <robh@kernel.org>

gallium: Enable ARM NEON CPU detection.

I wrote this code with reference to pixman, though I've only decided to
cover Linux (what I'm testing) and Android (seems obvious enough).  Linux
has getauxval() as a cleaner interface to the /proc entry, but it's more
glibc-specific and I didn't want to add detection for that.

This will be used to enable NEON at runtime on ARMv6 builds of vc4.

v2: Actually initialize the temp vars in the Android path (noticed by
    daniels)
v3: Actually pull in the cpufeatures library (change by robher).
    Use O_CLOEXEC.  Break out of the loop when we find our feature.
v4: Drop VFP code, which was confused about what it was detecting and not
    actually used yet.

Reviewed-by: Grazvydas Ignotas <notasas@gmail.com>

radv: fix stencil only clears.

If we are clearing stencil only, we still need to provide a
a valid Z output from the vertex shader, we can't rely
on the depth clear value having any meaning, as we use this
for the position output, and it could get clipped, so we
don't end up clearing anything.

Fixes:
dEQP-VK.renderpass.simple.stencil
since I added S8 support.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

renderonly: use drmIoctl

To restart interrupted system calls, use drmIoctl.

Fixes: 848b49b288f ("gallium: add renderonly library")
CC: <mesa-stable@lists.freedesktop.org>
Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

renderonly: drop resources on destroy

The renderonly_scanout holds a reference on its prime pipe resource,
which should be released when it is destroyed. If it was created by
renderonly_create_kms_dumb_buffer_for_resource, the dumb BO also has
to be destroyed.

Fixes: 848b49b288f ("gallium: add renderonly library")
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

renderonly: close transfer prime_fd

prime_fd is only used to transfer the scanout buffer to the GPU inside
renderonly_create_kms_dumb_buffer_for_resource. It should be closed
immediately to avoid leaking the DMA-BUF file handle.

Fixes: 848b49b288f ("gallium: add renderonly library")
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

radv/wsi: report presentation error per image request

This ports
0fcb92c17dee681bd39c08ddf0abc358a27337c7
anv: wsi: report presentation error per image request

This fixes:
dEQP-VK.wsi.xlib.incremental_present.scale_none.*

Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: minor pahole related improvements.

This just reduces the structs by 4-8 bytes each.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/image: resize some surface members.

Oops meant to be part of previous series.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: drop unused surface level members.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/image: drop blk_d

This was pretty much unused.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: remove some members of radeon surface.

We would be storing this info twice per image, no need to,
remove it from the surface struct.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: move some image info into a separate struct.

This is to rework the surface code like radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: provide a helper for comparing an image extents.

This just makes it easier to do the follow in cleanups of the surface.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

gbm/dri: Fix sign-extension in modifier query

When we were assembling the unsigned 64-bit query return from its
two signed 32-bit component parts, the lower half was getting
sign-extended into the top half. Be more explicit about what we want to
do.

Fixes gbm_bo_get_modifier() returning ((1 << 64) - 1) rather than
((1 << 56) - 1), i.e. DRM_FORMAT_MOD_INVALID.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

nir: Pick just the channels we want for bitmap and drawpixels lowering.

NIR now validates that SSA references use the same number of channels as
are in the SSA value.

v2: Reword commit message, since the commit didn't land before the
    validation change did.

Fixes: 370d68babcbb ("nir/validate: Validate that bit sizes and components always match")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v1)
Cc: <mesa-stable@lists.freedesktop.org>

anv/tests: Create a dummy instance as well as device

This fixes crashes caused by 35e626bd0e59e7ce9fd97ccef66b2468c09206a4
which made us start referencing the instance in the allocators.  With
this commit, the tests now happily pass again.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100877
Tested-by: Vinson Lee <vlee@freedesktop.org>

radv: Use correct stage for ready bit.

Set the bit in the same stage as the timestamp, instead always at top of pipe.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>

radv: Add top of pipe timestamp queries.

Does not fix brokenness with the ready bit.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Add NIR loop unrolling.

Not much effect on dota2/talos, but positive on deferred.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@itsqueeze.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

i965: Solve Android native fence fd double close

The Android native fence in i965 has two fds: _EGLSync::SyncFd and
brw_fence::sync_fd.

The semantics of __DRI2fenceExtensionRec::create_fence_fd are unclear on
whether the DRI driver takes ownership of the incoming fd (which is the
same incoming fd from eglCreateSync).  i965 did take ownership, but all
other Mesa drivers do not; instead, they dup the incoming fd. As
a result, _EGLSync::SyncFd and brw_fence::sync_fd were the same fd, and
both egl_dri2 and i965 believed they owned it. On eglDestroySync, that
led to a double-close.

Fix the double-close by making brw_dri_create_fence_fd dup the incoming
fd, just like the other drivers do.

Signed-off-by: Randy Xu <randy.xu@intel.com>
Test: Run Vulkan and GLES stress test and no crash.
Fixes: 6403e376511 ("i965/sync: Implement fences based on Linux sync_file")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
[chadv: Polish the commit message]
Cc: mesa-stable@lists.freedesktop.org

vc4: Only build the NEON code on arm32.

NEON is sufficiently different on arm64 that we can't just reuse this
code.  Disable it on arm64 for now.

v2: Use PIPE_ARCH_ARM instead, as __ARM_ARCH may be 8 for a 32-bit build
    for a v8 CPU.

Signed-off-by: Eric Anholt <eric@anholt.net>
Cc: <mesa-stable@lists.freedesktop.org>

gm107/ir: add a missing assertion in emitISCADD()

For consistency, similar to the other emitters.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

i965: Don't allocate uniform space for samplers

Samplers are encoded into the instruction word, so there's no need to
make space in the uniform file.

Previously matrix_columns and vector_elements were set to 0, making this
else case a no-op. Commit 75a31a20af26 changed that, causing malloc
corruption in thousands of tests on i965.

Fixes: 75a31a20af26 ("glsl: set vector_elements to 1 for samplers")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100871

egl: initialise dummy_thread via _eglInitThreadInfo

Considering we cannot make dummy_thread a constant we might as well,
initialise by the same function that handles the actual thread info.

This way we don't need to worry about mismatch between the initialiser
and initialising function.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

egl: polish dri2_to_egl_attribute_map[]

Annotate the array as static const and use C99 initialiser to populate
it.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

gallium/targets: fix bool setting on BE architectures

val_bool and val_int are in a union. val_bool gets the first byte, which
happens to work on LE when setting via the int, but breaks on BE. By
setting the value properly, we are able to use DRI3 on BE architectures.
Tested by running glxgears with a NV34 in a G5 PPC.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
[Emil Velikov: squash the vmwgfx hunk]
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

docs: add release calendar page and references to it

Add a page that has information which release is expected when and
associated information.

Reference to it from the "Releasing process" and "Release notes" pages.

v2:
 - Add Andres for 17.0.5
 - Rework table format to include the branch (Eric)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

travis: bump MAKEFLAGS to -j4

The instance should have 2 cores, yet bumping the jobs to 4 should give
us a minor speed improvement.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: enable wayland support

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: add Gallium state-tracker targets

Split into OpenCL and others, since the former is quite time consuming.

v2:
 - explicitly enable/disable components
 - build libvdpau 1.1 requirement
 - enable st/vdpau
 - build libva 1.6.2 (API 0.38) requirement

v3: Drop ubuntu-toolchain-r-test from sources (Andres)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>