mesa: Prevent _MaxLevel from being less than zero

When decoding using VDPAU, the _MaxLevel value becomes -1 due to
NumLevels being equal to 0 at a certain point, and decoding fails
due to an assertion later on.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>

ac: add ac_build_s_endpgm

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

ac: add 128-bit bitcount

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

ac/gpu_info: add pc_lines and use it in radeonsi

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

ac: unify primitive export code

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

ac: unify build_sendmsg_gs_alloc_req

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: clean up messy si_emit_rasterizer_prim_state

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: determine accurately if line stippling is enabled for performance

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: test polygon mode enablement accurately

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: fix context roll tracking in si_emit_shader_vs

probably harmless, because we don't need to track context rolls on gfx10

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: fix monolithic pixel shaders with two-sided colors and SampleMaskIn

They are never used except for testing AMD_DEBUG=mono.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

ac/gpu_info: always use distributed tessellation on gfx10

This might fix a hang on Navi14.

Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

gallium: bypass u_vbuf if it's not needed (no fallbacks and no user VBOs)

This decreases CPU overhead, because u_vbuf is completely bypassed
in those cases.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

gallium/cso_context: move non-vbuf vertex buffer and element code into helpers

These will be reused.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

gallium: put u_vbuf_get_caps return values into u_vbuf_caps

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

etnaviv: remove unnecessary vertex_elements_state_create error checking

PIPE_CAP_MAX_VERTEX_BUFFERS already sets the maximum vertex_buffer_index.

There's no need to error on num_elements == 0 (if that can even happen).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: implement gl_VertexID/gl_InstanceID

Fixes:
dEQP-GLES3.functional.instanced.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: HALTI2+ instanced draw

Fixes:
dEQP-GLES3.functional.draw.draw_arrays_instanced.*
dEQP-GLES3.functional.draw.draw_elements_instanced.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: update headers from rnndb

Update to etna_viv commit 46af5f1d.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

anv: don't close invalid syncfd semaphore

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

gallium/swr: Fix glVertexPointer race condition.

Sometimes using user buffer (not VBO) e.g. glVertexPointer
one thread could free memory before other thread used it.
Instead of copying this memory to driver simplier thing is
to block until draw finish.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>

intel/disasm: Fix decoding of src0 of SENDS

There is no instruction field for the register file for src0 because
it's always GRF.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>

meta: Add cleanup function for Bitmap

Buffer object and temporary texture were never freed, causing memory leaks.

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

nir/spirv: skip unreachable blocks in Phi second pass

Only the blocks that are reachable are inserted with an end_nop
instruction at the end.

When handling the Phi second pass, if the Phi has a parent block that
does not have an end_nop then it means this block is unreachable, and
thus we can ignore it, as the Phi will never come through it.

Fixes dEQP-VK.graphicsfuzz.uninit-element-cast-in-loop.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

radeonsi: check ctx->sdma_cs before using it

e5167a9276de1f383888714b41d3a9be2b9c1da9 disabled SDMA for gfx8.
This caused 3 piglit arb_sparse_buffer tests (basic, buffer-data
and commit) to crash on GFX8.

Reported-by: Michel Dänzer <michel@daenzer.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Fixes: e5167a9276d ("radeonsi: disable SDMA on gfx8 to fix corruption on RX 580")

radv: do not fill keys from fragment shader twice

radv_fill_shader_info() already does that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

main: allow external textures for BindImageTexture

From issue 10 of the OES_EGL_image_external_essl3:

  A limited set of use-cases is enabled by making glBindImageTexture
  accept external textures. Shaders can access such external textures
  using the existing <image2D> sampler type.

Fixes: 02a6d901eee ("mesa: add OES_EGL_image_external_essl3 support")
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

intel/nir: Add a memory barrier before barrier()

Our barrier instruction does not implicitly do a memory fence but the
GLSL barrier() intrinsic is supposed to.  The easiest back-portable
solution is to just add the NIR barriers.  We'll sort this out more
properly in later commits.

Cc: mesa-stable@lists.freedesktop.org
Closes: #2138
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

radv: Emit a BATCH_BREAK when changing pixel shaders or CB_TARGET_MASK.

Fixes a hang on Raven with Resident Evil 2.

I did not find anything more restricted to fix it:

- Setting persistent_states_per_bin to 1 fixes it too,
  but likely does an internal break on any descriptor set changes
  too.
- Only breaking the batch when cb_target_mask changes does not fix
  it (and looking at AMDVLK comments, I suspect the code in radeonsi
  should really be doing a FLUSH_DFSM).
- Always doing a FLUSH_DFSM on shader switch helps, but that is more
  often than this and I don't think we should be doing that when DFSM
  is disabled.
- Also emitting the existing break on framebuffer change when DFSM is
  disabled does not fix the issue.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2315
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa/st/i965: add a ProgramResourceHash for quicker resource lookup

Many resource APIs require searching by name, add a hash table to make
this faster. Currently we traverse the whole resource list for name
based queries, this change makes all these cases use the hash.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2203
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3254>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3254>

gitlab-ci: Test against LLVM / clang 9 on x86

They're not available for Debian buster yet, so we have to use upstream
snapshot packages again.

In contrast to earlier, we now store the LLVM APT repository key in Git
instead of re-downloading it every time.

panfrost: Don't double-flip Z/W for 2D arrays

We need to mindful that we don't clobber the shadow comparator.

Fixes dEQP-GLES3.functional.shaders.texture_functions.texture.sampler2darrayshadow_*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

pan/midgard: Account for z/w flip in texelFetch

Required for proper txf of 2D arrays.

Fixes dEQP-GLES3.functional.shaders.texture_functions.texelfetch.*2darray*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

panfrost: Adjust for mismatch between hardware/Gallium in arrays/cube

The hardware separates face selection and array indexing, it looks like,
whereas Gallium smushes them together with some modulus fun. Let's fix
it so mipmapped 2D arrays work without regressing cubemaps.

Fixes dEQP-GLES3.functional.texture.filtering.2d_array.* among others.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

panfrost: Respect constant buffer_offset

Fixes dEQP-GLES3.functional.ubo.multi_basic_types.single_buffer.* among
others

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

glsl: use nir version of check_image_resources() for nir linker

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

glsl: add check_image_resources() for the nir linker

This is adapted from the GLSL IR code but doesn't need to
iterate over the IR. I believe this also fixes a potential bug in
the GLSL IR code which potentially counts the same output twice.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

glsl: use nir linker to link atomics

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

mesa: add new UseNIRGLSLLinker constant

This will be used to disable some GLSL IR passes in following
patches.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

glsl: reorder link_and_validate_uniforms() calls

This is required for the following commit.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

glsl: add new gl_nir_link_glsl() helper

This will allow us to do some linking in NIR that was previously
done by the GLSL IR linker. To start with this just has calls for
linking atomics.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

glsl: add gl_nir_link_check_atomic_counter_resources()

This is pretty much a copy of link_check_atomic_counter_resources()
updated to work with the NIR linker.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

glsl: rename gl_nir_link() to gl_nir_link_spirv()

A NIR based glsl linking function will be too different to the
spirv version to bother attempting any sharing. So lets change
the name to be explicit.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

st/mesa: Lower vars to ssa and constant prop before gl_nir_lower_buffers

The gl_nir_lower_buffers pass relies on recognizing the same literal
constants as the GLSL compiler so that constant buffer array indices
are constant in nir as well.  Without this, get_block_array_index()
would see

  vec1 32 ssa_723 = deref_var &const_temp@1 (function_temp int)
  vec1 32 ssa_724 = load_const (0x00000001 /* 0.000000 */)
  ...
  vec1 32 ssa_5 = deref_var &const_temp@1 (function_temp int)
  vec1 32 ssa_6 = intrinsic load_deref (ssa_5) (0) /* access=0 */
  vec1 32 ssa_7 = deref_var &blockB (ssbo BlockB[1])
  vec1 32 ssa_8 = deref_array &(*ssa_7)[ssa_6] (ssbo BlockB) /* &blockB[ssa_6] */

instead of a literal 1, and ultimately generate the block name
BlockB[0].  That used to work, since we before the previous commits
we'd compact the block binding points and names. Thus, there would
always be a BlockB[0].

Now, if an entry in a block array isn't used, we don't generate that
block name, which means that if entry 0 isn't used BlockB[0] isn't
present and then get_block_array_index() fails to find the block.

In most cases we would have dealt with this in the call to
st_nir_opts() in st_nir_link_shaders(), but in the num_shaders == 1
case (for example, compute) we would call gl_nir_lower_buffers()
before we lowered GLSL constants.  Move that corner case up next to
where we call st_nir_link_shaders() so we call st_nir_opts() at the
same point in the flow for all shaders.

Fixes: dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.18
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl/nir: do not change an element index to have correct block name

When SSBO array is used with packed layout, both IR tree
and as a result, NIR tree will be incorrect.
In fact, the SSBO dereference indices won't
match the array size in some cases like the following:

"layout(packed, binding=1) buffer SSBO { vec4 a; } ssbo[3];
 out vec4 color;
 void main() {
   color = ssbo[2].a;
 }"

After linking the IR and then NIR will have an SSBO array
definition with size 1 but dereference still will have index 2
and linked_shader->Program->sh.ShaderStorageBlocks
will contain just SSBO with name "SSBO[2]"

So this line should be removed at least as a workaround for now
to avoid error like:
Failed to find the block by name "SSBO[0]"

Fixes: 810dde2a "glsl/nir: Add a pass to lower UBO and SSBO access"
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

glsl: fix a binding points assignment for ssbo/ubo arrays

This is needed to be in agreement with spec requirements:
https://github.com/KhronosGroup/OpenGL-API/issues/46

Piers Daniell:
   "We discussed this in the OpenGL/ES working group meeting
    and agreed that eliminating unused elements from the interface
    block array is not desirable. There is no statement in the spec
    that this takes place and it would be highly implementation
    dependent if it happens. If the application has an "interface"
    in the shader they need to match up with the API it would be
    quite confusing to have the binding point get compacted.
    So the answer is no, the binding points aren't affected by
    unused elements in the interface block array."

v2: - 'original_dim_size' field moved above to keep
      the struct packed better on 64-bit
    - added a comment for 'total_num_array_elements' field
    - fixed a binding point calculations for SSBOs array of arrays
          ( Ian Romanick <ian.d.romanick@intel.com> )
    - fixed binding point calculations for non-packed SSBOs
v3:
    - rename 'total_num_array_elements' to 'aoa_size'
          ( Jason Ekstrand <jason@jlekstrand.net> )
    - rename 'boffset' to 'binding_stride'
          ( Alejandro Piñeiro <apinheiro@igalia.com> )

Fixes: 8cf1333b "glsl: link uniform block arrays of arrays"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109532
Reported-By: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Fritz Koenig <frkoenig@google.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

glsl: fix an incorrect max_array_access after optimization of ssbo/ubo

This is needed to fix these tests:
piglit.spec.arb_shader_storage_buffer_object.compiler.unused-array-element_frag
piglit.spec.arb_shader_storage_buffer_object.compiler.unused-array-element_comp

Fixes: 8cf1333b "glsl: link uniform block arrays of arrays"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109532
Reported-By: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Fritz Koenig <frkoenig@google.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

radeonsi: remove TGSI

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: disable SDMA on gfx8 to fix corruption on RX 580

Closes: #1399
Closes: #1889
Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>

radeonsi: move SI and CIK+ SDMA code into 1 common function for cleanups

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>

radeonsi: rename dma_cs -> sdma_cs

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>

radeonsi: add AMD_DEBUG=nodmacopyimage for debugging

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>

radeonsi: add AMD_DEBUG=nodmaclear for debugging

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>

radeonsi: remove broken and unused SI SDMA image copy code

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>

radeonsi: rename SDMA debug flags

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>

gitlab-ci: Switch LAVA jobs to use shared dEQP runner

Take one step towards sharing code between the LAVA and non-LAVA jobs,
with the goals of reducing maintenance burden and use of computational
resources.

The env var DEQP_NO_SAVE_RESULTS allows us to skip the procesing of the
XML result files, which can take a long time and is not useful in the
LAVA case as we are not uploading artifacts anywhere at the moment.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

gitlab-ci: Update kernel for LAVA to 5.5-rc1 plus fixes

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

panfrost: Handle PIPE_FORMAT_R10G10B10A2_USCALED

Same format code as UINT... might be different in how it's fed into a
shader but we'll deal with that when we get there.

Fixes dEQP-GLES3.functional.vertex_arrays.single_attribute.output_types.usigned_int2_10_10_10.components4_vec2_quads1

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

panfrost: Report MSAA 4x supported for dEQP

Fixes dEQP-GLES3.functional.state_query.integers.max_samples_getinteger64

We'll have to actually implement multisampling next, but hey.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

panfrost: Cleanup tiling selection logic

Make it a lot more obvious what we're doing and fix more than a few
corner cases in the process.

Fixes
dEQP-GLES3.functional.buffer.map.write.render_as_index_array.pixel*, and
likely others.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

panfrost: Implement sRGB blend shaders

We use the lowering in nir_format_convert. There are native ops for this
so this is far from optimal and not remotely efficient but as with most
blend shader things right now, it's hard enough to get it working, so
let's focus on that for now. We'll make it fast later (once we have
GLES3 stable, we can start optimizing these things).

Fixes dEQP-GLES3.functional.fragment_ops.blend.fbo_srgb.*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

panfrost: Support rendering to non-zero Z/S layers

Fixes abort in STK's shadow implementation.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

panfrost: Texture from Z32F_S8 as R32F

Z32F_S8 becomes Z32F in texturing, which in turn just becomes R32F.

Fixes dEQP-GLES3.functional.texture.format.sized.*.depth32f_stencil8*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

iris/query: Implement PIPE_QUERY_GPU_FINISHED

Implementation is similar to radeonsi in 5f1cef76

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

st/mesa: use uint-samplers for sampling stencil buffers

Otherwise, we end up mismatching the sampler types when rendering.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/surface: use uint16_t for mipmap level pitches

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

etnaviv: fix incorrectly failing vertex size assert

Changes the assert to match the comment above.

This assert was failing in some cases while running darkplaces.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

lima: fix PP stream terminator size

PP stream terminator size seems to be 4 words, it worked with full PP
stream because we align stream beginning to 32 bytes and BO is
initialized with zeroes. But with partial PP stream it sometimes break
if for new PP stream we reuse BO that has non-zero value at this place.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

lima: don't reload and redraw tiles that were not updated

We don't need to reload and redraw some tiles if framebuffer was not
cleared and scissor test was enabled for some of draws. This simple
optimization fixes cursor lag in X11

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

lima: postpone PP stream generation

This commit postpones PP stream generation till job is submitted.
Doing that this late allows us to skip reloading and redrawing tiles
that were not updated.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

lima/parser: Fix VS cmd stream parser

prefetch is int, not bool.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>

lima/parser: Fix rsw parser

Drop assert as it is not necessary and used wrong anyway.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>

anv: Only enable EWA LOD algorithm when doing anisotropic filtering.

Updated documentation renames "Anisotropic Algorithm" to "LOD Algorithm"
and adds a note for Gen9+ saying "The EWA Algorithm should only be
enabled for Anisotropic Filtering modes." and indicating that the extra
accuracy shouldn't be necessary for other modes, and comes at a cost.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

iris: Allow HiZ for copy_region sources

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Allow HiZ for glCopyImageSubData sources

v2 (Ken): Handle platforms without sampler support for HiZ

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> [v2 changes]

anv: Allow HiZ in TRANSFER_SRC_OPTIMAL on Gen8-9

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/blorp: Use the source format when using blorp_copy with HiZ

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp: Don't resolve HiZ unless we're reinterpreting

This eliminates 50% of pixels (2M) rendered for a blit in GS:GO.  This
accounts for 3% of pixels rendered in the game.  Total GPU clocks for
the first 900 frames of CSGO improves by 1%.

Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

blorp: Allow reading with HiZ

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

blorp: Stop whacking Z24 depth to BGRA8

The shader code required to do this is int(sat(x) * UINT24_MAX) which
isn't really worth all the effort to avoid.  Doing the format
conversion, on the other hand, prevents us from sampling with HiZ which
is something that we very much want on gen8-9 where we can.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

etnaviv: move descriptor based texture structs

This moves the descriptor based texture structs and their helpers
into the only user.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>

etnaviv: move state based texture structs

This moves the state based texture structs and their helpers
into the only user.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>

panfrost: Fix Android build

Include missing `encoder/pan_props.c` into the build.

Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

mesa/st: glsl_to_nir: don't lower atomics to SSBOs if driver supports HW atomics

At least on r600 HW atomic operations are way less expensive than SSBO atomic
operations.

v2: use st->has_hw_atomics (Erik Anholt)

v3: remove second invocation of atomic to ssbo lowering (Erik Anholt)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>

r600: Delete vertex buffer only if there is actually a shader state

Fixes: gl-2.0-vertexattribpointer
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>

r600: Make SID and unsigned value

The value is never negative, and makeing it unsigned fixes some
warnings

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>

r600: Fix maximum line width

There are only 13 bits available to store the line width, hence
it can't be larger than 8191

v2: Add Fixes tag

v3: - Unify value since for all r600 archs (Konstantin Kharlamov)
    - Correct the value the line width value is emitted as a 12.4
      fixed point value of 1/2 line width on r600-r700 and as
      8 * line width on Evergreen and newer.

Fixes: 06bfb2d28f7adca7edc6be9c210a7a3583023652
    r600: fork and import gallium/radeon

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>

r600/sb: Correct SB disassambler for better debugging

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>

r600: Make it possible to include r600_asm.h in a C++ file

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>

r600: Add functions to dump the shader info

This will be helpful to compare TGSI and NIR code path,

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>

gallium: tgsi_from_mesa - handle VARYING_SLOT_FACE

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>

nir: make nir_get_texture_size/lod available outside nir_lower_tex

This functions can be useful in other places.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>

gallium/tgsi_from_mesa: Add 'extern "C"' to be able to include from C++

The r600/nir backend is in C++ and needs to include this file.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>

spirv: Fix glsl type assert in spir2nir.

Fixes: 624789e3708 "compiler/glsl: handle case where we have multiple users for types"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

etnaviv: use a better name for FE_VERTEX_STREAM_UNK14680

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>

radv: Only use the gfx mipmap level offset/pitch for linear textures.

The tiled-case is non-sensical for non-base mips, but Vulkan requires
that this function handles it but at the same time does not require
returning anything useful. So we can basically return anything.

Correct tiled pitch and offset are still required for our own WSI and
in the future getting the layouts of images with DRM format modifiers.
Both don't have to deal with images with more than 1 level though.

Fixes: 824bd0830e8 "radv: return the correct pitch for linear mipmaps on GFX10"
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2301
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2304
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

Revert "amd/common: Always initialize gfx9 mipmap offset/pitch."

This reverts commit 973181c06cca3fe232c3a435abde31f2fc1b81ef.

Requested by Marek.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

iris: Delete remnants of the unimplemented ASTC 5x5 workaround

I copy and pasted some of the boilerplate but never the implementation.
For now, ASTC 5x5 is disabled and faked via uncompressed RGBA; let's
delete these remnants until such a time when we implement it properly.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

iris: Disable ASTC 5x5 support on Gen9 for now.

Intel Gen9 hardware has some nasty restrictions where ASTC 5x5 formats
and color compression can't both live in the sampler cache at the same
time.  To properly support it, we have to track which of those exist
in the cache and flush ASTC out or resolve away compression.

As far as I'm aware, very little uses ASTC 5x5 textures, so instead
of replicating all that for iris, we simply turn it off and rely on
the Gallium fallback mechanism to fake it via uncompressed RGBA.

This should avoid GPU hangs any time people use ASTC 5x5 with CCS.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

st/mesa: Allow ASTC5x5 fallbacks separately from other ASTC LDR formats.

This patch allows us to fake ASTC 5x5 specifically, while leaving the
other ASTC LDR formats with native support.  I plan to use this in iris,
at least for the time being.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>