i965/gen6 fbo: make unmatched depth/stencil configs return unsupported

(f3c886b for gen6)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6 blorp depth: calculate base surface width/height

(e3a49e1 for gen6)

This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6 depth surface: calculate minimum array element being rendered

(a23cfb8 for gen6)

In layered rendering this will be 0. Otherwise it will be the
selected slice.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6 depth surface: calculate LOD being rendered to

(08ef1dd for gen6)

This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6 depth surface: calculate depth (array size) for depth surface

(bc1acaa for gen6)

This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.

Note: Cube maps are treated as 2D arrays with 6 times as
many array elements as the cube map array would have.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6 depth surface: calculate more specific surface type

(171e633 for gen6)

This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.

Note: Cube maps are treated as 2D arrays with 6 times as
many array elements as the cube map array would have.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6_depth_state.c: Remove (gen != 6) code paths

Since this code was branched from brw_misc_state.c, it had support for
gen != 6. We can now remove this.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Split gen6 depth hiz state out from brw

We will program the gen6 hiz depth state differently to enable layered
rendering on gen6.

v2:
 * Remove unneeded gen6_emit_depthbuffer as suggested by Topi

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6: Adjust render height in errata case for MSAA

In the gen6 PRM Volume 1 Part 1: Graphics Core, Section
7.18.3.7.1 (Surface Arrays For all surfaces other than separate
stencil buffer):

 "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the
  value calculated in the equation above , for every other odd Surface
  Height starting from 1 i.e. 1,5,9,13"

Since this Qpitch errata only impacts the sampler, we have to adjust
the input for the rendering surface to achieve the same qpitch. For
the affected heights, we increment the height by 1 for the rendering
surface.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6: Add support for layered renderbuffers

Rather than pointing the surface_state directly at a single
sub-image of the texture for rendering, we now point the
surface_state at the top level of the texture, and configure
the surface_state as needed based on this.

v2:
 * Use SET_FIELD as suggested by Topi
 * Simplify min_array_element assignment as suggested by Topi
v3:
 * Use irb->layer_count for depth instead of rb->Depth
 * Make gl_target const
 * depth - 1, not depth
v4:
 * Merge in dd43900b & b875f39e fixes to prevent 3D texture piglit
   regressions

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6_surface_state.c: Remove (gen < 6) code path

Since this code was branched from brw_wm_surface_state.c, it had
support for gen < 6. We can now remove this.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Split gen6 renderbuffer surface state from gen5 and older

We will program the gen6 renderbuffer surface state differently to
enable layered rendering on gen6.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

meta: Use instanced rendering for layered clears.

Layered rendering is part of OpenGL 3.2; GL_ARB_draw_instanced is part
of OpenGL 3.1.  As such, all drivers supporting layered rendering
already support gl_InstanceID.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

mesa: Expose vbo_exec_DrawArraysInstanced as _mesa_DrawArraysInstanced.

So we can use it in meta.c.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

Revert "hud: don't overrun malloced arrays"

This reverts commit 1cfcd0164e1be7d7b05b693f60a262ad735b7565.

This seems to cause r600g lockups,
https://bugs.freedesktop.org/show_bug.cgi?id=82628

Signed-off-by: Dave Airlie <airlied@redhat.com>

i965: Guard access to gl_Layer by extension #ifdef

Only assign gl_Layer if we have GL_AMD_vertex_shader_layer.  Gen6 doesn't
(currently) have that extension, but it also doesn't support layered
rendering.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Jordan Justen <jordan.l.justen@intel.com>

gallium/vc4: PIPE_CAP_VIDEO_MEMORY return the amount of system ram

Suggested-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

vc4: Add support for blending.

Passes blendminmax and blendsquare.  glean's more serious blendFunc fails
in simulation due to binner memory overflow (I really need to work around
that), and fbo-blending-formats fails due to Mesa refusing one of the
getter requests, even before it could fail due to the driver not actually
supporting different formats yet.

vc4: Drop incorrect attempt to incorrectly invert the primconvert hw_mask.

The hw_mask is the set of primitives you actually support, so this attempt
to provide the set of formats that's unsupported was wrong in two ways (it
was intended to be '~' not '!').  However, we only call this code when
prim isn't one of the actually supported hw_mask bits, so missing out on
the memcpy didn't matter anyway.

vc4: Use cl_f() instead of cl_u32(fui())

vc4: Consistently use qir_uniform_f().

vc4: Consume the implicit varyings for points and lines.

We were triggering simulator assertion failures for not consuming these,
and presumably we want to actually make use of them some day (for things
like point/line antialiasing)

Note that this has the qreg index as 0, which is the same index as the
first GL varyings read.  This doesn't matter currently, since that number
isn't used for anything except dumping.

vc4: Move the deref of the color buffer for simulator into the simulator.

At some point I'm going to want to move the information necessary for the
host buffer upload/download into the BO so that it's independent of the
current vc4->framebuffer, but for now this fixes pointless derefs on
non-simulator in vc4_context.c since the dump_fbo() removal

i965: Implement fast color clears using meta operations

This patch uses the infrastructure put in place by previous patches
to implement fast color clears and replicated color clears in terms of
meta operations.

This works all the way back to gen7 where fast clear was introduced and
adds support for fast clear on gen8.  It replaces the blorp path
completely and improves on a few cases.  Layered clears are now done
using instanced rendering and multiple render-target clears use a
MRT shader with rep16 writes.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add optimization pass to let us use the replicate data message

The data port has a SIMD16 'replicate data' message, which lets us write
the same color for all 16 pixels by sending the four floats in the
lower half of a register instead of sending 4 times 16 identical
component values in 8 registers.

The message comes with a lot of restrictions and could be made generally
useful by recognizing when those restriction are satisfied.  For now,
this lets us enable the optimization when we know it's safe, but we don't
enable it by default.  The optimization works for simple color clear shaders
only, but does recognized and support multiple render targets.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

meta: Export _mesa_meta_drawbuffers_from_bitfield()

We'll use this in the i965 fast clear implementation.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

mesa: Use _mesa_lock_context_textures in _mesa_GetTexParameterfv()

GetTexParamterfv() doesnt change texture state, so instead of
_mesa_lock_texture() we can use _mesa_lock_context_textures(),
which doesn't increase the texture stamp.  With this change,
_mesa_update_state_locked() is now only called from under
_mesa_lock_context_textures(), which is right thing to do.  Right now
it's the same mutex, but if we made texture locking more fine grained
locking one day, just locking one texture here would be wrong.

This all ignores the fact that texture locking seem a bit
flaky and broken, but we're trying to not blatantly make it worse.

This change allows us to reliably unlock the context textures in the
dd::UpdateState callback as is necessary for meta color resolves.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Move pre-draw resolve buffers to dd::UpdateState

No functional change except for glBegin/glEnd style rendering, where we now
do the resolves at glBegin time instead of FLUSH_VERTICES time.  This is also
the reason for this change, so that when we later switch fast clear resolve to
use meta, we won't be doing meta operations in the middle of a begin/end
sequence.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Provide a context flag to let us enable fast clear

GEN7+ has the fast clear functionality, which lets us clear the color
buffers using the MCS and a scaled down rectangle.  To enable this
we have to set the appropriate bits in the 3DSTATE_PS package.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Disable clipping when rendering 3DPRIM_RECTLIST primitives

The clipper doesn't support clipping 3DPRIM_RECTLIST primitives and must
be turned off when we use them.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add a mechanism for sending native primitives into the driver

The brw_draw_prims() function is the draw entry point into the driver,
and takes struct _mesa_prim for input.  We want to be able to feed
native primitives into the driver, and to that end we introduce
BRW_PRIM_OFFSET, which lets use describe geometry using the native
GEN primitive types.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add context flag to disable the viewport transform

This lets us disable the viewport transform, which will be useful for
emitting 3DPRIM_RECTLIST.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add an option to not generate the SIMD8 fragment shader

For now, this can only be triggered with a new 'no8' INTEL_DEBUG option
and a new context flag.  We'll use the context flag later, but introducing
it now lets us bisect to this commit if it breaks something.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

docs/autoconf: explicitly mention PKG_CONFIG_PATH for cross/multilib builds

... and squash a couple of typos.

Suggested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

st/dri: Add __DRI2rendererQueryExtension support

The final step to get GLX_MESA_query_renderer working with gallium
drivers.

v2: Remove __DRI2_RENDERER_PREFERRED_PROFILE handling. It's already
handled in dri/common. Spotted by Marek.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/softpipe/llvmpipe: handle query_renderer caps

Both report 0xffffffff as both vendor and device id, and the maximum
amount of system memory as video memory.

v2: Use aux helper os_get_total_physical_memory().

Cc: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

gallium/svga: handle query_rendered caps

All the values are are currently hardcoded. One could use
some heuristics to determine the amount of video memory if
a callback to the host is not available.

Do we what to advertise the driver as hardwar accelerated ?

Cc: Brian Paul <brianp@vmware.com>
Cc: José Fonseca <jose.r.fonseca@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

gallium/nouveau: handle query_renderer caps

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

gallium/vc4: handle query_renderer caps

Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

gallium/r300/r600/radeonsi: handle query_renderer caps

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/ilo: handle query_renderer caps

Implementation based on the classic driver with the following
changes:
 - Use auxiliarry function os_get_total_physical_memory to get the
total amount of memory.
 - Move the libdrm_intel specific get_aperture_size to the winsys.

Cc: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

gallium/i915: handle query_renderer caps

Implementation based on the classic driver with the following
changes:
 - Use auxiliarry function os_get_total_physical_memory to get the
total amount of memory.
 - Move the libdrm_intel specific get_aperture_size to the winsys.

Cc: Stephane Marchesin <stephane.marchesin@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

gallium/freedreno: handle query_renderer caps

Provide the real vendor and and hardcode the device id as
0xffffffff as the devices currently using freedreno are non-pci.
The device features UMA.

Cc: Rob Clark <robclark@freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>

auxiliary/os: introduce os_get_total_physical_memory helper function

Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

gallium: add GLX_MESA_query_renderer caps

Namely vendor/device id, accelerated and UMA, which will be used to describe
the underlying renderer.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

dri/swrast: add GLX_MESA_query_renderer support

v2:
 - Drop __DRI2_RENDERER_PREFERRED_PROFILE case.
 - Cleanup return statements.

Cc: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

dri/radeon: add GLX_MESA_query_renderer support

 - Create radeon{Vendor,GetRenderer}String helpers.
 - Drop __DRI2_RENDERER_PREFERRED_PROFILE case.
 - Cleanup return statements.

To be used by the upcomming GLX_MESA_query_renderer implementation.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

dri/radeon: don't print TCL status on glGetString(GL_RENDERER)

Printing the TCL involves that context is available at the time of
query. The GLX_MESA_query_renderer states that glGetString(GL_RENDERER)
and glXQueryRendererStringMESA(GLX_RENDERER_DEVICE_ID_MESA) will have
the same format, thus removing the context dependenicy will help us
achieve that.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

dri/nouveau: add GLX_MESA_query_renderer support

 - Create nouveau_{vendor,get_renderer}_string helpers.
 - Set correct max_gl*version.
 - Query the device PCIID via libdrm_nouveau/nouveau_getparam.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

dri/common: Move __DRI2_RENDERER_PREFFERED_PROFILE handling to driQueryRendererIntegerCommon

Essentially all drivers would like to use to opengl core profile if
available, so avoid duplication by moving the code to a common fallback
within driQueryRendererIntegerCommon.

If a driver uses different approach they can handle it separately.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

glx/drisw: add support for DRI2rendererQueryExtension

The extension is used by GLX_MESA_query_renderer, which
can be provided for by hardware and software drivers.

v2: Use designated initializers.
v3: Move drisw_query_renderer_*() to dri2_query_renderer.c

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

glx/dri2: use mapping table for dri2_convert_glx_query_renderer_attribs()

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

glx/drisw: Move private structure declarations to a header file

v2: Reff the correct file wrt copyright, spotted by Chia-I

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

mesa: check if GL_ARB_copy_image is enabled in _mesa_CopyImageSubData()

Generate a GL error and return rather than crashing on a null
ctx->Driver.CopyImageSubData pointer (gallium).  This allows apitraces
with glCopyImageSubData() calls to continue rather than crash.

Plus, fix a comment typo.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/blorp_clear: Use memcpy instead of assignment to copy clear value

Similar to the problem described in 2c50212b14da27de4e3, if we copy the clear
value through a regular assignment via a floating point value, then if an
integer clear value is being used that happens to contain a signalling NaN
value then it would get converted to a quiet NaN when stored via the x87
floating-point registers. This would corrupt the integer value. Instead we
should use a memcpy to ensure the exact bit representation is preserved.

This bug can be triggered on 32-bit builds with optimisations by using an
integer clear color with a value like 0x7f817f81.

Reviewed-by: Matt Turner <mattst88@gmail.com>

r600g: Implement ARB_derivative_control

Requires Evergreen/Cayman

marek: update release notes

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

docs: Update relnotes for ARB_gpu_shader5

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>

docs: Mark off ARB_gpu_shader5 for i965

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Enable ARB_gpu_shader5 on Gen7

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Add support for nonconst sampler indexing in FS visitor

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Add support for non-const sampler indices in generator

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Refactor generate_tex in prep for nonconst sampler indexing

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Use brw_adjust_sampler_state_pointer in fs generator too

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Add support for nonconst sampler indexing in VS visitor

V2: Set force_writemask_all on ADD; this *is* necessary in the VS case
too.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Add support for non-const sampler indices in generator

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Generalize sampler state pointer mangling for non-const

For now, assume that the addressed sampler can be in any of the
16-sampler banks. If we preserved range information this far, we
could avoid emitting these instructions if the sampler were known
to be contained within one bank.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Refactor generate_tex in prep for non-const samplers

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Extract helper function for surface state pointer adjustment

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

docs: Mark off ARB_gpu_shader5 UBO array indexing for i965

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

i965/vec4: Add visitor support for nonconst ubo block indexing

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

i965/vec4: Generate indirect sends for nonconstant UBO array access

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

i965/fs: Add visitor support for nonconstant UBO indices

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

i965/fs: Generate indirect sends for nonconstant UBO array accesses

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Adjust set_message_descriptor to handle non-sends

We're about to be using this infrastructure to build descriptors in
src1 of non-send instructions, when preparing to do an indirect send.

Don't accidentally clobber the conditionalmod field of those
instructions with SFID bits, which aren't part of the descriptor.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Add low-level support for indirect sends

This provides a reasonable place to enforce the hardware restriction
that indirect descriptors must be in a0.0

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

i965/fs: Add pass to rename registers to break live ranges.

The pass breaks live ranges of virtual registers by allocating new
registers when it sees an assignment to a virtual GRF it's already seen
written.

total instructions in shared programs: 4337879 -> 4335014 (-0.07%)
instructions in affected programs:     343865 -> 341000 (-0.83%)
GAINED:                                46
LOST:                                  1

[mattst88]: Make pass not break in presence of control flow.
            invalidate_live_intervals() only if progress.
            Fix up delta_x/delta_y.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

i965: Fix INTDIV math assertions on Broadwell.

Commit c66d928f2c9fa59e162c391fbdd37df969959718 ("i965: Enable INTDIV
in SIMD16 mode.") began using generate_math_gen6 to break SIMD16 INTDIV
into two SIMD8 operations.

generate_math_gen6 takes two registers - for unary operations, we pass
ARF null for the second operand.  Prior to Broadwell, real operands were
always GRF.  But now they can be IMM as well.

So, check for != ARF instead of == GRF.

+12 piglits.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

Revert "i965/vec4: Use MOV, not OR, to set URB write channel mask bits."

This reverts commit af13cf609f4257768ad8b80be8cec7f2e6ca8c81, which
appears to cause huge performance problems on Ivybridge.  I'd missed
that the FFTID bits are in the low byte.  The documentation doesn't
indicate that the URB write message header actually wants FFTID - it
just labels those bits as "Reserved."  But it appears necessary.

This does slightly more than revert the original change: originally,
Broadwell had separate code generation, which used MOV, and this patch
only changed it for Gen4-7.  Now that both are unified, reverting this
also makes Broadwell use OR.  Which should be fine.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

docs: Mark off ARB_derivative_control for i965.

Also update 10.3 relnotes to match.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Enable ARB_derivative_control on Gen7+.

The extension says GL 4.0 is required. We'll meet the spirit
of that restriction by enabling on just those generations which will
soon support GL 4.0 (Gen7+), although it's technically supportable on
all generations.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Support fine/coarse derivative opcodes

The quality level (fine/coarse/dont-care) is plumbed through to the
generator as a constant in src1.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Assert that fine/coarse derivative ops don't appear

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Mark program as using dFdy if coarse/fine variant is used

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nv50,nvc0: add support for fine derivatives

The quadop-based method we currently use on all chipsets already
provides the fine version of the derivatives.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa/st: add support for emitting fine derivative opcodes

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: add opcodes/cap for fine derivative support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
v2: Reuse opcode gaps as suggested by Marek

mesa/program: add new derivative unops to the unexpected list

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

glsl: add ARB_derivative control support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: add ARB_derivative_control extension bit

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: add ARB_texture_barrier support

This extension is identical to NV_texture_barrier. Alias
glTextureBarrier to the existing glTextureBarrierNV and use the existing
NV_texture_barrier extension bit.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

docs: document radeonsi BPTC support, sort extensions in 10.3 release notes

r600g: Implement BPTC texture support

Requires Evergreen/Cayman

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

i965: Rename intelValidateState to intel_update_state

This matches the name of the dd hook.  Also convert a couple of nearby
dd implementations to lowercase + underscore as is now the standard.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Assign PS kernel start pointers when we decide which kernels to use

Right now we decide which kernels to use and the GRF start offsets in
one place and emit the kernel pointers later.  The logic of how to map
8, 16 and 32 kernels to kernel start pointers follows the same logic as which
GRF start offsets to use, so lets figure out these two things in one place.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

radeonsi: implement BPTC texture support

Passes all piglit tests.

v2: rebased

Signed-off-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: fix buffer invalidation of unbound texture buffer objects

This maintains a list of all TBOs in a pipe_context.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: implement invalidation of texture buffer objects

This fixes piglit spec/ARB_texture_buffer_object/data-sync.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: fix constant buffer fetches

Somebody forgot to do this. It was uncovered by recent st/mesa changes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82139

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>

r600g: clear constant buffer sizes at the beginning of CS

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

egl_dri2: fix EXT_image_dma_buf_import fds

The EGL_EXT_image_dma_buf_import specification was revised (according to
its revision history) on Dec 5th, 2013, for EGL to not take ownership of
the file descriptors.

Do not close the file descriptors passed in to eglCreateImageKHR with
EGL_LINUX_DMA_BUF_EXT target.

It is assumed, that the drivers, which ultimately process the file
descriptors, do not close or modify them in any way either. This avoids
the need to dup(), as it seems we would only need to just close the
dup'd file descriptors right after.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76188
Signed-off-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>