amdgpu/addrlib: rename ComputeSurfaceThickness to Thickness

amdgpu/addrlib: add define HAVE_TSERVER

amdgpu/addrlib: Add new interface to support macro mode index query

amdgpu/addrlib: add explicit Log2NonPow2 function

amdgpu/addrlib: Fix invalid access to m_tileTable

Sometimes client driver passes valid tile info into address library,
in this case, the tile index is computed in function
HwlPostCheckTileIndex instead of CiAddrLib::HwlSetupTileCfg.
We need to call HwlPostCheckTileIndex to calculate the correct tile
index to get tile split bytes for this case.

amdgpu/addrlib: add ADDR_ANALYSIS_ASSUME

It helps fix analysis warnings in MSC.

amdgpu/addrlib: add tcCompatible htile addr from coordinate support.

amdgpu/addrlib: force all zero tile info for linear general.

amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex and AddrConvertTileInfoToHW

When clients queries tile Info from tile index and expects accurate
tileSplit info,  bits per pixel info is required to be provided since
this is necessary for computing tileSplitBytes; otherwise Addrlib will
return value of "tileBytes" instead if bpp is 0 - which is also
current logic. If clients don't need tileSplit info, it's OK to pass
bpp with value 0.

amdgpu/addrlib: Refine the PRT tile mode selection

Switch the tile index based on logic instead of hardcoded threshold
for different ASIC.

amdgpu/addrlib: add dccRamSizeAligned output flag

This flag indicates to the client if this level's DCC memory is aligned
or not. No aligned means there are padding to the end.

amdgpu/addrlib: Change comment alignment

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amdgpu/addrlib: style changes and minor cleanups

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amdgpu/addrlib: AddrLib inheritance refactor

Add one more abstraction layer into inheritance system.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amdgpu/addrlib: rearrange code in preparation of refactoring

No code changes.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amdgpu/addrlib: add disableLinearOpt flag

amdgpu/addrlib: Add GetMaxAlignments

amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding path

Kaveri (2-pipe) macro tiling mode table was initially set to all
4-aspect-ratio so the swizzling path did not work for it and then we
chose to pad the offset. We now discover the root cause is that if
ratio > 2, the swizzling path does not work. So we can safely use the
same path for Kaveri.

amdgpu/addrlib: Rewrite tile mode optmization code

Note: remove reference to degrade4Space and use opt4Space instead.

amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.

Even if surface info input flag "tcComaptible" is enabled, tc
compatible may be not supported if tile split happens for depth
surfaces. Add a new flag in output structure to notify client to
disable tc compatible in this case.

amdgpu/addrlib: Make comments shorter

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amdgpu/addrlib: add new flag nonSplit

Flag tcCompatible has different usage in CI and VI. Add a new flag
"nonSplit" for CI.

amdgpu/addrlib: allow tileSplitBytes greater than row size

Carrizo row size is 1K, while tileSplitBytes is 2K for a 4xAA 32bpp
depth surface. Remove the sanity check that tileSplitBytes must be
greater than row size. There could be performance loss but may be
covered by non-split depth which enables tc-compatible read.

amdgpu/addrlib: Change to compute TC compatible stencil info

Change the logic to compute tc compatible stencil info via depth's
tileIndex instead of using depth's tileInfo. So the clients can get
the stencil's tileInfo computed from macroModeTable. If the stencil
tileInfo is same as depth tileInfo, then stencil is tc compatible;
otherwise, stencil is not tc compatible. The current suggestion is to
create another stencil buffer with the tc compatible tileInfo, use
depth-to-color copy to decompress and tile convert the rendered
stencil to tc compoatible stencil (And use the new stencil buffer to
program TC).

amdgpu/addrlib: rename SiAddrLib/CiAddrLib to match internal spelling

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

configure.ac: require libdrm_amdgpu 2.4.76 for Vega

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/glsl_to_tgsi: use glsl_type::sampler_index()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

glsl: allow glsl_type::sampler_index() with images

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/mesa: improve error messages and fix security warning

Debian, Ubuntu set default build flag: -Werror=format-security

  CC       state_tracker/st_cb_texturebarrier.lo
state_tracker/st_cb_eglimage.c: In function ‘st_egl_image_get_surface’:
state_tracker/st_cb_eglimage.c:64:7: error: format not a string literal and no format arguments [-Werror=format-security]
       _mesa_error(ctx, GL_INVALID_VALUE, error);
       ^~~~~~~~~~~
state_tracker/st_cb_eglimage.c:71:7: error: format not a string literal and no format arguments [-Werror=format-security]
       _mesa_error(ctx, GL_INVALID_OPERATION, error);
       ^~~~~~~~~~~

Reported-by: Krzysztof Kolasa <kkolasa@winsoft.pl>
Fixes: 83e9de25f325 ("st/mesa: EGLImageTarget* error handling")

i965: Combine intel_batchbuffer_reloc and intel_batchbuffer_reloc64

These two functions do the exact same thing.  One returns a uint64_t,
and the other takes the same uint64_t and truncates it to a uint32_t.

We only need the uint64_t variant - the caller can truncate if it wants.
This patch gives us one function, intel_batchbuffer_reloc, that does
the 64-bit thing.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Use WARN_ONCE instead of open coding it.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

android: pass sse4.1 flag as appropriate

We have functions which depend on sse4.1 support but we didnt pass
the right compile flag for it. This patch fixes it.

Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com>
Signed-off-by: Harish Krupo <harish.krupo.kps@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

radv: fix mask attribs properly.

some days it just doesn't pay to get out of bed.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: fix regression with mask attrib setting code.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: move to using nir clip/cull merge pass.

Doing this before tessellation makes doing some bits of
tessellation a bit cleaner. It also cleans up a bit of the
llvm generator code.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

swr: [scons] Fix windows build

Fix codegen build break that was introduced earlier

v2: update rules for gen_knobs.cpp and gen_knobs.h

v3: Introduce bldroot and revert generator file changes, making patch simpler.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

anv/cmd_buffer: fix host memory leak

push_constants must be free'd.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100452
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>

mesa/glthread: fallback to sync if count validation fails

The old code would sync and then throw a cryptic error message.
There is no need for a custom error, we can just fallback to
the real function and have it do proper validation.

Fixes piglit test:
glsl-uniform-out-of-bounds

Which was returning the wrong error code.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa/glthread: add async support to glProgramUniform*() functions

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa/glthread: print out syncs when MARSHAL_MAX_CMD_SIZE is exceeded

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

anv/batch_chain: Handle another OOM in cmd_buffer_execbuf

Found by inspection while rebasing other patches.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

st/mesa: EGLImageTarget* error handling

Stop trying to specify texture or renderbuffer objects for unsupported
EGL images. Generate the error codes specified in the OES_EGL_image
extension.

EGLImageTargetTexture2D and EGLImageTargetRenderbuffer would call
the pipe driver's create_surface callback without ever checking that
the given EGL image is actually compatible with the chosen target
texture or renderbuffer. This patch adds a call to the pipe driver's
is_format_supported callback and generates an INVALID_OPERATION error
for unsupported EGL images. If the EGL image handle does not describe
a valid EGL image, an INVALID_VALUE error is generated.

v2: fixed get_surface to actually use the usage and error parameters

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/mesa: move st_manager_get_egl_image_surface into st_cb_eglimage.c

The only callers are here, and we will add generation of GL errors in
the following patch.  Rename the function to st_egl_image_get_surface,
pass the gl_context instead of st_context, and move the cast from
GLeglImageOES to void* into st_egl_image_get_surface.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

i965: expose BRW_OPCODE_[F32TO16/F16TO32] name on gen8+

Technically those hw operations are only available on gen7, as gen8+
support the conversion on the MOV. But, when using the builder to
implement nir operations (example: nir_op_fquantize2f16), it is not
needed to do the gen check. This check is done later, on the final
emission at brw_F32TO16 (brw_eu_emit), choosing between the MOV or the
specific operation accordingly.

So in the middle, during optimization phases those hw operations can
be around for gen8+ too.

Without this patch, several (at least 95) vulkan-cts quantize tests
crashes when using INTEL_DEBUG=optimizer. For example:
dEQP-VK.spirv_assembly.instruction.graphics.opquantize.too_small_vert

v2: simplify the code using GEN_GE (Ilia Mirkin)
v3: tweak brw_instruction_name instead of changing opcode_descs
    table, that is used for validation (Matt Turner)

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove dd_function_table::BindProgram

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

r200: remove BindProgram

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

i915: remove BindProgram

The same thing is done in i915_update_program called by i915InvalidateState.
Why do it twice.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: don't use _NEW_TEXTURE mainly in mesa/main

v2: add missing %s

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: split _NEW_TEXTURE into _NEW_TEXTURE_OBJECT & _NEW_TEXTURE_STATE

No performance testing has been done, because it makes sense to make this
change regardless of that. Also, _NEW_TEXTURE is still used in many places,
but the obvious occurences are replaced here.

It's now possible to split _NEW_TEXTURE_OBJECT further.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: inline _mesa_update_texture

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

appveyor: Update dependencies.

- Use explicit versions everywhere.
- Avoid deprecate `--egg` pip option.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

c11/threads: Include thr/xtimec.h for xtime definition when building with MSVC.

MSVC has been including a xtime definition in thr/xtimec.h ever since
MSVC 2013 (which is the minimum we require for building Mesa), and
including it prevents duplicate definitions when it gets included by
LLVM.

In fact, it looks that MSVC has been including a partial C11 threads
implementation too for some time, which we should consider migrating to
once we eliminate the use of _MTX_INITIALIZER_NP in our tree.

Thanks to the anonymous helper from
https://bugs.freedesktop.org/show_bug.cgi?id=100201#c4 for spotting
this.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100201
CC: "17.0" <mesa-stable@lists.freedesktop.org>

mesa: update lower_jumps tests after bug fix

This change updates the tests to reflect the IR after
the following bug fix.

Fixes: c1096b7f1d49 ("glsl: fix lower jumps for returns when loop is
                      inside an if")

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Bugzilla: https://bugs.freedesktop.org/100441

gbm/dri: Flush after unmap

Drivers may queue dma operations on the context at unmap time so we need
to flush to make sure the data gets to the bo. Ideally the application
would take care of this, but since there appears to be no exported gbm
flush functionality we need to explicitly flush at unmap time.

This fixes a problem where kmscube on vmwgfx in rgba textured mode would
render using an uninitialized texture rather than the intended
rgba pattern.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

radv: Enable sparseBinding feature.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv/amdgpu: Use reference counting for bos.

Per the Vulkan spec, memory objects may be deleted before the buffers
and images using them are deleted, although those resources then
cannot be used except for deletion themselves.

For the virtual buffers, we need to access them on resource destruction
to unmap the regions, so this results in a use-after-free. Implement
reference counting to avoid this.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Implement sparse memory binding.

v2: Only submit when semaphores are specified.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Implement sparse image creation.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Implement sparse buffer creation.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv/amdgpu: Add winsys implementation of virtual buffers.

v2: - Added comments.
    - Fixed a double unmap bug.
    - Actually unmap the non-edge old ranges.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Assert when setting 0 registers in a sequence.

To catch more of those hangs early.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Acked-by: Dave Airlie <airlied@redhat.com>

anv/cmd_buffer: Refactor flush_pipeline_select_*

While having the _3d and _gpgpu versions is nice, there's no reason why
we need to have duplicated logic for tracking the current pipeline.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv: Flush caches prior to PIPELINE_SELECT on all gens

The programming note that says we need to do this still exists in the
SkyLake PRM and, from looking at the bspec, seems like it may apply to
all hardware generations SNB+.  Unfortunately, this isn't particularly
clear cut since there is also language in the bspec that says you can
skip the flushing and stall to get better throughput.  Experimentation
with the "Car Chase" benchmark in GL seems to indicate that some form of
flushing is still needed.  This commit makes us do the full set of
flushes regardless of hardware generation.  We can always reduce the
flushing later.

Reported-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>

anv/cmd_buffer: Fix bad indentation

A bunch of code was indented in such a way that it looked like it went
with the if statement above but it definitely didn't.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>

anv/cmd_buffer: Apply flush operations prior to executing secondaries

This fixes rendering issues in the Vulkan port of skia on some hardware.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>

anv/blorp: Use anv_get_layerCount everywhere

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>

anv: Make anv_get_layerCount a macro

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>

radv: only emit ps_input_cntl is we have any to output

Otherwise we get GPU hangs.

Reported-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

glx: Remove #include <GL/glxint.h>

We're not using anything in it, and we don't want to inherit struct
definitions from some other package anyway.

Signed-off-by: Adam Jackson <ajax@redhat.com>

r600g: check NULL return from r600_aligned_buffer_create

Signed-off-by: Julien Isorce <jisorce@oblong.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st_cb_bitmap: check NULL return from u_upload_alloc

Signed-off-by: Julien Isorce <jisorce@oblong.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

si_compute: check NULL return from u_upload_alloc

Signed-off-by: Julien Isorce <jisorce@oblong.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

r600g: check NULL return from u_upload_alloc

Like done in si_state_draw.c::si_draw_vbo

u_upload_alloc can fail, i.e. set output param *ptr to NULL, for 2 reasons:
alloc fails or map fails. For both there is already a fprintf/stderr in
radeon_create_bo and radeon_bo_do_map.

In src/gallium/drivers/ it is a common usage to just avoid to crash by doing
a silent check. But defer fprintf where the error comes from, libdrm calls.

Signed-off-by: Julien Isorce <jisorce@oblong.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

swr: fix llvm-5.0.0 build bustage

Handle rename of llvm AttributeSet to AttributeList in the same
fashion as ac_llvm_helper.cpp.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer jitter] fix llvm-5.0.0 build bustage

Add CreateAlignmentAssumptionHelper to gen_llvm_ir_macros.py ignore list.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

isl: Drop unused isl_surf_init_info::min_pitch

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel: Fix requests for exact surface row pitch (v2)

All callers of isl_surf_init() that set 'min_row_pitch' wanted to
request an *exact* row pitch, as evidenced by nearby asserts, but isl
lacked API for doing so. Now that isl has an API for that, update the
code to use it.

v2: Assert that isl_surf_init() succeeds because the callers assume
    it.  [for jekstrand]

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> (v1)
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> (v1)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2)

isl: Let isl_surf_init's caller set the exact row pitch (v2)

The caller does so by setting the new field
isl_surf_init_info::row_pitch.

v2: Validate the requested row_pitch.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2)

isl: Validate the calculated row pitch (v45)

Validate that isl_surf::row_pitch fits in the below bitfields,
if applicable based on isl_surf::usage.

    RENDER_SURFACE_STATE::SurfacePitch
    RENDER_SURFACE_STATE::AuxiliarySurfacePitch
    3DSTATE_DEPTH_BUFFER::SurfacePitch
    3DSTATE_HIER_DEPTH_BUFFER::SurfacePitch

v2:
  -Add a Makefile dependency on generated header genX_bits.h.
v3:
  - Test ISL_SURF_USAGE_STORAGE_BIT too. [for jekstrand]
  - Drop explicity dependency on generated header. [for emil]
v4:
  - Rebase for new gen_bits_header.py script.
  - Replace gen_10x with gen_device_info*.
v5:
  - Drop FINISHME for validation of GEN9 1D row pitch. [for jekstrand]
  - Reformat bit tests. [for jekstrand]

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v4)

genxml: New generated header genX_bits.h (v6)

genX_bits.h contains the sizes of bitfields in genxml instructions,
structures, and registers. It also defines some functions to query those
sizes.

isl_surf_init() will use the new header to validate that requested
pitches fit in their destination bitfields.

What's currently in genX_bits.h:

  - Each CONTAINER::Field from gen*.xml that has a bitsize has a macro
    in genX_bits.h:

        #define GEN{N}_CONTAINER_Field_bits {bitsize}

  - For each set of macros whose name, after stripping the GEN prefix,
    is the same, genX_bits.h contains a query function:

      static inline uint32_t __attribute__((pure))
      CONTAINER_Field_bits(const struct gen_device_info *devinfo);

v2 (Chad Versace):
  - Parse the XML instead of scraping the generated gen*_pack.h headers.

v3 (Dylan Baker):
  - Port to Mako.

v4 (Jason Ekstrand):
  - Make the _bits functions take a gen_device_info.

v5 (Chad Versace):
  - Fix autotools out-of-tree build.
  - Fix Android build. Tested with git://github.com/android-ia/manifest.
  - Fix macro names. They were all missing the "_bits" suffix.
  - Fix macros names more. Remove all double-underscores.
  - Unindent all generated code. (It was floating in a sea of whitespace).
  - Reformat header to appear human-written not machine-generated.
  - Sort gens from high to low. Newest gens should come first because,
    when we read code, we likely want to read the gen8/9 code and ignore
    the gen4 code. So put the gen4 code at the bottom.
  - Replace 'const' attributes with 'pure', because the functions now
    have a pointer parameter.
  - Add --cpp-guard flag. Used by Android.
  - Kill class FieldCollection. After Jason's rewrite, it was just
    a dict.

v6 (Chad Versace):
  - Replace `key not in d.keys()` with `key not in d`. [for dylan]

Co-authored-by: Dylan Baker <dylan@pnwbakers.com>
Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v5)
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> (v6)

swr: [rasterizer core] Disable inline function expansion

Disable expansion in windows Debug builds.

Reviewed-by: George Kyriazis <george.kyriazis@intel.com>

swr: [rasterizer common] Use C++ thread_local keyword

Allows use of thread_local objects with constructors.

Reviewed-by: George Kyriazis <george.kyriazis@intel.com>

swr: [rasterizer core] SIMD16 Frontend WIP

Implement widened clipper and binner interfaces for SIMD16.

Reviewed-by: George Kyriazis <george.kyriazis@intel.com>

swr: [rasterizer core] Don't bind single-threaded contexts

Reviewed-by: George Kyriazis <george.kyriazis@intel.com>

swr: [rasterizer core] Enable SIMD16

Make the AVX512 insert/extract intrinsics KNL-compatible

Reviewed-by: George Kyriazis <george.kyriazis@intel.com>

swr: [rasterizer jitter] Clean up EngineBuilder construction

Reviewed-by: George Kyriazis <george.kyriazis@intel.com>

swr: [rasterizer codegen] add cmdline to archrast gen files

Reviewed-by: George Kyriazis <george.kyriazis@intel.com>

swr: [rasterizer core] SIMD16 Frontend WIP

Fix GS and streamout.

Reviewed-by: George Kyriazis <george.kyriazis@intel.com>

swr: [rasterizer codegen] Refactor codegen

Move common codegen functions into gen_common.py.

v2: change gen_knobs.py to find the template file internally, like
the rest of the gen scripts.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

tests/cache_test: allow crossing mount points

When using an overlayfs system (like a Docker container), rmrf_local()
fails because part of the files to be removed are in different mount
points (layouts). And thus cache-test fails.

Letting crossing mount points is not a big problem, specially because
this is just for a test, not to be used in real code.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

glcpp/tests/glcpp-test-cr-lf: error out if we cannot find any tests

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

glcpp/tests/glcpp-test-cr-lf: correctly set/use srcdir/abs_builddir

Otherwise manual invokation of the script from elsewhere than
`dirname $0` will fail.

With these all the artefacts should be created in the correct location,
and thus we can remove the old (and slighly strange) clean-local line.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

glcpp/tests: update testname in help string

Rather than hardcoding glcpp/other use `basename "$0"` which expands
appropriatelly.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

glcpp/tests/glcpp-test: error out if we cannot find any tests

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

glcpp/tests/glcpp-test: print only the test basename

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

glcpp/tests/glcpp-test: set srcdir/abs_builddir variables

Current definitions work fine for the manual invokation of the script,
although the whole script does not consider that one can run it OOT.

The latter will be handled with latter patches, although it will be
extensively using the two variables.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

glsl/tests/optimization-test: 'echo' only folders which has generators

The current "let's print any folder which exists" is simply confusing.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

glsl/tests/optimization-test: print only the test basedir/name

The relative/absolute path brings little to no benefit in being printed
as testname. Trim it out.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

glsl/tests/optimization-test: error if zero tests were executed

We don't want to lie ourselves that 'everything is fine' when no tests
were found/ran.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

glsl/tests/optimization-test: pass glsl_test as argument

Rather than hardcoding the binary location (which ends up wrong in a
number of occasions) in the python script, pass it as argument.

This allows us to remove a couple of dirname/basename workarounds that
aimed to keep this working, and succeeded in the odd occasion.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>