st/program: add support for gs/tes/tcs nir shaders.

This probably needs more work but this just add the initial
code to convert gs/tcs/tes nir based shaders in the state tracker.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

st/program: rework basic variant interface

This just passes st_common_program and uses it.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

anv/entrypoints: Dump useful data if mako throws an exception

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

nir/opt_intrinsics: Rework progress

This commit fixes two issues:  First, we were returning false regardless
of whether or not the function made progress.  Second, we were calling
nir_metadata_preserve far more often than needed; we only need to call
it once per impl.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/compiler: Call nir_lower_system_values in brw_preprocess_nir

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

i965/program: Move nir_lower_system_values higher up

We want this to get called before nir_lower_subgroups which is going in
brw_preprocess_nir.  Now that nir_lower_wpos_ytransform can handle
system values, this should be safe to do.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

nir/lower_wpos_ytransform: Support system value intrinsics

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/pipeline: Call nir_lower_system_valaues after brw_preprocess_nir

We currently have a bug where nir_lower_system_values gets called before
nir_lower_var_copies so it will miss any system value uses which come
from a copy_var intrinsic.  Moving it to after brw_preprocess_nir fixes
this problem.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org

anv/pipeline: Drop nir_lower_clip_cull_distance_arrays

We already handle it in brw_preprocess_nir

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/pipeline: Dump shader immedately after spirv_to_nir

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/eu: Use EXECUTE_1 for JMPI

The PRM says "The execution size must be 1."  In 73137997e23ff6c11, the
execution size was set to 1 when it should have been BRW_EXECUTE_1
(which maps to 0).  Later, in dc2d3a7f5c217a7cee9, JMPI was used for
line AA on gen6 and earlier and we started manually stomping the
exeution size to BRW_EXECUTE_1 in the generator.  This commit fixes the
original bug and makes brw_JMPI just do the right thing.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 73137997e23ff6c1145d036315d1a9ad96651281

i965/fs: Add brw_reg_type_from_bit_size utility method

Returns the brw_type for a given ssa.bit_size, and a reference type.
So if bit_size is 64, and the reference type is BRW_REGISTER_TYPE_F,
it returns BRW_REGISTER_TYPE_DF. The same applies if bit_size is 32
and reference type is BRW_REGISTER_TYPE_HF it returns BRW_REGISTER_TYPE_F

v2 (Jason Ekstrand):
 - Use better unreachable() messages
 - Add Q types

Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/fs/nir: Use the nir_src_bit_size helper

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/fs: Handle flag read/write aliasing in needs_src_copy

In order to implement the ballot intrinsic, we do a MOV from flag
register to some GRF.  If that GRF is used in a SEL, cmod propagation
helpfully changes it into a MOV from the flag register with a cmod.
This is perfectly valid but when lower_simd_width comes along, it simply
splits into two instructions which both have conditional modifiers.
This is a problem since we're reading the flag register.  This commit
makes us check whether or not flags_written() overlaps with the flag
values that we are reading via the instruction source and, if we have
any interference, will force us to emit a copy of the source.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org

clover: Fix compilation after clang r315871

v2: use a more generic compat function
v3: rename and formatting cleanup

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103388
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
CC: <mesa-stable@lists.freedesktop.org>

glsl_to_tgsi: remove unused glsl_version variable

trivial

radv: Compute ac keys from pipeline key.

The beginning of the end for the shader keys. Not entirely sure
what I'm going to replace them with for the compiler though, so this
is the first step.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radv: Add single pipeline cache key.

To decouple the key used for info gathering and the cache from
whatever we pass to the compiler.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radv: Don't compute as_ls/as_es before hashing.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl_to_nir: Zero nir_constant in constant_copy for valgrind & nir_serialize

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

glsl_to_nir: Zero nir_variable struct for valgrind & nir_serialize

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: Zero nir_load_const_instr::value for valgrind & nir_serialize

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/nir: Zero local index const struct for valgrind & nir_serialize

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: Zero local_size const struct for valgrind & nir_serialize

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

glsl: Add field initializers for glsl_struct_field default constructor

This helps valgrind when encode_type_to_blob is used.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

compiler/types: Support [de]serializing void types

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

nir/intrinsics: Set the correct num_indices for load_output

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

glsl: move shader_cache type handling to glsl_types

Not sure if this is the best place to put it, but we're going to need
this for NIR too.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

vulkan: Update headers and registry to 1.0.64

Acked-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Smith <asmith@feralinteractive.com>

ac/nir: generate correct instruction for atomic min/max on unsigned images

v2: fix silly typo

Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

gallium/util: remove some block alignment assertions

These assertions were revisited a couple of times in the past, and they
still weren't quite right.
The problem I was seeing (with some other state tracker) was a copy between
two 512x512 s3tc textures, but from mip level 0 to mip level 8. Therefore,
the destination has only size 2x2 (not a full block), so the box width/height
was only 2, causing the assertion to trigger for src alignment.
As far as I can tell, such a copy is completely legal, and because a correct
assertion would get ridiculously complicated just get rid of it for good.

Reviewed-by: Brian Paul <brianp@vmware.com>

meson: be explicit about the version required

This way, we know what we're allowed to use (no nested include lists
for instance) and users get immediate feedback when trying to use
unsupported versions, rather than a cryptic crash or things being
silently not built correctly.

Cc: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

meson: add opt-out of libunwind

Libunwind has some issues on some platforms, so let's allow people
who have issues to opt-out. This is similar to what we do in automake,
and the implementation is modelled after our opt-out for valgrind.

Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

gles2: support for GL_EXT_occlusion_query_boolean

Following test checking entrypoints passes:
   dEQP-EGL.functional.get_proc_address.extension.gl_ext_occlusion_query_boolean

Piglit test 'ext_occlusion_query_boolean-any-samples' passes with these changes.

No changes/regression observed in WebGL occlusion tests or Intel CI.

v2: add es2="2.0" for glapi entrypoints, clean up xml
    dispatch_sanity changes (fix 'make check')

Signed-off-by: Harish Krupo <harish.krupo.kps@intel.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: enum checks for GL_EXT_occlusion_query_boolean

Some of the checks are valid for generic ES 3.2 as well.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

radv: print NIR before LLVM IR and disassembly

It's still printed after linking, but it makes more sense to
have SPIRV->NIR->LLVM IR->ASM.

Fixes: f0a2bbd1a4 (radv: move nir print after linking is done)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: Fix truncation issue hexifying the cache uuid for the disk cache.

Going from binary to hex has a 2x blowup.

Fixes: 14216252923 'radv: create on-disk shader cache'
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: enable lower to scalar nir pass

This will allow dead components of varyings to be removed.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: add support for explicit component packing

This is needed for RADV to support explicit component packing.

This is also required to use the new NIR component splitting /
packing passes.

V2:
 - add commponent packing support for interpolate_at* intrinsics
 - improve store packing support when not all varyings are scalar
   as spotted by Bas the store source was incorrectly offset.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

i965: fix unused var warnings in release build

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

radv: use device name in cache creation like radeonsi.

Not sure how useful this is, but it makes it more consistent.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: use a define for the transition point between cp and compute shader

For certain buffer meta ops we can use the CP or a compute shader,
we should use a define to rather than hardcoding 4096, allows
for easier testing and more consistency.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

docs: Mark GL_KHR_no_error as done.

Drivers have supported KHR_no_error for a while.  We'd been leaving it
marked as "in progress" because there's a zillion places that could get
slightly more optimized.  But, Timothy and Samuel have already done
piles of work, and I think we have a solid implementation at this point.

Let's check it off the list.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

i965: Call gen6_upload_push_constants() even when the stage is disabled.

This properly sets stage_state->push_constant_dirty = true, so that we
emit 3DSTATE_CONSTANT_XS to disable the constant buffer for the shader
stage.  It also sets stage_state->push_const_size = 0.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Drop a bunch of downcasting and upcasting of gl_program pointers.

We have a gl_program and we want a gl_program.  There's no point in
converting to brw_program and back again.  This probably made more
sense in the old days before Tim dropped a layer of subclassing.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Move _mesa_shader_write_subroutine_indices down a level.

Now we call it in one place instead of making every caller do it.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

radv: only emit dfsm packets if dfsm is allowed.

radeonsi only emits these when dfsm is enabled, so for now
just hinge them on a flag we never set.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

meson: build freedreno

Mostly copy/pasta from Dylan Baker's conversion of nouveau and i965.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

meson: extract out variable for nir_algebraic.py

Also needed in freedreno/ir3.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

freedreno/ir3: use a flag instead of setting PYTHONPATH

Similar to 848da662224326ccfbe6647bc82f4f89ca22c762, pass an arg to
ir3_nir_trig.py to add to python path, rather than using $PYTHONPATH,
to prep for meson build support.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

i965: Don't disable CCS for RT dependencies when dispatching compute.

Compute shaders don't have access to the framebuffer, so there's no
point in worrying whether a texture is bound as a render target.

This saves a bunch of resolves in GFXBench4 Manhattan 3.1, but doesn't
seem to impact performance at all, at least on Apollolake.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Fix memmem compiler warnings.

gcc is throwing this warning in my meson build:

../src/intel/compiler/brw_eu_validate.c:50:11: warning
argument 1 null where non-null expected [-Wnonnull]
    return memmem(haystack.str, haystack.len,
           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                                  needle.str, needle.len) != NULL;
                                  ~~~~~~~~~~~~~~~~~~~~~~~

The first check for CONTAINS has a NULL error_msg.str and 0 len.  The
glibc implementation will exit without looking at any haystack bytes if
haystack.len < needle.len, so this was safe, but silence the warning
anyway by guarding against implementation variablility.

Fixes: 122ef3799d56 ("i965: Only insert error message if not already present")
Reviewed-by: Matt Turner <mattst88@gmail.com>

freedreno: per-context fd_pipe

To enable per-context priorities, we need to have per-context pipe's.
Unfortunately we still need to keep the global screen pipe, mostly just
for screen->get_timestamp().

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: rename pipe -> vsc_pipe

To add context priority support we need to have an fd_pipe per context,
rather than per-screen.  Which conflicts with existing ctx->pipe (which
is actually a visibility stream pipe (hw resource).  So just rename it.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: pass context flags through to fd_context_init()

Prep work for later patch.

Signed-off-by: Rob Clark <robdclark@gmail.com>

gallium/util: use util_snprintf() in u_socket_connect()

Instead of plain snprintf().  To fix the MSVC build.

snprintf() is used in various places in Mesa/gallium, but apparently,
not in code built with MSVC.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

configure: Allow android as an EGL platform

I'm working on radeonsi support in the Chrome OS Android container
(ARC++).  Mesa in ARC++ uses autotools instead of Android.mk, but all
the necessary EGL bits are there, so the existing check is too strict.

Signed-off-by: Benjamin Gordon <bmgordon@chromium.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

radeonsi: postponed KILL isn't postponed anymore, but maintains WQM

This restores performance for the drirc workaround, i.e.
KILL_IF does:
   visible = src0 >= 0;
   kill_flag &= visible; // accumulate kills
   amdgcn_kill(wqm_vote(visible)); // kill fully dead quads only

And all helper pixels are killed at the end of the shader:
   amdgcn_kill(kill_flag);

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: use postponed KILL only when derivatives are used

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: use llvm.amdgcn.kill with LLVM 6.0

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: replace ac_build_kill with ac_build_kill_if_false

This will be a new LLVM intrinsic and will also work nicely with
llvm.amdgcn.wqm.vote.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radv: move nir print after linking is done

We now have linking optimisations so we want to delay dumping the
nir until after these are complete.

Fixes: 06f05040eb73 (radv: Link shaders)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

mesa/bufferobj: don't double negate the range

This fixes a regression I introduced refactoring this code,
I managed to invert range twice, I moved the inversion into
the common code, but forgot to stop doing it in the callee.

Fixes: GL45-CTS.multi_bind.dispatch_bind_buffers_base
Fixes: 35ac13ed3 (mesa/bufferobj: consolidate some codepaths between ubo/ssbo/atomics.)
Reported-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: clone meta shaders before linking

The IR is reused in different pipeline combinations so we need
to clone it to avoid link time optimistaions messing up the
original copy.

Fixes: 06f05040eb73 (radv: Link shaders)
Reviewed-by: Dave Airlie <airlied@redhat.com>

gallium/util: don't call close() on Windows in u_tests.c

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: use util_strdup() macro in u_debug_symbol.c

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: use util_strdup() macro in symbol_table.c

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

util: add util_strdup() wrapper macro

To work around MSVC warning that strdup() is a deprecated POSIX function.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/util: replace gethostbyname() with getaddrinfo()

Compiling with MSVC options /we4995 /we4996 (a subset of /sdl) generates
a warning that the gethostbyname() function is deprecated in favor of
getaddrinfo() or GetAddrInfoW().  Replace the call with getaddrinfo().

Untested.  There are no callers to u_socket_connect() in Gallium.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radv: Update code pointer correctly if a variant is already created

This was the actual cause of GPU hangs fixed by 0fdd531457ec ("radv:
Fix pipeline cache locking issues"), since multiple threads would end
up trying to create the variants for a single entry.

Now that we're locking around the whole of this function, this isn't
really necessary (we either create all or none of the variants), but
fix this anyway in case things change later.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
CC: 17.3 <mesa-stable@lists.freedesktop.org>

i965: Revert absolute mode for constant buffer pointers.

The kernel doesn't initialize the value of the INSTPM or CS_DEBUG_MODE2
registers at context initialization time.  Instead, they're inherited
from whatever happened to be running on the GPU prior to first run of a
new context.  So, when we started setting these, other contexts in the
system started inheriting our values.  Since this controls whether
3DSTATE_CONSTANT_* takes a pointer or an offset, getting the wrong
setting is fatal for almost any process which isn't expecting this.

Unfortunately, VA-API and Beignet don't initialize this (nor does older
Mesa), so they will die horribly if we start doing this.  UXA and SNA
don't use any push constants, so they are unaffected.

Until we have some kind of solution to this problem, I'm going to revert
this patch and abandon using the feature for now.  It will lead to fewer
pushed UBO ranges on Broadwell+, which may lead to lower performance,
though I don't have any data on the impact.

Cc: "17.3 17.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102774

meson: build imx driver

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

meson: build etnaviv driver + winsys

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

ac: Silence a compiler warning about results[0].

We know that num_components will be > 0, but it doesn't.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: Fix a compiler warning for possibly undefined "name"

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

meson: fix egl build for meson version < 0.43

Meson 0.43 added the ability to pass nested lists to
include_directories, so the code that we have works for 0.43, but not
for 0.42. This patch changes the include_directories list to be flat so
it works with 0.42

fixes: 108d257a16859898f5c ("meson: build libEGL")
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>

amd/common/gfx9: workaround DCC corruption more conservatively

Fixes KHR-GL45.texture_swizzle.smoke and others on Vega.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102809
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

docs/release-calendar: update - 17.3.0-rc1 is out

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

glsl: fix derived cs variables

There are two issues with the current implementation. First, it relies
on the layout(local_size_*) happening in the same shader as the main
function, and secondly it doesn't work for variable group sizes.

In both cases, the simplest fix is to move the setup of these derived
values to a later time, similar to how the gl_VertexID workarounds are
done. There already exist system values defined for both of the derived
values, so we use them unconditionally, and lower them after linking is
performed.

While we're at it, we move to using gl_LocalGroupSizeARB instead of
gl_WorkGroupSize for variable group sizes.

Also the dead code elimination avoidance can be removed, since there
can be situations where gl_LocalGroupSizeARB is needed but has not been
inserted for the shader with main function. As a result, the lowering
code has to insert its own copies of the system values if needed.

Reported-by: Stephane Chevigny <stephane.chevigny@polymtl.ca>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103393
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

docs: add 17.4.0-devel release notes template

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

mesa: bump version to 17.4.0-devel

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

radv: automake: include radv_extensions.py in the tarball

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

ac/nir: Only clamp shadow reference on radeonsi.

Vulkan CTS does not expect the value to be clamped (at least for D32),
and it makes a differences even though depth is in [0,1], due
to strict inequalities.

I couldn't find anything in the Vulkan spec about this, but the test
seemed to be copied from GL tests and the GL spec only specifies
clamping for fixed point formats. Hence I expect radeonsi to run into
this at some point as well, but given that they still have a usecase
with the Z16->Z32 promotion, I'll leave that for someone else to clean
up.

This at least fixes radv dEQP-VK.texture.shadow.* on VI.

Fixes: 0f9e32519bb 'ac/nir: clamp shadow texture comparison value on VI'
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Disallow indirect outputs for GS on GFX9 as well.

Since it also uses the output vector before writing to memory.

Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

ac/nir: Fix nir_texop_lod on GFX for 1D arrays.

Fixes: 1bcb953e166 'radv: handle GFX9 1D textures'
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv/ac/nir: only emit tess factors to storage if tes reads them

Otherwise we just need to write them to the tf ring.

this seems to improve the tessellation demo on Bonarie
~2190->~2230 fps

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Don't use vgpr indexing for outputs on GFX9.

Due to LLVM bugs. Fixes a bunch of dEQP-VK.glsl.indexing.*
tests.

Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Account for compact array index in GS input load from LDS.

Mirrors the vram path.

Fixes: d4ecc3c9299 'ac/nir: Add loading from LDS for merged GS.'
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Don't compile shaders when they are cached already.

When the gs_copy_shader is NULL (due to an incomplete cache), but
the main shaders are found, we still do the nir, but we shouldn't
compile the shaders again. For merged shaders we should also account
for the missing shaders.

Fixes: ce03c119ce0 'radv: Add code to compile merged shaders.'
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Don't check for max GL GS invocations.

We specify 127 instead of 32 as the limit in vulkan.

Fixes: 6bc42855f92 'radv: enable GS on GFX9'
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Don't explicitly reference vertex shader for draw_id.

With merged shaders the vertex shader may not exist. This got in
because the offending patch was written before merged shaders were
upstream, but committed after.

Fixes: 75dfab24a2c 'radv: refactor indirect draws with radv_draw_info'
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Don't reset cmd_buffer->state.dirty.

Otherwise for non-indexed draws we set and immediately unset
RADV_CMD_DIRTY_INDEX_BUFFER. As all the set functions should
clear their own bit, this is unnecessary.

Fixes: 341529dbee5 'radv: use optimal packet order for draws'
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Correctly detect changed shaders for vertex descriptors.

As they were emitted after the new pipeline, the changed pipeline
detection was not working anymore.

Fixes: 341529dbee5 'radv: use optimal packet order for draws'
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

ac/nir: Set larged wrokgroup size for GS on GFX9.

They don't take a single wave anymore and we need the barriers.

Fixes: 6bc42855f92 'radv: enable GS on GFX9'
Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Take the max workgroup size of all provided shaders.

Fixes: ffaf4d608a1 'radv: Enable tessellation shaders for GFX9.'
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Fix pipeline cache locking issues

Need to lock around the whole process of retrieving cached shaders, and
around GetPipelineCacheData.

This fixes GPU hangs observed when creating multiple pipelines in
parallel, which appeared to be due to invalid shader code being pulled
from the cache.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

anv: don't assert on device init on Cannonlake

v2: Warn that support is still in alpha (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: disable stencil pma fix on Gen > 9

This workaround isn't listed on Gen10.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

blorp: enable R32G32B32X32 blorp ccs copies

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

meson: Fix vc5 deps on the XML-generated headers.

I typoed and was depending on v3d_xml.h (the gzipped xml)_, not on the
v3d_packet_v33_pack.h that the compiler and QPU packing actually use.