Luke Kenneth Casson Leighton [Wed, 8 May 2019 11:06:55 +0000 (12:06 +0100)]
disable fpissue
Luke Kenneth Casson Leighton [Wed, 8 May 2019 10:39:33 +0000 (11:39 +0100)]
make SR Latch async again, make busy signal sync into issue unit
Luke Kenneth Casson Leighton [Wed, 8 May 2019 10:39:10 +0000 (11:39 +0100)]
rename variable wid -> dep
Luke Kenneth Casson Leighton [Wed, 8 May 2019 10:19:47 +0000 (11:19 +0100)]
make write latch sync in Function Unit
Luke Kenneth Casson Leighton [Wed, 8 May 2019 09:52:19 +0000 (10:52 +0100)]
add decode out of src1 and src2 pending from FnUnit
Luke Kenneth Casson Leighton [Wed, 8 May 2019 09:21:15 +0000 (10:21 +0100)]
add regfile array test
Luke Kenneth Casson Leighton [Wed, 8 May 2019 08:21:04 +0000 (09:21 +0100)]
begin debugging, temporary sync on issueunit
Luke Kenneth Casson Leighton [Wed, 8 May 2019 07:50:11 +0000 (08:50 +0100)]
start on unit test
Luke Kenneth Casson Leighton [Wed, 8 May 2019 07:24:07 +0000 (08:24 +0100)]
connect up ALUs
Luke Kenneth Casson Leighton [Wed, 8 May 2019 07:23:57 +0000 (08:23 +0100)]
whoops connect enable / data correct way round in regfilearray
Luke Kenneth Casson Leighton [Wed, 8 May 2019 07:22:49 +0000 (08:22 +0100)]
add computational unit
Luke Kenneth Casson Leighton [Wed, 8 May 2019 05:43:00 +0000 (06:43 +0100)]
add register file connection
Luke Kenneth Casson Leighton [Wed, 8 May 2019 05:42:38 +0000 (06:42 +0100)]
add ORing of port inputs together
Luke Kenneth Casson Leighton [Wed, 8 May 2019 03:51:46 +0000 (04:51 +0100)]
connect to integer global pending vectors
Luke Kenneth Casson Leighton [Wed, 8 May 2019 02:47:54 +0000 (03:47 +0100)]
add intpick connections
Luke Kenneth Casson Leighton [Wed, 8 May 2019 02:19:02 +0000 (03:19 +0100)]
rename rel_req to req_rel
Luke Kenneth Casson Leighton [Wed, 8 May 2019 02:12:49 +0000 (03:12 +0100)]
replace go_read/go_write with go_rd/go_wr
Luke Kenneth Casson Leighton [Wed, 8 May 2019 02:11:19 +0000 (03:11 +0100)]
connect issue unit to function units
Luke Kenneth Casson Leighton [Wed, 8 May 2019 01:48:53 +0000 (02:48 +0100)]
start wiring up issue unit
Luke Kenneth Casson Leighton [Wed, 8 May 2019 01:26:34 +0000 (02:26 +0100)]
add int fu-reg dep matrix
Luke Kenneth Casson Leighton [Wed, 8 May 2019 01:13:35 +0000 (02:13 +0100)]
add names to read/write ports, add priority picker and other pieces
Luke Kenneth Casson Leighton [Wed, 8 May 2019 00:41:31 +0000 (01:41 +0100)]
begin connecting units together
Luke Kenneth Casson Leighton [Tue, 7 May 2019 11:36:33 +0000 (12:36 +0100)]
add nmigen alu_hier to experiment
Luke Kenneth Casson Leighton [Tue, 7 May 2019 11:29:41 +0000 (12:29 +0100)]
add a variant of a regfile that has individual read/write-enable lines
Luke Kenneth Casson Leighton [Tue, 7 May 2019 07:35:20 +0000 (08:35 +0100)]
add regfile.py
Luke Kenneth Casson Leighton [Tue, 7 May 2019 05:53:16 +0000 (06:53 +0100)]
update layout of test_helper.py
Luke Kenneth Casson Leighton [Tue, 7 May 2019 05:51:45 +0000 (06:51 +0100)]
simplify gitignore
Luke Kenneth Casson Leighton [Tue, 7 May 2019 05:51:00 +0000 (06:51 +0100)]
add extra ignore files
Luke Kenneth Casson Leighton [Tue, 7 May 2019 05:49:32 +0000 (06:49 +0100)]
add IEEE754 FPU dependency
Luke Kenneth Casson Leighton [Tue, 7 May 2019 05:49:08 +0000 (06:49 +0100)]
update setup.py (cookie-cut from ieee754fpu)
Luke Kenneth Casson Leighton [Tue, 7 May 2019 05:47:29 +0000 (06:47 +0100)]
convert test_address_encoder.py to nosetest3 compatibility
Luke Kenneth Casson Leighton [Tue, 7 May 2019 05:45:10 +0000 (06:45 +0100)]
add __init__.py to scoreboard directory
Luke Kenneth Casson Leighton [Tue, 7 May 2019 05:44:13 +0000 (06:44 +0100)]
add Makefile, setup.py, blank README and NEWS
Luke Kenneth Casson Leighton [Tue, 7 May 2019 05:42:28 +0000 (06:42 +0100)]
reorg TLB src
Luke Kenneth Casson Leighton [Tue, 7 May 2019 05:40:15 +0000 (06:40 +0100)]
move main python code to src directory
Luke Kenneth Casson Leighton [Tue, 7 May 2019 04:43:49 +0000 (05:43 +0100)]
add scoreboard source (moving from ieee754fpu repo)
Daniel Benusovich [Sat, 4 May 2019 22:36:59 +0000 (15:36 -0700)]
Add test setup. It compiles
Daniel Benusovich [Sat, 4 May 2019 22:36:46 +0000 (15:36 -0700)]
Add default platform
Daniel Benusovich [Sat, 4 May 2019 20:49:13 +0000 (13:49 -0700)]
Add plru test. Needs work.
Daniel Benusovich [Sat, 4 May 2019 20:48:58 +0000 (13:48 -0700)]
Move files into correct folders within ariane
Luke Kenneth Casson Leighton [Fri, 26 Apr 2019 10:56:27 +0000 (11:56 +0100)]
whitespace
rishucoding [Fri, 26 Apr 2019 09:48:08 +0000 (15:18 +0530)]
added comments in AddressEncoder.py
Luke Kenneth Casson Leighton [Tue, 23 Apr 2019 08:35:08 +0000 (09:35 +0100)]
add some use of new "Elaboratable"
Luke Kenneth Casson Leighton [Tue, 23 Apr 2019 08:31:48 +0000 (09:31 +0100)]
rename LFSR2 to LFSR in test_LFSR2.py
Luke Kenneth Casson Leighton [Tue, 23 Apr 2019 08:30:06 +0000 (09:30 +0100)]
add Elaboratable to LFSR2
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 20:58:26 +0000 (21:58 +0100)]
comment about max_exponent, remove its use: use python slice [:-1]
slice [:-1] is the python way to not need explicit length
it is already in self.state, so no need to do self.max_exponent-1
just use -1
Daniel Benusovich [Tue, 23 Apr 2019 04:45:58 +0000 (21:45 -0700)]
Move MemorySet into separate file
Daniel Benusovich [Tue, 23 Apr 2019 04:42:19 +0000 (21:42 -0700)]
Update SAC to use new LFSR import
Daniel Benusovich [Tue, 23 Apr 2019 04:41:45 +0000 (21:41 -0700)]
Replace LFSR with better version
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 20:55:41 +0000 (21:55 +0100)]
remove width, use max_exponent instead
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 20:54:47 +0000 (21:54 +0100)]
derive LFSR from LFSRPolynomial - cut even more code
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 19:53:29 +0000 (20:53 +0100)]
add a link to cachesim.py
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 19:43:26 +0000 (20:43 +0100)]
add link to online simulator
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 19:42:12 +0000 (20:42 +0100)]
add link to online simulator
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 16:03:23 +0000 (17:03 +0100)]
reduce LFSR2.__init__ by another 2 lines
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 15:50:17 +0000 (16:50 +0100)]
more whitespace / shuffle / cleanup
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 15:47:33 +0000 (16:47 +0100)]
minor code-shuffle, comments
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 15:37:40 +0000 (16:37 +0100)]
use random selection for LFSR on write
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 15:21:25 +0000 (16:21 +0100)]
write_entry, sef encoder.i has to be *conditional*
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 15:08:49 +0000 (16:08 +0100)]
sort-of put LFSR mode into SetAssocCache... not really sure what to do
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 12:53:47 +0000 (13:53 +0100)]
move max_exponent to be a property (max(self))
replace if tests with assert (single lines each)
remove self.max_exponent test on every element, use max(self) as property
set-ify the incoming argument exponents and add zero explicitly to it
pass that in to the set constructor, no need for accumulating in a temporary
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 12:34:53 +0000 (13:34 +0100)]
use a set not a list, can remove an extra line
also, spotted that width will always be 1 or greater
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 12:29:50 +0000 (13:29 +0100)]
simplify further,use max() on elements
remove function, use elements=[0] to accumulate exponents
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 11:14:42 +0000 (12:14 +0100)]
replace if elif elif with dictionary trick, and map-plus-lambda
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 11:09:31 +0000 (12:09 +0100)]
whitespace
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 11:08:04 +0000 (12:08 +0100)]
add docstrings and comments
pass in LFSR_POLY_24 into example rather than the list
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:49:02 +0000 (11:49 +0100)]
skip the entire thing if width is zero
simplify creation of feedback: use Cat(feedback, statebits)
add test code-generation
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:31:30 +0000 (11:31 +0100)]
remove redundant Signal width=1
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:30:40 +0000 (11:30 +0100)]
remove property polynomial
(why assign __polynomial then add extra code where property polynomial
*returns* __polynomial? just... assign polynomial to self)
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:27:50 +0000 (11:27 +0100)]
LFSR2.pyi, type is set not frozenset, exponents returns list
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:26:00 +0000 (11:26 +0100)]
add error reports on exceptions in LFSR2
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:25:35 +0000 (11:25 +0100)]
use set instead of frozenset
return sorted list from exponents property
join operates on strings (not the list)
simplify __repr__
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:10:04 +0000 (11:10 +0100)]
use join trick instead of manually creating the exponent string
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:07:01 +0000 (11:07 +0100)]
instead of using abstract class Set, actually *derive* from frozenset
(which was not possible to do in python2): can remove 25% of LFSR2.py in
the process. also made max_exponent just a member of LFSR2 instead of
being a property (no need for __max_exponent when max_exponent is what
is needed and can be assigned then accessed directly)
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 09:58:28 +0000 (10:58 +0100)]
remove typing, move to .pyi file (increases code clarity)
Jacob Lifshay [Mon, 22 Apr 2019 07:47:08 +0000 (00:47 -0700)]
Merge remote-tracking branch 'origin/master'
Jacob Lifshay [Mon, 22 Apr 2019 07:46:45 +0000 (00:46 -0700)]
rename LFSR -> LFSR2
Jacob Lifshay [Mon, 22 Apr 2019 07:41:42 +0000 (00:41 -0700)]
add LFSR
Jacob Lifshay [Mon, 22 Apr 2019 07:40:04 +0000 (00:40 -0700)]
add empty __init__.py files
Jacob Lifshay [Mon, 22 Apr 2019 07:25:28 +0000 (00:25 -0700)]
add waveforms dir to git, ignoring all but .gitkeep
Daniel Benusovich [Mon, 22 Apr 2019 06:45:43 +0000 (23:45 -0700)]
Add lfsr with 11 bits
Jacob Lifshay [Mon, 22 Apr 2019 06:09:52 +0000 (23:09 -0700)]
add mypy typechecker integration
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 04:53:31 +0000 (05:53 +0100)]
make tag_valid and active_bit local
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 04:36:15 +0000 (05:36 +0100)]
disable write by default
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 04:28:54 +0000 (05:28 +0100)]
move setting up of tag into MemorySet
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:57:08 +0000 (04:57 +0100)]
add TODO comment, bug #71, replace PLRU with LFSR
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:52:09 +0000 (04:52 +0100)]
data_i needs to be data_size not input_size
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:44:35 +0000 (04:44 +0100)]
hmmm.... AddressEncoder needs to be of width way_count
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:44:15 +0000 (04:44 +0100)]
move tag/vector decoding into MemorySet
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:27:40 +0000 (04:27 +0100)]
data_size+tag_size = input_size, use it
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:18:23 +0000 (04:18 +0100)]
whoops, plru_array wasnt an array
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:18:04 +0000 (04:18 +0100)]
tidyup hit/multiple, move to main block
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:17:15 +0000 (04:17 +0100)]
tidy up comments
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 02:52:23 +0000 (03:52 +0100)]
small reorg, split memory into separate module with its own read/write ports
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 02:40:39 +0000 (03:40 +0100)]
same trick with encoder, remove switch, use encoder.o
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 02:33:57 +0000 (03:33 +0100)]
replace switch statement with straight index to array
Daniel Benusovich [Mon, 22 Apr 2019 01:24:07 +0000 (18:24 -0700)]
Add ubit test for set associative
Daniel Benusovich [Mon, 22 Apr 2019 01:23:54 +0000 (18:23 -0700)]
Use singal passed into plru rather than relying on internal signal
Daniel Benusovich [Mon, 22 Apr 2019 01:23:38 +0000 (18:23 -0700)]
Change plru to be combinational
Daniel Benusovich [Mon, 22 Apr 2019 01:19:34 +0000 (18:19 -0700)]
Add output signal to PLRU