ls2.git
2 years agoinvert reset and chip-select on dram, and initialise uart input
Luke Kenneth Casson Leighton [Wed, 2 Mar 2022 13:56:55 +0000 (13:56 +0000)]
invert reset and chip-select on dram, and initialise uart input
in iverilog sim

2 years agoforgot to include firmware in build for new icarus sim platform
Luke Kenneth Casson Leighton [Wed, 2 Mar 2022 13:56:15 +0000 (13:56 +0000)]
forgot to include firmware in build for new icarus sim platform

2 years agoadd new icarus-versa-ecp5 platform in ls2.py
Luke Kenneth Casson Leighton [Tue, 1 Mar 2022 17:09:07 +0000 (17:09 +0000)]
add new icarus-versa-ecp5 platform  in ls2.py

2 years agoincrease timescale of icarus simulation
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 21:51:56 +0000 (21:51 +0000)]
increase timescale of icarus simulation
to cover the period for coldboot.bin to initialise DRAM and perform
read/write tests

2 years agofix undefined uart_tx in icarus simulation, icarus is damn smart,
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 18:12:16 +0000 (18:12 +0000)]
fix undefined uart_tx in icarus simulation, icarus is damn smart,
it respects undefined values and propagates them. kinda cool

2 years agouse a slightly different yosys initialisation sequence for memory
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 18:10:57 +0000 (18:10 +0000)]
use a slightly different yosys initialisation sequence for memory

2 years agofix memory issue in yosys synth for icarus
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 17:43:59 +0000 (17:43 +0000)]
fix memory issue in yosys synth for icarus

2 years agoadd icarus simulation of ls2 with DDR3 and ECP5 models
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 17:25:04 +0000 (17:25 +0000)]
add icarus simulation of ls2 with DDR3 and ECP5 models

2 years agoinvert CRG reset on PLL see if it makes any difference
Luke Kenneth Casson Leighton [Wed, 23 Feb 2022 14:14:53 +0000 (14:14 +0000)]
invert CRG reset on PLL see if it makes any difference
also reduce power-on-reset delay

2 years agoadd comments about DRAM sync clock being identical to main clock
Luke Kenneth Casson Leighton [Wed, 23 Feb 2022 13:14:52 +0000 (13:14 +0000)]
add comments about DRAM sync clock being identical to main clock

2 years agoxdr=4 missing on ddr3 platform request for VERSA_ECP5
Luke Kenneth Casson Leighton [Tue, 22 Feb 2022 10:54:11 +0000 (10:54 +0000)]
xdr=4 missing on ddr3 platform request for VERSA_ECP5

2 years agolengthen cdelay pauses by a factor of 10
Luke Kenneth Casson Leighton [Mon, 21 Feb 2022 22:05:07 +0000 (22:05 +0000)]
lengthen cdelay pauses by a factor of 10

2 years ago* use readl and writel for accessing memory
Luke Kenneth Casson Leighton [Mon, 21 Feb 2022 18:40:25 +0000 (18:40 +0000)]
* use readl and writel for accessing memory
* add #defines for timer loops to make it possible to shorten
  time taken in simulations when running firmware in verilator
* try pulling DRAM DFII reset HI under software control
* split out DomainRenamer for DRAM Core
* add strange-looking way to expose DFII pads on FakePHY (simulated PH)
  which ensures that, under simulation, a batch of HDL does not get
  deleted: the clk_en, reset and odt parameters deep in the DFII
  interface connected to CSRs are *not* actually connected to anything
  "real" and consequently get deleted... oh and anything connecting
  to them)
* add some firmware debug print statements that need to go some time

2 years agouse microwatt mmu powerpc.lds with better stack space
Luke Kenneth Casson Leighton [Mon, 21 Feb 2022 18:34:13 +0000 (18:34 +0000)]
use microwatt mmu powerpc.lds with better stack space

2 years agofix dfi initialisation and calibration to use
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 13:55:32 +0000 (13:55 +0000)]
fix dfi initialisation and calibration to use
microwatt memory-io read/write (stwcix/lwzcix)

2 years agoset RAM base to #defined DRAM_BASE not hard-coded value
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 13:54:03 +0000 (13:54 +0000)]
set RAM base to #defined DRAM_BASE not hard-coded value

2 years agofor simulatio keep the simulated dram in the
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 00:06:56 +0000 (00:06 +0000)]
for simulatio keep the simulated dram in the
same clock domain as the main sim, for now

2 years agoadd fake (sim) DRAM from gram library
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 00:00:01 +0000 (00:00 +0000)]
add fake (sim) DRAM from gram library

2 years agomatch up dram initialisation parameters
Luke Kenneth Casson Leighton [Sat, 19 Feb 2022 15:54:05 +0000 (15:54 +0000)]
match up dram initialisation parameters

2 years agoput together coldboot startup firmware
Luke Kenneth Casson Leighton [Sat, 19 Feb 2022 15:32:17 +0000 (15:32 +0000)]
put together coldboot startup firmware

2 years agohm -abc9 seems to be working, and without -nowidelut
Luke Kenneth Casson Leighton [Sat, 19 Feb 2022 15:07:48 +0000 (15:07 +0000)]
hm -abc9 seems to be working, and without -nowidelut

2 years agoadd DRAM class to DDR3Soc
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 21:01:51 +0000 (21:01 +0000)]
add DRAM class to DDR3Soc

2 years agoadd FPGA argument to DDR3SoC
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 21:01:11 +0000 (21:01 +0000)]
add FPGA argument to DDR3SoC

2 years agoadd microwatt console lib and #includes
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 20:11:35 +0000 (20:11 +0000)]
add microwatt console lib and #includes

2 years agomake cpu optional (test purposes), make bios optional,
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 13:43:55 +0000 (13:43 +0000)]
make cpu optional (test purposes), make bios optional,
start on adding SDRAM

2 years agoremove minerva cpu
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 14:20:19 +0000 (14:20 +0000)]
remove minerva cpu

2 years agodrop clock frequency to 25 mhz and disable abc9 (it fails to build)
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 14:16:18 +0000 (14:16 +0000)]
drop clock frequency to 25 mhz and disable abc9 (it fails to build)

2 years agoadd openocd load command for ecp5
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 14:15:58 +0000 (14:15 +0000)]
add openocd load command for ecp5

2 years agowildcards never ok. update comments
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 13:16:10 +0000 (13:16 +0000)]
wildcards never ok. update comments

2 years agoadd copyright notices
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 13:12:59 +0000 (13:12 +0000)]
add copyright notices

2 years agoupdate ECP5 PLL to accept parameters for setting arbitrary clock frequencies
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 12:30:20 +0000 (12:30 +0000)]
update ECP5 PLL to accept parameters for setting arbitrary clock frequencies

2 years agoadd start of README as reminder
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 01:24:15 +0000 (01:24 +0000)]
add start of README as reminder

2 years ago* add uart_pins to UART16550 peripheral so they get connected
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 01:23:13 +0000 (01:23 +0000)]
* add uart_pins to UART16550 peripheral so they get connected
* add yosys -abc9 option
* correct path to external_core_top.v

2 years ago* disable DDR3 for now
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 00:54:26 +0000 (00:54 +0000)]
* disable DDR3 for now
* reduce bootrom size
* add external_core_top.v when building for VERSA_ECP5

2 years agoconnect up stall signals (fake) for WB Classic compliance
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 20:10:05 +0000 (20:10 +0000)]
connect up stall signals (fake) for WB Classic compliance

2 years agoalternative uart wishbone mapping which just takes 8-bit data and
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 15:57:58 +0000 (15:57 +0000)]
alternative uart wishbone mapping which just takes 8-bit data and
drops it onto 32-bit bus

2 years agoattempt to do 8-bit downconvert on wishbone bus for uart,
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 15:43:30 +0000 (15:43 +0000)]
attempt to do 8-bit downconvert on wishbone bus for uart,
but it is probably actually 8-bit data aligned to 32-bit
(see soc.vhdl in microwatt)
also set CTS,DSR,RI, DCD to default values

2 years agocorrect syscon bus address to 0xC000_0000
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 15:04:58 +0000 (15:04 +0000)]
correct syscon bus address to 0xC000_0000

2 years agoadd microwatt SYSCON peripheral at 0xc000_0000
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 13:55:15 +0000 (13:55 +0000)]
add microwatt SYSCON peripheral at 0xc000_0000
this is for (Sys)tem (Con)figuration info

2 years agoincrease size of bootmem
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 01:35:25 +0000 (01:35 +0000)]
increase size of bootmem

2 years agoadd interrupt controller module, remove stall feature from CPU buses
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 00:41:59 +0000 (00:41 +0000)]
add interrupt controller module, remove stall feature from CPU buses

2 years agoFLGA_TARGET=verilator not uppercase
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 00:41:12 +0000 (00:41 +0000)]
FLGA_TARGET=verilator not uppercase

2 years agoadd external cpu
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 14:03:11 +0000 (14:03 +0000)]
add external cpu

2 years agoconvert boot rom to bootmem and get first hello_world firmware loaded
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 11:47:42 +0000 (11:47 +0000)]
convert boot rom to bootmem and get first hello_world firmware loaded

2 years agoadd IBM microwatt CC4 license and copyright notices
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 11:36:01 +0000 (11:36 +0000)]
add IBM microwatt CC4 license and copyright notices

2 years agoadd first cut of verilator simulation, over from microwatt
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 11:33:20 +0000 (11:33 +0000)]
add first cut of verilator simulation, over from microwatt

2 years agoadd verilog build option, make DDR3 PHY optional, add UART pins
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 10:34:48 +0000 (10:34 +0000)]
add verilog build option, make DDR3 PHY optional, add UART pins

2 years agoadd future sim option (needs Simulated DDR PHY)
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 15:33:58 +0000 (15:33 +0000)]
add future sim option (needs Simulated DDR PHY)

2 years agoadd build to gitignore
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:26:29 +0000 (14:26 +0000)]
add build to gitignore

2 years agorename examples to src
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:26:07 +0000 (14:26 +0000)]
rename examples to src

2 years agonot for any good reason, separate adding the uart16550 verilog source
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:25:44 +0000 (14:25 +0000)]
not for any good reason, separate adding the uart16550 verilog source

2 years agoadd MemoryMap to UART16550 (TODO, put that into UART16550 class)
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:13:51 +0000 (14:13 +0000)]
add MemoryMap to UART16550 (TODO, put that into UART16550 class)

2 years agostart adding uart16550
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:03:30 +0000 (14:03 +0000)]
start adding uart16550

2 years agoselect a firmware file
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 12:53:08 +0000 (12:53 +0000)]
select a firmware file

2 years agoallow selection of alternative FPGAs at commandline
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 12:48:51 +0000 (12:48 +0000)]
allow selection of alternative FPGAs at commandline

2 years agoadd blinky lights so we know FPGA is alive
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 12:42:14 +0000 (12:42 +0000)]
add blinky lights so we know FPGA is alive

2 years agomake firmware and cpu optional for now to get a basic compile
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 12:39:11 +0000 (12:39 +0000)]
make firmware and cpu optional for now to get a basic compile

2 years agobegin a tidyup on the example
Luke Kenneth Casson Leighton [Sat, 12 Feb 2022 20:57:05 +0000 (20:57 +0000)]
begin a tidyup on the example
core, put addresses of peripherals at the microwatt-expected addresses

2 years agoresolve imports, whitespace, add Copyright
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 12:37:39 +0000 (12:37 +0000)]
resolve imports, whitespace, add Copyright

2 years agoadd crg.py
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 12:36:33 +0000 (12:36 +0000)]
add crg.py

2 years agoupdate contributors
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 12:32:32 +0000 (12:32 +0000)]
update contributors

2 years agosort out license and headers for NLnet and NGI POINTER funded work
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 12:31:27 +0000 (12:31 +0000)]
sort out license and headers for NLnet and NGI POINTER funded work

2 years agoadd gram soc example and license and contributors
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 11:59:39 +0000 (11:59 +0000)]
add gram soc example and license and contributors

2 years agoempty first commit
Luke Kenneth Casson Leighton [Wed, 9 Feb 2022 13:24:08 +0000 (13:24 +0000)]
empty first commit