mesa: Fix trailing whitespace in polygon.c

Signed-off-by: Lyude <lyude@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa: Fix gross indenting in _mesa_PolygonMode()

Signed-off-by: Lyude <lyude@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

r300: Fix indenting in r300_get_param()

Signed-off-by: Lyude <lyude@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

vc4: Fix indenting in vc4_screen_get_param()

Signed-off-by: Lyude <lyude@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

intel: Add INTEL_CFLAGS to aubinator CFLAGS.

It still needs intel_aub.h.  Fixes the build.

nir: Add support for 8 and 16-bit types

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

nir/constant_expressions: Don't switch on bit size when not needed

For opcodes such as the nir_op_pack_64_2x32 for which all sources and
destinations have explicit sizes, the bit_size parameter to the evaluate
function is pointless and *should* do nothing.  Previously, we were
always switching on the bit_size and asserting if it isn't one of the
sizes in the list.  This generates way more code than needed and is a
bit cruel because it doesn't let us have a bit_size of zero on an ALU op
which shouldn't need a bit_size.

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

nir/constant_expressions: Pull the guts out into a helper block

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

i965: Stop using legacy dri_bufmgr_* and intel_* names.

Eric renamed these from dri_bufmgr_* and intel_bufmgr_* to drm_intel_*
in libdrm commit 4b9826408f65976a1a13387beda748b65e03ec52, circa 2008,
but we've been using the legacy names this whole time.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel: automake: move INTEL_CFLAGS as applicable

Only common/decoder.[ch] requires it [for intel_aub.h].

v2: The code was moved to from intel/tools to intel/common,
update accordingly.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: android: remove libdrm_intel requirement

The only part which requires libdrm_intel tools/aubinator is not built
on Android.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

Partially revert "amd/addrlib: silence warnings" to fix builds with DEBUG

This partially reverts commit 8a74140a21fe6b0d2e8a60b065b890f797f2db51.

ddebug: implement clear_texture

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: fix an unused-variable warning in a release build

vdpau: fix a maybe-uninitialized warning

softpipe: fix a maybe-uninitialized warning

/home/marek/dev/mesa-main/src/gallium/drivers/softpipe/sp_compute.c:178:
 warning: 'grid_size' may be used uninitialized in this function
 [-Wmaybe-uninitialized]

gallivm: fix a maybe-uninitialized warning

/home/marek/dev/mesa-main/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c:3598:
 warning: 'level' may be used uninitialized in this function [-Wmaybe-uninitialized]
       out1 = lp_build_cmp(&leveli_bld, PIPE_FUNC_GREATER, level, last_level);
            ^

gallium/radeon: s/dcc_disable/disable_dcc/

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: handle incompatible DCC formats in resource_copy_region

Required because of later commits.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>

radeonsi: remove a workaround for inexact *8_SNORM blits

All tests pass on Fiji now. This prevents DCC disablement due to
incompatible DCC formats due to the fallback.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>

gallium/radeon: add and use a new helper vi_dcc_enabled

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

gallium/radeon: formalize that r600_query_hw_add_result doesn't need a context

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: don't make a copy of pipe_index_buffer in draw_vbo

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

gallium/util: use const in u_index_modify helpers

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

winsys/amdgpu: remove AMDGPU_INFO_NUM_EVICTIONS

This is now exposed with libdrm_amdgpu 2.4.76.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add Vega10 PCI IDs

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeon/uvd: set correct vega10 db pitch alignment

Create new function to get correct alignment based on Asics, and change
the corresponding decode message buffer and dpb buffer size calculations

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vce: add vce support for firmware 53.19.4

v2: squashed with other similar commits

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vce: adapt gfx9 surface to vce

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

winsys/surface: add height pitch for gfx9

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>

radeon/uvd: clear message buffer when reuse

As required by firmware

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/uvd: adapt gfx9 surface to uvd

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/uvd: add uvd soc15 register

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeonsi/gfx9: disable features that don't work

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: only allow GL 3.1

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add linear address computations for texture transfers

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't generate LS and ES states

these shaders don't exist on GFX9

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: SPI_SHADER_USER_DATA changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: set/get BO tiling flags for GFX9

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: handle pitch and offset overrides for texture_from_handle

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set/validate GFX9 BO metadata

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add radeon_surf.gfx9.surf_offset

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't write mipmap level offsets to BO metadata

GFX9 doesn't have (usable) mipmap offsets.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: flush CB & DB caches with an EOP TS event

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: use ACQUIRE_MEM

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: only use CE RAM for most-used descriptors

because the CE RAM size decreased to 4 KB.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: emit FLUSH_DFSM where required

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: emit BREAK_BATCH in emit_framebuffer_state

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: fix MIP0_WIDTH & MIP0_HEIGHT for compressed texture blits

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: fix textureSize/imageSize for 1D textures

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add a workaround for 1D depth textures

The same workaround is used by Vulkan.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: enable clamping for Z UNORM formats promoted to Z32F

so that shaders don't have to do it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: image descriptor changes in mutable fields

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: FMASK image descriptor changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: image descriptor changes in immutable fields

The border color swizzle logic was copied from Vulkan. It doesn't make any
sense to me, but it passes all piglits except the stencil ones.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: DB changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: CB changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: do DCC clears on non-mipmapped textures only

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: update can_sample_z/s flags

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: pass correct parameters to buffer_get_handle

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: update si_set_optimal_micro_tile_mode

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't check array_mode for allowing TC-compatible HTILE

GFX9 supports this with all modes except linear.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: update HTILE/CMASK/FMASK allocators

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: stub testdma - array_mode_to_string

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: update r600_print_texture_info

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: move pre-GFX9 radeon_bo_metadata.* to u.legacy.*

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: set num_tile_pipes, pipe_interleave_bytes for GFX9

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: wire up new addrlib for GFX9

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: update amdgpu_addr_create for GFX9

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: rename GFX6 surface functions

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: add GFX9 surface info to radeon_surf

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.*

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: allow Z16_UNORM for TC-compatible HTILE

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: draw changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: pad shader binaries by 128 bytes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: trivial shader and ring changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: sampler state changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add a scissor bug workaround

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: rasterizer changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: disable the 2-bit format fetch fix

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set NUM_RECORDS correctly

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: ELEMENT_SIZE change

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: enable ETC2

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: disable RB+ on Vega10

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: init_config changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't set PA_SC_RASTER_CONFIG*

The registers don't exist on GFX9.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: Gather4 no longer needs the workaround

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: CP DMA changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: query changes - EVENT_WRITE and SET_PREDICATION

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: EVENT_WRITE_EOP -> RELEASE_MEM

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: INDIRECT_BUFFER change

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: enable SDMA buffer copying & clearing

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: handle GFX9 in a few places

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't read back non-existent SRBM registers

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add IB parser support

Both GFX6 and GFX9 fields are printed next to each other in parsed IBs.

The Python script parses both headers like one stream and tries to merge
all definitions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set the LLVM processor, require LLVM 5.0

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add GFX9 and VEGA10 enums

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amd: GFX9 packet changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amd: define event types for GFX9

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amd: add texture format definitions for GFX9

the DATA_FORMAT and NUM_FORMAT fields are the same, but some of the enums
differ, thus add GFX6 and GFX9 suffixes, so that the IB parser can show
enums for both.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>