radeonsi/gfx9: emit FLUSH_DFSM where required

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 174baaa01d33c410d548524782c7b9a719971c4c..e1df3b65261499f531f66b17721173d33d8392c4 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -259,6 +259,7 @@ struct si_context {
        struct r600_atom                msaa_config;
        struct si_sample_mask           sample_mask;
        struct r600_atom                cb_render_state;
+       unsigned                        last_cb_target_mask;
        struct si_blend_color           blend_color;
        struct r600_atom                clip_regs;
        struct si_clip_state            clip_state;

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 1b7aaa9a6905f6c26fbea663a812f5d77c4111e1..f6c6f1f2dc5569fc386549753710a6ee2b39812c 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -117,6 +117,17 @@ static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *a
 
        radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
 
+       /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
+        * I think we don't have to do anything between IBs.
+        */
+       if (sctx->b.chip_class >= GFX9 &&
+           sctx->last_cb_target_mask != cb_target_mask) {
+               sctx->last_cb_target_mask = cb_target_mask;
+
+               radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+               radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
+       }
+
        /* RB+ register settings. */
        if (sctx->screen->b.rbplus_allowed) {
                unsigned spi_shader_col_format =
@@ -2877,6 +2888,12 @@ static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
                                sctx->ps_iter_samples,
                                sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
                                sc_mode_cntl_1);
+
+       /* GFX9: Flush DFSM when the AA mode changes. */
+       if (sctx->b.chip_class >= GFX9) {
+               radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+               radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
+       }
 }
 
 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)