Luke Kenneth Casson Leighton [Wed, 3 Aug 2022 00:42:10 +0000 (01:42 +0100)]
completely bungled multi-EXTRA specs
https://bugs.libre-soc.org/show_bug.cgi?id=838#c9
should be d:RS;d:CR0, missing a semicolon. sigh
Luke Kenneth Casson Leighton [Wed, 3 Aug 2022 00:38:07 +0000 (01:38 +0100)]
WHOOPS. set the pack column in CSV files unconditionally to 1
fortunately it is not used yet
Luke Kenneth Casson Leighton [Sun, 31 Jul 2022 21:19:21 +0000 (22:19 +0100)]
whoops should be True
Luke Kenneth Casson Leighton [Sun, 31 Jul 2022 16:02:45 +0000 (17:02 +0100)]
whoops initialise nia_update to False
Dmitry Selyutin [Sat, 30 Jul 2022 18:18:01 +0000 (21:18 +0300)]
sv_binutils: refactor naming conventions
Dmitry Selyutin [Sat, 30 Jul 2022 12:42:10 +0000 (15:42 +0300)]
sv_binutils: introduce svp64_opindex_rm_field routine
Luke Kenneth Casson Leighton [Sat, 30 Jul 2022 19:35:58 +0000 (20:35 +0100)]
add README in ISA sim directory
Luke Kenneth Casson Leighton [Sat, 30 Jul 2022 17:48:53 +0000 (18:48 +0100)]
fix LDST immed using EXTRA2 not EXTRA3 in tests to make
room for Pack/Unpack
Luke Kenneth Casson Leighton [Sat, 30 Jul 2022 17:33:37 +0000 (18:33 +0100)]
sigh begin process of fixing unit tests which are no longer EXTRA3
on lwz.stz (immediate) makinng room for Pack/Unpack
https://bugs.libre-soc.org/show_bug.cgi?id=871
Luke Kenneth Casson Leighton [Sat, 30 Jul 2022 17:10:12 +0000 (18:10 +0100)]
add LDST-2P-*PU.csv, tracked down weirdness, it was the
BREV versions of LDST which need removing (not now)
Luke Kenneth Casson Leighton [Sat, 30 Jul 2022 16:49:09 +0000 (17:49 +0100)]
addPack/Unpack to sv_analysis, extra CSV column.
much weirdness, still investigating, lwz is still showing up in
LDST-2P-1S1D-imm which should not be happening
Luke Kenneth Casson Leighton [Sat, 30 Jul 2022 14:29:08 +0000 (15:29 +0100)]
add PACK/UNPACK constants for RM-2P-1S1D-PU
Luke Kenneth Casson Leighton [Thu, 28 Jul 2022 20:40:08 +0000 (21:40 +0100)]
much dumbness. fmvis is RM-1P-1D
Luke Kenneth Casson Leighton [Thu, 28 Jul 2022 20:36:47 +0000 (21:36 +0100)]
Revert "add fmvis as a new RM-1P-1S SVP64 RM type"
This reverts commit
9fc4f5fd4ec2e3a3e52acacaf699f18d324b9f2d.
Luke Kenneth Casson Leighton [Thu, 28 Jul 2022 20:32:42 +0000 (21:32 +0100)]
add fmvis as a new RM-1P-1S SVP64 RM type
Dmitry Selyutin [Thu, 28 Jul 2022 13:47:40 +0000 (16:47 +0300)]
sv_binutils: include SVP64 context header
Dmitry Selyutin [Thu, 28 Jul 2022 13:34:11 +0000 (16:34 +0300)]
sv_binutils: remove separate CRs table
Jacob Lifshay [Thu, 28 Jul 2022 10:10:47 +0000 (03:10 -0700)]
DOUBLE2SINGLE: convert doc comments to docstring
Jacob Lifshay [Thu, 28 Jul 2022 09:50:30 +0000 (02:50 -0700)]
re-convert frsp pseudocode
Fixes: https://bugs.libre-soc.org/show_bug.cgi?id=896
Jacob Lifshay [Thu, 28 Jul 2022 08:59:44 +0000 (01:59 -0700)]
try to add some line numbers to ast -- helps with debugging
Jacob Lifshay [Thu, 28 Jul 2022 08:58:34 +0000 (01:58 -0700)]
switch ast for assignment to tuple to use the python 3 classes
Jacob Lifshay [Thu, 28 Jul 2022 08:57:27 +0000 (01:57 -0700)]
fix line number tracking
Jacob Lifshay [Thu, 28 Jul 2022 08:47:29 +0000 (01:47 -0700)]
add handy re-indenting script
Jacob Lifshay [Wed, 27 Jul 2022 18:30:49 +0000 (11:30 -0700)]
gitlab-ci.yml: stop testing after 5 failures
Jacob Lifshay [Wed, 27 Jul 2022 18:17:07 +0000 (11:17 -0700)]
shrink build log
Jacob Lifshay [Wed, 27 Jul 2022 17:54:23 +0000 (10:54 -0700)]
add another test and fix broken fishmv pseudocode
Luke Kenneth Casson Leighton [Wed, 27 Jul 2022 13:57:12 +0000 (14:57 +0100)]
add extra fmvis to see what is going on
Konstantinos Margaritis [Wed, 27 Jul 2022 13:18:13 +0000 (13:18 +0000)]
Fix fmvis & fishmv bit handling for d0, add tests for negative fp numbers
Konstantinos Margaritis [Wed, 27 Jul 2022 11:01:37 +0000 (11:01 +0000)]
Add fishmv instruction (bug #887)
Konstantinos Margaritis [Wed, 27 Jul 2022 08:43:42 +0000 (08:43 +0000)]
fix wrong shift in fmvis, use correct immediates in test
Luke Kenneth Casson Leighton [Tue, 26 Jul 2022 15:38:53 +0000 (16:38 +0100)]
update comments in fmvis case
Luke Kenneth Casson Leighton [Tue, 26 Jul 2022 15:37:40 +0000 (16:37 +0100)]
add first FP "expected state" use it in fmvis
Luke Kenneth Casson Leighton [Tue, 26 Jul 2022 15:28:13 +0000 (16:28 +0100)]
bit more docs on fmvis
Luke Kenneth Casson Leighton [Tue, 26 Jul 2022 15:15:50 +0000 (16:15 +0100)]
off-by-one in declaration of pattern-match XO for fmvis
Luke Kenneth Casson Leighton [Tue, 26 Jul 2022 15:15:17 +0000 (16:15 +0100)]
add some more example fmvis to work out which is LSB and which MSB
Luke Kenneth Casson Leighton [Tue, 26 Jul 2022 15:11:53 +0000 (16:11 +0100)]
add example fmvis instruction to trans/svp64.py
Luke Kenneth Casson Leighton [Tue, 26 Jul 2022 15:08:21 +0000 (16:08 +0100)]
dang.
Revert "Revert "set IN1 to NONE for fmvis", in1 is FRS."
This reverts commit
ecfe1775e98cf367733a66fc368a8c6e92d92504.
Luke Kenneth Casson Leighton [Tue, 26 Jul 2022 15:06:35 +0000 (16:06 +0100)]
Revert "set IN1 to NONE for fmvis", in1 is FRS.
https://libre-soc.org/openpower/sv/int_fp_mv/
0-5 6-10 11-15 16-25 26-30 31 Form
Major FRS d1 d0 XO d2 DX-Form
This reverts commit
ff67f3220d279512fe2656136dfc3287842a91e3.
Luke Kenneth Casson Leighton [Tue, 26 Jul 2022 15:05:01 +0000 (16:05 +0100)]
use DOUBLE helper function in fmvis
Luke Kenneth Casson Leighton [Tue, 26 Jul 2022 15:04:29 +0000 (16:04 +0100)]
annoying. DX-Form is one exception to the rule of having the
immediate be directly actual fields. the immediate has to be
"de-constructed" before fitting into its places, d0 d1 and d2
Konstantinos Margaritis [Tue, 26 Jul 2022 14:48:21 +0000 (14:48 +0000)]
set IN1 to NONE for fmvis
Konstantinos Margaritis [Tue, 26 Jul 2022 13:57:46 +0000 (13:57 +0000)]
fix form and pseudo-code for fmvis, tests in 64-bit mode
Luke Kenneth Casson Leighton [Tue, 26 Jul 2022 13:25:24 +0000 (14:25 +0100)]
whitespace cleanup
Konstantinos Margaritis [Tue, 26 Jul 2022 13:22:30 +0000 (13:22 +0000)]
fix fmvis decoder, it's now a 2-operand instruction
Konstantinos Margaritis [Tue, 26 Jul 2022 10:02:35 +0000 (10:02 +0000)]
Add fmvis instruction + tests, bug #887
Dmitry Selyutin [Mon, 25 Jul 2022 12:39:25 +0000 (15:39 +0300)]
svp64.py: fix alignment
Dmitry Selyutin [Mon, 25 Jul 2022 12:24:39 +0000 (15:24 +0300)]
svp64.py: update svindex operands
Luke Kenneth Casson Leighton [Sat, 23 Jul 2022 13:16:38 +0000 (14:16 +0100)]
dump output from pypowersim_fp
Luke Kenneth Casson Leighton [Thu, 21 Jul 2022 16:27:49 +0000 (17:27 +0100)]
whoops missing variables in new subfunction after
moving code around in ISACaller
Luke Kenneth Casson Leighton [Thu, 21 Jul 2022 16:22:19 +0000 (17:22 +0100)]
add dsubstep to ISACaller
Luke Kenneth Casson Leighton [Thu, 21 Jul 2022 16:01:42 +0000 (17:01 +0100)]
sort out subvl unit test with expected results
Luke Kenneth Casson Leighton [Thu, 21 Jul 2022 11:38:48 +0000 (12:38 +0100)]
fix loopend conditions for subvectors in ISACaller
Luke Kenneth Casson Leighton [Wed, 20 Jul 2022 19:20:06 +0000 (20:20 +0100)]
rename substep to ssubstep, add dsubstep to SVP64State
Luke Kenneth Casson Leighton [Wed, 20 Jul 2022 18:35:24 +0000 (19:35 +0100)]
add first subvl unit test, subvl comes from
RM not SVSTATE
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 20:47:08 +0000 (21:47 +0100)]
move D-Immediate rewriting in ISACaller into separate function
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 20:42:08 +0000 (21:42 +0100)]
move inputs in ISACaller into get_input()
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 20:34:43 +0000 (21:34 +0100)]
move debug remap to ISACaller.remap_debug()
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 20:29:22 +0000 (21:29 +0100)]
whitespace and function-return code-morphing in ISACaller
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 20:10:59 +0000 (21:10 +0100)]
move another function in ISACaller (check_write)
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 20:05:27 +0000 (21:05 +0100)]
begin function split in ISACaller
https://bugs.libre-soc.org/show_bug.cgi?id=728
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 19:55:47 +0000 (20:55 +0100)]
remove duplicate code create ISACaller.advance_svstate_steps()
which performs required stepping of src/dst/sub-steps
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 16:37:36 +0000 (17:37 +0100)]
add SUBVL (substep) support to PowerDecoder2 and to ISACaller.
the actual computation (multiplication) is done inside PowerDecoder2
which will need to understand Pack/Unpack at some point
https://bugs.libre-soc.org/show_bug.cgi?id=871
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 13:58:49 +0000 (14:58 +0100)]
add substep getter/setter to SVP64State
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 10:50:53 +0000 (11:50 +0100)]
rename SVSTATE.svstep to SVSTATE.substep to avoid
a name-conflict with the instruction "svstep"
Luke Kenneth Casson Leighton [Sat, 16 Jul 2022 17:49:04 +0000 (18:49 +0100)]
simplify remapyield.py, skip shows the bit to be skipped
Luke Kenneth Casson Leighton [Thu, 14 Jul 2022 18:26:09 +0000 (19:26 +0100)]
got fed up of long list of ifs for manually decoded ".long"s,
replaced with a single search
Jacob Lifshay [Thu, 14 Jul 2022 09:21:54 +0000 (02:21 -0700)]
add jit_test for testing icbi and isync
TODO: integrate into unit test framework
Luke Kenneth Casson Leighton [Tue, 12 Jul 2022 15:48:10 +0000 (16:48 +0100)]
add DX-Form FRS for fmvis
https://bugs.libre-soc.org/show_bug.cgi?id=887
Luke Kenneth Casson Leighton [Tue, 12 Jul 2022 09:31:05 +0000 (10:31 +0100)]
add recognition of 0xNNN and 0bMMMM to sv/trans/svp64.py
for translation of "non-supported" opcodes in binutils
Luke Kenneth Casson Leighton [Tue, 12 Jul 2022 09:30:21 +0000 (10:30 +0100)]
add FRS as destination to PowerDecoder2 DecodeOut
Luke Kenneth Casson Leighton [Mon, 11 Jul 2022 12:29:47 +0000 (13:29 +0100)]
add mm=1 svindex test, setting single targetted SVSHAPE
Luke Kenneth Casson Leighton [Mon, 11 Jul 2022 12:21:44 +0000 (13:21 +0100)]
fix issue in SelectableInt.__rsub__ causing truncation of values
Luke Kenneth Casson Leighton [Mon, 11 Jul 2022 11:55:51 +0000 (12:55 +0100)]
fix issue in SelectableInt using slices involving SelectableInts
Andrey Miroshnikov [Mon, 11 Jul 2022 10:47:59 +0000 (10:47 +0000)]
Added insn initialisation for grev() func
Andrey Miroshnikov [Mon, 11 Jul 2022 10:24:38 +0000 (11:24 +0100)]
Missed another two form sub-headings
Andrey Miroshnikov [Mon, 11 Jul 2022 10:18:19 +0000 (11:18 +0100)]
Missed another two form sub-headings
Andrey Miroshnikov [Mon, 11 Jul 2022 10:15:49 +0000 (11:15 +0100)]
Fixed missing space for form headings
Luke Kenneth Casson Leighton [Mon, 11 Jul 2022 00:45:09 +0000 (01:45 +0100)]
compute 2nd svindex dimension using unsignee compare
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 17:52:20 +0000 (18:52 +0100)]
add yx svindex test, needed to compute size of 2nd dim
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 16:18:50 +0000 (17:18 +0100)]
Indexed SVSHAPE add bypass mode when dim sizes are 1
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 16:18:05 +0000 (17:18 +0100)]
add second svindex test, modulo 3
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 16:17:09 +0000 (17:17 +0100)]
fix svindex pseudocode, set large 2nd dim on nonskip
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 12:59:26 +0000 (13:59 +0100)]
fix svindex unit test, experiment setting dimensions
to
0b111111 in svindex pseudocode
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 11:42:26 +0000 (12:42 +0100)]
fix SVSHAPE iterator for index case, stop deepcopy
(was copying entire GPR)
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 11:42:02 +0000 (12:42 +0100)]
add new svindex sv.add test with arbitrary index map
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 11:41:32 +0000 (12:41 +0100)]
non-persistence enabled on svindex as well as svremap
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 10:53:56 +0000 (11:53 +0100)]
fix svindex pseudocode
rename RS to SVG in SVI-Form (svindex) to avoid a register name conflict
start checking things properly in test_caller_svindex.py
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 21:12:06 +0000 (22:12 +0100)]
pass GPR to SVSHAPEs in ISACaller
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 20:45:12 +0000 (21:45 +0100)]
add gpr lookup in Indexed SVSHAPE iterator (no elwidths yet)
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 20:26:28 +0000 (21:26 +0100)]
rough unit test ahowing Index REMAP basically functional in SVSHAPE
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 19:39:53 +0000 (20:39 +0100)]
add support for Indexed mode in SVSHAPE
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 12:58:21 +0000 (13:58 +0100)]
add storing of shape in requested SVSHAPE in svindex pseudocode
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 21:08:46 +0000 (22:08 +0100)]
move DX Form
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 17:54:07 +0000 (18:54 +0100)]
add first stub of svindex pseudocode
https://bugs.libre-soc.org/show_bug.cgi?id=885
Dmitry Selyutin [Wed, 6 Jul 2022 17:33:43 +0000 (20:33 +0300)]
audio/mp3: convert asm to the new notation
https://bugs.libre-soc.org/show_bug.cgi?id=884
Dmitry Selyutin [Wed, 6 Jul 2022 17:10:52 +0000 (17:10 +0000)]
svp64.py: allow macros as register names
This patch enables things like *fv0, where *fv0 is just a macro.
https://bugs.libre-soc.org/show_bug.cgi?id=884
Dmitry Selyutin [Thu, 30 Jun 2022 13:11:25 +0000 (16:11 +0300)]
svp64.py: generate registers
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 16:55:36 +0000 (17:55 +0100)]
add svindex to power_enums.py, minor_22.csv
https://bugs.libre-soc.org/show_bug.cgi?id=867
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 15:55:28 +0000 (16:55 +0100)]
indentation on fields.txt to make it more markdown-like
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 07:37:17 +0000 (08:37 +0100)]
convert Logical svp64_cases.py to new vector reg form
https://bugs.libre-soc.org/show_bug.cgi?id=884