add yx svindex test, needed to compute size of 2nd dim

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index e2c742948e57c59a65ad306b7ea2932e1e39c0fa..745bd11192142d2de1f522c490e7d1bf0f9a3cb9 100644 (file)
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -273,7 +273,12 @@ SVI-Form
 
 Pseudo-code:
 
-    # VL in Matrix Multiply is xd*yd*zd
+    # based on MAXVL compute other dimension
+    MVL <- SVSTATE[0:6]
+    d <- [0] * 6
+    dim <- SVd+1
+    do while d*dim < ([0]*4 || MVL)
+       d <- d + 1
     # set up template, then copy once location identified
     shape <- [0]*32
     shape[30:31] <- 0b00            # mode
@@ -284,9 +289,9 @@ Pseudo-code:
         else           shape[6:11] <- 0b111111 # ydim max
     else
         shape[18:20] <- 0b111       # indexed yd/xd
-        if sk = 0 then shape[0:5] <- 0 # xdim
-        else           shape[0:5] <- 0b111111 # xdim max
-        shape[6:11] <- (0b0 || SVd) # ydim
+        if sk = 1 then shape[6:11] <- 0 # ydim
+        else           shape[6:11] <- d-1 # ydim max
+        shape[0:5] <- (0b0 || SVd) # ydim
     shape[12:17] <- (0b0 || SVG)        # SVGPR
     shape[28:29] <- ew                  # element-width override
     if sk = 1 then shape[28:29] <- 0b01 # skip 1st dimension

diff --git a/src/openpower/decoder/isa/test_caller_svindex.py b/src/openpower/decoder/isa/test_caller_svindex.py
index 366943e29a6a4f3e098e273e3a690a2e33a1066d..36bb6e837a1e61a79518ec84448a0ce70704c137 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svindex.py
+++ b/src/openpower/decoder/isa/test_caller_svindex.py
@@ -224,6 +224,80 @@ class SVSTATETestCase(FHDLTestCase):
                 self.assertEqual(shape.svgpr, 0) 
             self._check_regs(sim, expected_regs)
 
+    def test_2_sv_index_add(self):
+        """sets VL=6 (via SVSTATE) then does 2D remapped svindex, and an add.
+
+        dim=3,yx=1
+        only RA is re-mapped via Indexing, not RB or RT
+        """
+        isa = SVP64Asm(['svindex 8, 1, 3, 0, 1, 0, 0',
+                        'sv.add *8, *0, *0',
+                       ])
+        lst = list(isa)
+        print ("listing", lst)
+
+        # initial values in GPR regfile
+        initial_regs = [0] * 32
+        idxs = [1, 0, 5, 2, 4, 3] # random enough
+        for i in range(6):
+            initial_regs[16+i] = idxs[i]
+            initial_regs[i] = i
+
+        # SVSTATE vl=10
+        svstate = SVP64State()
+        svstate.vl = 6 # VL
+        svstate.maxvl = 6 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
+
+        # copy before running
+        expected_regs = deepcopy(initial_regs)
+        for i in range(6):
+            xi = i % 3
+            yi = i // 3
+            remap = yi+xi*2
+            RA = initial_regs[0+idxs[remap]] # modulo 3 but still indexed
+            RB = initial_regs[0+i]
+            expected_regs[i+8] = RA+RB
+            print ("expected", i, expected_regs[i+8])
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_regs, svstate=svstate)
+
+            print (sim.spr)
+            SVSHAPE0 = sim.spr['SVSHAPE0']
+            print ("SVSTATE after", bin(sim.svstate.asint()))
+            print ("        vl", bin(sim.svstate.vl))
+            print ("        mvl", bin(sim.svstate.maxvl))
+            print ("    srcstep", bin(sim.svstate.srcstep))
+            print ("    dststep", bin(sim.svstate.dststep))
+            print ("      RMpst", bin(sim.svstate.RMpst))
+            print ("       SVme", bin(sim.svstate.SVme))
+            print ("        mo0", bin(sim.svstate.mo0))
+            print ("        mo1", bin(sim.svstate.mo1))
+            print ("        mi0", bin(sim.svstate.mi0))
+            print ("        mi1", bin(sim.svstate.mi1))
+            print ("        mi2", bin(sim.svstate.mi2))
+            print ("STATE0svgpr", hex(SVSHAPE0.svgpr))
+            print ("STATE0 xdim", SVSHAPE0.xdimsz)
+            print ("STATE0 ydim", SVSHAPE0.ydimsz)
+            print ("STATE0 skip", bin(SVSHAPE0.skip))
+            print ("STATE0  inv", SVSHAPE0.invxyz)
+            print ("STATE0order", SVSHAPE0.order)
+            print (sim.gpr.dump())
+            self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0
+            self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm
+            # rmm is 0b00001 which means mi0=0 and all others inactive (0)
+            self.assertEqual(sim.svstate.mi0, 0)
+            self.assertEqual(sim.svstate.mi1, 0)
+            self.assertEqual(sim.svstate.mi2, 0)
+            self.assertEqual(sim.svstate.mo0, 0)
+            self.assertEqual(sim.svstate.mo1, 0)
+            self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1
+            for i in range(1,4):
+                shape = sim.spr['SVSHAPE%d' % i]
+                self.assertEqual(shape.svgpr, 0) 
+            self._check_regs(sim, expected_regs)
+
     def run_tst_program(self, prog, initial_regs=None,
                               svstate=None):
         if initial_regs is None: