glsl: handle interactions between EXT_gpu_shader4 and texture extensions

also, EXT_texture_buffer_object has to be enabled separately.

Reviewed-by: Eric Anholt <eric@anholt.net>

st/mesa: expose EXT_gpu_shader4 if GLSL 1.40 is supported

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: only allow EXT_gpu_shader4 in the compatibility profile

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: expose EXT_texture_buffer_object

This is needed for exposing the samplerBuffer functions under
EXT_gpu_shader4.

v2: - expose it in the compat profile only
    - make it an alias of EXT_gpu_shader4

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (v1)
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: allow "varying out" for fragment shader outputs with EXT_gpu_shader4

Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: add texture builtin functions for EXT_gpu_shader4

v2: some fixes to texture functions thanks to piglit tests

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> (v1)
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: add arithmetic builtin functions for EXT_gpu_shader4

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: add builtin variables for EXT_gpu_shader4

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: apply some 1.30 and other rules to EXT_gpu_shader4 as well

Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: enable types for EXT_gpu_shader4

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: add `unsigned int` type for EXT_GPU_shader4

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: enable noperspective|flat|centroid for EXT_gpu_shader4

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: add scaffolding for EXT_gpu_shader4

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: enable glGet for EXT_gpu_shader4

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Eric Anholt <eric@anholt.net>

v3d: Disable SSBOs and atomic counters on vertex shaders.

The CTS fails on
dEQP-GLES31.functional.shaders.opaque_type_indexing.atomic_counter.*vertex
when they are enabled, due to the VS being run for both bin and render.  I
think this behavior is expected to be valid, but I can't find text in
atomic counters or SSBO specs saying so (the closed I found was in
shader_image_load_store).  Just disable it for now, since the closed
source driver doesn't expose vertex atomic counters/SSBOs either.

st/mesa: Don't set atomic counter size != 0 if MAX_SHADER_BUFFERS == 0.

This is just asking for tests to get confused about the HW supporting
atomics in this shader stage or not, such as
dEQP-GLES31.functional.shaders.opaque_type_indexing.atomic_counter.const_expression_vertex.

v2: Rebase on the other atomic cleanups that have happened since posting.
v3: Commit message tweak by Marek.

Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

iris: Advertise EXT_texture_sRGB_R8 support

Using the luminance format, like both brw and anv do.

iris: Enable GL_AMD_depth_clamp_separate

We support this, we just forgot to turn it on.

util: fix a compile failure in u_compute.c on windows

iris: enable preemption support for gen10

this automatically enables preemption on gen10 where it is disabled by
default but still available

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

iris: add preemption support on gen9

this is basically just porting the following two commits to gallium:
d8b50e152a0d5df0971c05b8db132fa688794001
5c454661c66fa2624cf4bba1071175070724869a

resolves kwg/mesa#49

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

iris: Split iris_flush_and_dirty_for_history into two helpers.

We create two new helpers, iris_flush_bits_for_history, and
iris_dirty_for_history, then use them in the existing function.

The first accumulates flush bits based on res->bind_history, but doesn't
actually perform a flush.  This allows us to accumulate flush bits by
looping over multiple resources, but ultimately emit a single flush for
all of them.

The latter flags dirty bits without flushing, which again allows us to
handle multiple resources, but also is more convenient when writing from
the CPU where we don't need a flush (as in commit 4d12236072).

intel/compiler: fix uninit non-static variable. (v2)

Pointed out by coverity.

v2: init nir_locals also.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

virgl/drm: insert correct handles into the table. (v3)

This inserts a handle for the flink name and a handle the correct
gem handle for the bo.

v2: fix handles/names confusion (Lepton Wu)
v3: set flink name correctly (Lepton Wu)

Reviewed-by: Chia-I Wu <olvaffe@gmail.com>

virgl/drm: handle flink name better.

This realigns this code with code from radeon.

Reviewed-by: Chia-I Wu <olvaffe@gmail.com>

virgl/drm: cleanup buffer from handle creation (v2)

This cleans up and realigns this code with what is in radeon

v2: fix names->handles (Lepton Wu)

Reviewed-by: Chia-I Wu <olvaffe@gmail.com>

iris: Actually put Mesa in GL_RENDERER string

I constructed the right thing and then returned the other one.

va: use a compute shader for the blit

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

gallium: add PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIA

docs: update calendar, and news item and link release notes for 19.0.3

docs: Add SHA256 sums for mesa 19.0.3

docs: add relnotes for 19.0.3

gallium: set PIPE_CAP_MAX_FRAMES_IN_FLIGHT to 2 for all drivers

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/isl: Resize clear color buffer to full cacheline

Fixes MCS fast clear gpu hangs with Vulkan CTS on ICL in CI.

v2 (Nanley): In the title s/Align/Resize/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>

anv/descriptor_set: Properly align descriptor buffer to a page

Instead of aligning and then taking inline uniforms into account, we
need to take inline uniforms into account and then align to a page.
Otherwise, we may not be aligned to a page and allocation may fail.

Fixes: 43f40dc7cb2 "anv: Implement VK_EXT_inline_uniform_block"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/descriptor_set: Only vma_heap_finish if we have a descriptor buffer

Fixes: 7bb34ecff98 "anv: release memory allocated by bo_heap when..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/descriptor_set: Destroy sets before pool finalization

Fixes: 105002bd2d "anv: destroy descriptor sets when pool gets..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/descriptor_set: Unlink sets from the pool in set_destroy

anv_descriptor_pool_free_set is called on the clean-up path of
anv_descriptor_set_create and the set may not have been added to the
pool's list of sets yet.  While we're here, we move adding it to that
list into set_create for symmetry.

Fixes: 105002bd2d "anv: destroy descriptor sets when pool gets..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

android/iris: fix driinfo header filename

Fixes iris driver Android build.

Fixes: faa52e328e3 "iris: Add mechanism for iris-specific driconf options"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/fs: Fix D to W conversion in opt_combine_constants

Found by GCC warning:

src/intel/compiler/brw_fs_combine_constants.cpp: In function ‘bool needs_negate(const fs_reg*, const imm*)’:
src/intel/compiler/brw_fs_combine_constants.cpp:306:34: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
       return ((reg->d & 0xffffu) < 0) != (imm->w < 0);
               ~~~~~~~~~~~~~~~~~~~^~~

The result of the bit-and is a 32-bit value with the top bits all zero.
This will never be < 0.  Instead of masking off the bits, just cast to
int16_t and let the compiler handle the actual conversion.

Fixes: e64be391dd0 ("intel/compiler: generalize the combine constants pass")
Cc: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

panfrost/midgard: Remove assembler

This code is outdated and unused; now that the compiler is mature,
there's no point keeping it around in-tree (or at all).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: Adds Bifrost shader disassembler utility

This code is stable and can live upstream independently while the rest
of the Bifrost stack comes up.

v2: Added a verbose flag to hide away some of the more verbose features
that nobody really needs

[The Bifrost disassembler is written by Connor Abbott, Lyude Paul, and
Ryan Houdek.]

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Add "op commutes?" property

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Refactor opcode tables

We create an all-encompassing opcode table for handling name and
properties, removing a number of ad hoc opcode tables which became
brittle and quickly out of date. While we're at it, we fix some
incorrect opcodes relating to ball/bany, and move a small function out
to midgard_compile.c. Together these changes should allow compilation
without warnings, along with helping the codebase health considerably.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Optimize MIR in progress loop

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Implement copy propagation

Most copy prop should occur at the NIR level, but we generate a fair
number of moves implicitly ourselves, etc... long story short, it's a
net win to also do simple copy prop + DCE on the MIR. As a bonus, this
fixes the weird imov precision bug once and for good, I think.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Set integer mods

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Document sign-extension/zero-extension bits (vector)

For floating point ops, these bits determine the "negate?" and "abs?"
modifiers. For integer ops, it turns out they control how sign/zero
extension work, useful for mixing types.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Update integer op list

In the future, we might want to switch to a table-based approach, but
for now, at least have it current.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Remove unused mir_next_block

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Fix off-by-one in successor analysis

This reduces register pressure substantially since we get smaller
liveness ranges.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Track loop depth

This fixes nested loops.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Dead code eliminate MIR

We reshuffle the existing "dead move elimination" pass into a generic
dead code elimination layer, fixing bugs incurred with looping in the
process.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: Use actual imov instruction

The bug this worked around is no longer applicable, it seems -- remove
the hack that breaks more than it fixes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: Disable indirect outputs for now

The hardware needs this lowered anyway; for now, might as well use
mesa's default lowering for pure conformance reasons.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: imul can only run on *mul

This restriction makes sense logically. Not sure why it wasn't obeyed
before. In conjunction with previous commit's disclaimer, fixes
dEQP-GLES2.functional.shaders.loop.for_dynamic_iterations.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Don't try to inline constants on branches

Along with a corresponding fix to the move elimination pass (not
included here yet -- I just have it disabled for now), this will fix
dEQP-GLES2.functional.shaders.loops.for_uniform_iterations.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: Respect backwards branches in RA

Fixes a bunch of issues with looping. Honestly, I'm not sure why loops
worked at all before.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Remove useless MIR dump

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Respect component of bcsel condition

Fixes a bunch of non-vec4 indexing.varying_array tests.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Implement indirect loads of varyings/UBOs

This adds preliminary support for indirect loads of varying arrays and
uniform arrays, bringing a few new tests in shader.indexing.* to
passing, although there remains a number of cases still missing.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Pipe through varying arrays

Varying arrays sometimes are lowered to a series of directly accessed
varyings (which we handled okay), but when indirectly accessed, they
appear as a single array; we need to handle this as well.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/mdg/disasm: Print raw varying_parameters

The semantics of this field are not well understood; it is better to
print it unconditionally along with the other unknown state, rather than
silently eat the value. Without this change, some critical state was
being lost in some shaders (notably, the offset for load/store
scratchpad intructions found in shaders that spill registers.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

iris: Prefer staging blits when destination supports CCS_E.

Otherwise our textures don't get color compression.  Thanks to
Eero Tamminen for noticing this was missing!

Improves performance of GLB27_FillTestC24Z16 on my Apollolake
laptop with single channel RAM by 2.3x.

Reported-by: Eero Tamminen <eero.t.tamminen@intel.com>

gallium: replace drm_driver_descriptor::configuration with driconf_xml

PIPE_CAPs are better.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gallium: replace DRM_CONF_SHARE_FD with PIPE_CAP_DMABUF

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gallium: replace DRM_CONF_THROTTLE with PIPE_CAP_MAX_FRAMES_IN_FLIGHT

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

st/dri: simplify throttling code

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gallium: document conservative rasterization flags

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/compiler: Lower ffma on Gen4 and Gen5

flrp32 is also a 3-source instruction, but there is another pending
series that handles that for Gen4 and Gen5.

v2: Rebase on "intel/compiler: Don't have sepearate, per-Gen
nir_options"

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/compiler: Don't have sepearate, per-Gen nir_options

Instead, just have separate scalar vs. vector nir_options and do
per-Gen "fix ups".

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Silence may unused parameter warnings in glsl/ir.h

Every file that included glsl/ir.h had a warning like:

src/compiler/glsl/ir.h: In member function ‘virtual bool ir_rvalue::is_lvalue(const _mesa_glsl_parse_state*) const’:
src/compiler/glsl/ir.h:236:64: warning: unused parameter ‘state’ [-Wunused-parameter]
    virtual bool is_lvalue(const struct _mesa_glsl_parse_state *state = NULL) const
                                                                ^
Cc: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: fa4ebf6b8d9 ("glsl: add _mesa_glsl_parse_state object to is_lvalue()")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

st/mesa/radeonsi: fix race between destruction of types and shader compilation

Commit 624789e3708c moved the destruction of types out of atexit() and
made use of a ref count instead. This is useful for avoiding a crash
where drivers such as radeonsi are still compiling in a thread when the app
exits and has not called MakeCurrent to change from the current context.

While the above scenario is technically an app bug we shouldn't crash.
However that change caused another race condition between the shader
compilation tread in radeonsi and context teardown functions.

This patch makes two changes to fix this new problem:

First we explicitly call _mesa_destroy_shader_compiler_types() when destroying
the st context rather than calling it indirectly via _mesa_free_context_data().
We do this as we must call it after st_destroy_context_priv() so that we don't
destory the glsl types before the compilation threads finish.

Next wait for the shader threads to finish in si_destroy_context() this
also means we need to call context destroy before destroying the queues
in si_destroy_screen().

Fixes: 624789e3708c ("compiler/glsl: handle case where we have multiple users for types")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radv: Add adaptive_sync driconfig option and enable it by default.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

vulkan/wsi: Add X11 adaptive sync support based on dri options.

The dri options are optional. When the dri options are not provided
the WSI will not  use adaptive sync.

FWIW I think for xf86-video-amdgpu this still requires an X11 config
option, so only people who opt in can get possible regressions from this.

So then the remaining question is: why do this in the WSI?

It has been suggested in another MR that the application sets this.
However, I disagree with that as I don't think we'll ever get a
reasonable set of applications setting it.

The next questions is whether this can be a layer. It definitely
can be as implemented now. However, I think this generally fits
well with the function of the WSI. Furthemore, for e.g. the DISPLAY
WSI this is much harder to do in a layer.

Of course, most of the WSI could almost be a layer, but I think
this still fits best in the WSI.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>

radv: Add support for driconf.

This includes 0 options.

The cache parsing is located at a position where we can easily add
config filtering by VkApplicationInfo.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

iris: add support for INTEL_conservative_rasterization

this hooks up the iris gallium driver to existing mesa bits which handle
the implementation

resolves kwg/mesa#8

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

st/mesa: indicate intel extension support for inner_coverage based on cap

if the driver (iris) indicates support for the inner_coverage pipe cap, this
will set the necessary states in the driver flags and rasterizer structs

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gallium: add pipe cap for inner_coverage conservative raster mode

this can be used by drivers which support the extension to indicate support

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Fix DrawTransformFeedback math when there's a buffer offset

We need to subtract the starting offset from the final offset before
dividing by the stride.  See src/intel/vulkan/genX_cmd_buffer.c:3142.

Not known to fix anything.

iris: Make some offset math helpers take a const isl_surf pointer

spirv: Handle SpvOpDecorateId

This operation decorate with an Id instead of a Literal or String.

It is used by HlslCounterBufferGOOGLE (provided by
SPV_GOOGLE_hlsl_functionality1).  Even if we don't do anything with
that decoration, we must be able to parse SPIR-V that uses it.

Fixes: 891886da2f9 "spirv: Add no-op support for VK_GOOGLE_hlsl_functionality1"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

spirv: Rename vtn_decoration literals to operands

Decorations (and ExecutionModes) can have not only literals, but also
Ids associated with them.  So rename the field to the more general
name "Operand" used by the spec.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: fix argument name for vkCmdEndQuery

Doesn't fix anything but it's not the right function prototype.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 673f33c77dd765 ("anv: Implement CmdBegin/EndQueryIndexed")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>

virgl: skip empty cmdbufs

Several empty cmdbufs are submitted by app/xserver per frame, from
glamor_block_handler for example.  Let's skip them.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>

gallium: Remove the malloc pipebuffer manager.

This has been unused since r600 stopped using it in 2010.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com>

gallium: Remove the "alt" pipebuffer manager interface.

This one would allocate from two underlying pools, but has never been
used.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com>

gallium: Remove the ondemand pipebuffer manager.

I couldn't find any uses in the tree since its introduction.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com>

gallium: Remove the pool pipebuffer manager.

Noticed while trying to decide if pipebuffer was of any use to me, and
found that nothing has used it in the last 10 years at least.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com>

freedreno: a2xx: same gmem2mem sequence for all tiles

Set REG_A2XX_RB_COPY_DEST_OFFSET in the tile init as it won't get touched
by the draw batch. Then gmem2mem is the same for all tiles.

Similar to what is done in a6xx, but only for gmem2mem.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>

freedreno: a2xx: enable batch reordering

Batch reordering on a2xx is now tested and functional.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>

freedreno: a2xx: use nir_lower_io for TGSI shaders

Allows removing the load_deref/store_deref code in the compiler.

tgsi_to_nir now uses screen instead of options so we can simplify that too.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>

freedreno: a2xx: disable PIPE_CAP_PACKED_UNIFORMS

a2xx driver is currently broken when PIPE_CAP_PACKED_UNIFORMS is enabled,
disable it for now.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>

freedreno: a2xx: fix builtin blit program compilation

tgsi_to_nir now requires a screen pointer and is used by fd2_prog_init.
fd2_prog_init is used before fd_context_init so set the pointer manually.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>

svga: add new ATC formats to the format conversion table

Fixes the static assertion error.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

freedreno: a2xx: add GL_AMD_compressed_ATC_texture support

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

freedreno: a3xx: add GL_AMD_compressed_ATC_texture support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: add ATC support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

llvmpipe, softpipe: no support for ATC textures

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: add ATC format support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>