Dongwon Kim [Tue, 16 Feb 2016 18:05:24 +0000 (10:05 -0800)]
configure.ac: enable_asm=yes when x-compiling across same X86 arch
Currently, configure script is forcing 'enable_asm' to be 'no'
whenever cross-compilation is performed on X86 host. This is
based on an assumption that target architecture is different
from host's (i.e. ARM). But there's always a case that we do
cross-compilation for target that is also X86 based just like
host in which same ASM codes will be supported. 'enable_asm'
should not be forced to be "no" anymore in this case.
v2: corrected commit message
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Timothy Arceri [Mon, 29 Feb 2016 00:46:37 +0000 (11:46 +1100)]
glsl: disable varying packing when its not safe
In GL 4.4+ there is no guarantee that interpolation qualifiers will
match between stages so we cannot safely pack varyings using the
current packing pass in Mesa.
We also disable packing on outerward facing interfaces for SSO
because in ES we need to retain the unpacked varying information
for draw time validation. For desktop GL we could allow packing for
SSO in versions < 4.4 but its just safer not to do so.
We do however enable packing on individual arrays, structs, and
matrices as these are required by the transform feedback code and it
is still safe to do so.
Finally we also enable packing when a varying is only used for
transform feedback and its not a SSO.
This fixes all remaining rendering issues with the dEQP SSO tests,
the only issues remaining with thoses tests are to do with validation.
Note: There is still one remaining SSO bug that this patch doesn't fix.
Their is a chance that VS -> TCS will have mismatching interfaces
because we pack VS output in case its used by transform feedback but
don't pack TCS input for performance reasons. This patch will make the
situation better but doesn't fix it.
V4: fix out of order function params after rebase, make sure packing
still disabled in tess stages. Update comments as to why we disable
packing on SSO.
V3: ES 3.1 *does* require interpolation to match so don't disable
packing there. Rebased on master rather than on enhanced layouts
component packing series.
V2: Make is_varying_packing_safe() a function in the varying_matches
class, fix spelling (Matt) and make sure to remove the outer array
when dealing with Geom and Tess shaders where appropriate.
Lastly fix piglit regression in new piglit test and document the
undefined behaviour it depends on:
arb_separate_shader_objects/execution/vs-gs-linking.shader_test
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Timothy Arceri [Tue, 24 Nov 2015 01:56:45 +0000 (12:56 +1100)]
glsl: pass disable_varying_packing bool to the lowering pass
This will allow us to choose to ignore the disable which will be
useful for more fine grained control over when to enable or disable
packing.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Marek Olšák [Tue, 15 Mar 2016 20:49:54 +0000 (21:49 +0100)]
radeonsi: fix Hyper-Z hangs on P2 configs
Cc: 11.1 11.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Romain Failliot [Tue, 15 Mar 2016 20:14:11 +0000 (16:14 -0400)]
docs: Renormalize older extensions.
For older extensions, there is an explanation first and the extension
name in brackets, like that:
Clamping controls (GL_ARB_color_buffer_float)
I inverted that so we have the extension first and then the explanation
in brackets, like that:
GL_ARB_color_buffer_float (Clamping controls)
It will help me later to parse the few extensions that use this syntax:
all drivers that support <GL_extension>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Romain Failliot [Tue, 15 Mar 2016 20:14:10 +0000 (16:14 -0400)]
docs: Renormalize some extensions.
This fixes some exceptions I have to deal with in mesamatrix.net.
The extensions GL_ARB_texture_buffer_object had a comment between "DONE"
and the brackets.
And the extension GL_KHR_robustness (in GL 4.5 and GLES 3.1) was using
"90% done" instead of "in progress". The "90% done" is still here
though, but as an extension comment.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Romain Failliot [Tue, 15 Mar 2016 20:14:09 +0000 (16:14 -0400)]
docs: Realign the "Status" column.
The "Status" column was misaligned in some GL sections.
This is a lot of diffs, but it's only spaces in the end.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Romain Failliot [Tue, 15 Mar 2016 20:14:08 +0000 (16:14 -0400)]
docs: howto to read and edit GL3.txt
Added a small guide on how to read and edit GL3.txt.
I think this would help as much the devs as the users reading this file.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Brian Paul [Thu, 17 Mar 2016 15:47:21 +0000 (09:47 -0600)]
r300g: add missing layer argument to rws->buffer_get_handle() call
Fixes compilation error since
5aea0d691.
Reviewed-by: Christian König <christian.koenig@amd.com>
Christian König [Thu, 14 Jan 2016 14:01:39 +0000 (15:01 +0100)]
radeon/winsys: add layer support for BO export
Add layer support to export individual array layers.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Christian König [Tue, 12 Jan 2016 14:59:11 +0000 (15:59 +0100)]
radeon/winsys: add offset support for BO import/export
Add offset support to handle NV12 offsets as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Christian König [Thu, 14 Jan 2016 12:51:18 +0000 (13:51 +0100)]
gallium/winsys/drm: add layer to struct winsys_handle
For exporting a specific layer of an array texture.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Christian König [Tue, 12 Jan 2016 14:19:54 +0000 (15:19 +0100)]
gallium/winsys/drm: add offset to struct winsys_handle
We are going to need this for EGL_EXT_image_dma_buf_import.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Connor Abbott [Fri, 14 Aug 2015 18:45:30 +0000 (11:45 -0700)]
nir: propagate bitsize information in nir_search
When we replace an expresion we have to compute bitsize information for the
replacement. We do this in two passes to validate that bitsize information
is consistent and correct: first we propagate bitsize from child nodes to
parent, then we do it the other way around, starting from the original's
instruction destination bitsize.
v2 (Iago):
- Always use nir_type_bool32 instead of nir_type_bool when generating
algebraic optimizations. Before we used nir_type_bool32 with constants
and nir_type_bool with variables.
- Fix bool comparisons in nir_search.c to account for bitsized types.
v3 (Sam):
- Unpack the double constant value as unsigned long long (8 bytes) in
nir_algrebraic.py.
v4 (Sam):
- Use helpers to get type size and base type from nir_alu_type.
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Connor Abbott [Tue, 17 Nov 2015 12:57:54 +0000 (13:57 +0100)]
nir: add a bit_size parameter to nir_ssa_dest_init
v2: Squash multiple commits addressing the new parameter in different
files so we don't break the build (Iago)
v3: Fix tgsi (Samuel)
v4: Fix nir_clone.c (Samuel)
v5: Fix vc4 and freedreno (Iago)
v6 (Sam)
- Fix build errors in nir_lower_indirect_derefs
- Use helper to get type size from nir_alu_type.
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Tested-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Iago Toral Quiroga [Wed, 16 Mar 2016 11:11:34 +0000 (12:11 +0100)]
nir: rename nir_const_value fields to include bitsize information
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Connor Abbott [Fri, 14 Aug 2015 17:45:06 +0000 (10:45 -0700)]
nir: update opcode definitions for different bit sizes
Some opcodes need explicit bitsizes, and sometimes we need to use the
double version when constant folding.
v2: fix output type for u2f (Iago)
v3: do not change vecN opcodes to be float. The next commit will add
infrastructure to enable 64-bit integer constant folding so this is isn't
really necessary. Also, that created problems with source modifiers in
some cases (Iago)
v4 (Jason):
- do not change bcsel to work in terms of floats
- leave ldexp generic
Squashed changes to handle different bit sizes when constant
folding since otherwise we would break the build.
v2:
- Use the bit-size information from the opcode information if defined (Iago)
- Use helpers to get type size and base type of nir_alu_type enum (Sam)
- Do not fallback to sized types to guess bit-size information. (Jason)
Squashed changes in i965 and gallium/nir drivers to support sized types.
These functions should only see sized types, but we can't make that change
until we make sure that nir uses the sized versions in all the relevant places.
A later commit will address this.
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Connor Abbott [Fri, 14 Aug 2015 17:18:39 +0000 (10:18 -0700)]
nir: add nir_{src,dest}_bit_size() helpers
v2: use a ternary (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Tue, 17 Nov 2015 14:45:18 +0000 (15:45 +0100)]
nir: Add a bit_size to nir_register and nir_ssa_def
This really hacky commit adds a bit size to registers and SSA values. It
also adds rules in the validator to validate that they do the right things.
It's still an open question as to whether or not we want a bit_size in
nir_alu_instr or if we just want to let it inherit from the destination.
I'm inclined to just let it inherit from the destination. A similar
question needs to be asked about intrinsics.
v2 (Connor):
- Relax validation: comparisons have explicit destination sizes
and implicit source sizes.
v3 (Sam):
- Use helpers to get size and base types of nir_alu_type enum.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Connor Abbott [Fri, 14 Aug 2015 17:36:15 +0000 (10:36 -0700)]
nir/types: add a function to get the bitsize of a base type
v2: fix it for GLSL_TYPE_SUBROUTINE (Iago)
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Samuel Iglesias Gonsálvez [Wed, 24 Feb 2016 09:51:22 +0000 (10:51 +0100)]
i965/nir: fix check to resolve booleans to work with sized nir_alu_type
As nir_alu_type has now embedded the data size, the check for the
instruction's output type (to see if a boolean resolve is required)
should ignore the data size part.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Fri, 15 May 2015 16:21:23 +0000 (09:21 -0700)]
nir: Add explicitly sized types
v2: Fix size/type mask to properly handle 8-bit types.
v3: Add helpers to get the bitsize and base type of a
nir_alu_type enum.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jordan Justen [Mon, 18 Jan 2016 17:45:46 +0000 (09:45 -0800)]
i965/nir: Lower nir compute shader shared variables
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Mon, 18 Jan 2016 17:59:19 +0000 (09:59 -0800)]
nir: Lower shared var atomics during nir_lower_io
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Mon, 18 Jan 2016 17:44:31 +0000 (09:44 -0800)]
nir: Add support for lowering load/stores of shared variables
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Mon, 18 Jan 2016 17:53:44 +0000 (09:53 -0800)]
nir: Add atomic operations on variables
This allows us to first generate atomic operations for shared
variables using these opcodes, and then later we can lower those to
the shared atomics intrinsics with nir_lower_io.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Sat, 9 Jan 2016 01:16:29 +0000 (17:16 -0800)]
nir: Add compute shader shared variable storage class
Previously we were receiving shared variable accesses via a lowered
intrinsic function from glsl. This change allows us to send in
variables instead. For example, when converting from SPIR-V.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Sun, 17 Jan 2016 07:11:16 +0000 (23:11 -0800)]
nir/print: Add space after shader_storage var mode
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Thu, 3 Dec 2015 08:50:49 +0000 (09:50 +0100)]
i965: Skip execution size adjustment for instructions of width 4
This code in brw_set_dest adjusts the execution size of any instruction
with a dst.width < 8. However, we don't want to do this with instructions
operating on doubles, since these will have a width of 4, but still
need an execution size of 8 (for SIMD8). Unfortunately, we can't just check
the size of the operands involved to detect if we are doing an operation on
doubles, because we can have instructions that do operations on double
operands interpreted as UD, operating on any of its 2 32-bit components.
Previous commits have made it so we never emit instructions with a horizontal
width of 4 that don't have the correct execution size set for gen6+, so
we can skip it in this case, avoiding the conflicts with fp64 requirements.
Expanding the same fix to other hardware generations requires many more
changes but since we are not targetting fp64 support on them
wer don't really care for now.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Samuel Iglesias Gonsalvez [Tue, 15 Dec 2015 08:34:38 +0000 (09:34 +0100)]
i965/vec4/gen6: fix exec_size for MOV with a width of 4 in generate_gs_ff_sync()
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Samuel Iglesias Gonsalvez [Fri, 4 Dec 2015 09:23:15 +0000 (10:23 +0100)]
i965/vec4/gen6: fix exec_size for instructions with destination width of 4
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Samuel Iglesias Gonsalvez [Thu, 3 Dec 2015 17:27:39 +0000 (18:27 +0100)]
i965/vec4/gen6: fix exec_size for instructions with width of 4 in generate_gs_svb_write()
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Samuel Iglesias Gonsalvez [Thu, 3 Dec 2015 17:05:39 +0000 (18:05 +0100)]
i965/gs/gen6: fix execsize for instructions with width of 4 in gen6_sol_program()
v2:
- Add assert (Topi).
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Iago Toral Quiroga [Thu, 3 Dec 2015 10:11:14 +0000 (11:11 +0100)]
i965: set correct execsize for MOVS with a width of 4 in brw_find_live_channel
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Iago Toral Quiroga [Thu, 3 Dec 2015 10:10:12 +0000 (11:10 +0100)]
i965/eu: set execution size for SEND message in brw_send_indirect_message
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Iago Toral Quiroga [Thu, 3 Dec 2015 09:59:23 +0000 (10:59 +0100)]
i965/fs: Set exec size for gen7 pull const loads
v2 (Topi):
- No need to set the execsize for the indirect send message,
the next patch will handle that.
- Set the execution size explicitly instead of taking it from
the width of the dst that we set before.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Iago Toral Quiroga [Thu, 3 Dec 2015 07:49:13 +0000 (08:49 +0100)]
i965/eu: set correct execution size in brw_NOP
v2: NOP should have an execsize of 1 (Matt)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Tue, 15 Mar 2016 17:51:55 +0000 (10:51 -0700)]
meta: Don't use integer handles for shaders or programs.
Previously, we gave our internal clear/blit shaders actual GL handles
and stored them in the shader/program hash table. We used ordinary
GL API entrypoints to work with them.
We thought this shouldn't be a problem because GL doesn't allow
applications to invent their own names for shaders or programs.
GL allocates all names via glCreateShader and glCreateProgram.
However, having them in the hash table is a bit risky: if a broken
application guesses the name of our shaders or programs, it could
alter them, potentially screwing up future meta operations.
Also, test cases can observe the programs in the hash table. Running
a single dEQP process that executes the following test list:
dEQP-GLES3.functional.negative_api.buffer.clear
dEQP-GLES3.functional.negative_api.shader.compile_shader
dEQP-GLES3.functional.negative_api.shader.delete_shader
would result in the last two tests breaking. The compile_shader test
calls glCompileShader(9) straight away, and since it hasn't even created
any shaders or programs, it expects to get a GL_INVALID_VALUE error
because there's no such name. However, because the clear test ran
first, it created Meta programs, so an object named "9" did exist.
This patch reworks Meta to work with gl_shader and gl_shader_program
pointers directly. These internal programs have bogus names, and are
never stored in the hash tables, so they're invisible to applications.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94485
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Tue, 15 Mar 2016 17:51:33 +0000 (10:51 -0700)]
mesa: Expose compile_shader() and link_program() beyond the file.
This will allow me to use them directly from Meta, bypassing the
versions that work with GL integer handles.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Wed, 16 Mar 2016 00:08:17 +0000 (17:08 -0700)]
mesa: Make link_program() take a gl_shader_program, not a GLuint.
In half the callers, we already have a pointer, and don't need
to look it up again. This will also help with upcoming meta work.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Tue, 15 Mar 2016 17:24:09 +0000 (10:24 -0700)]
mesa: Make compile_shader() take a gl_shader, not a GLuint.
In half the callers, we already have a pointer, and don't need
to look it up again. This will also help with upcoming meta work.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Tue, 15 Mar 2016 23:21:36 +0000 (16:21 -0700)]
meta: Use the _mesa_meta_compile_and_link_program helper more places.
Less boilerplate.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Eric Anholt [Wed, 16 Mar 2016 01:00:22 +0000 (18:00 -0700)]
vc4: Move discard handling to the condition flag.
Now that the field exists in the instruction, we can make discards less
special. As a bonus, that means that we should be able to merge some more
.sf instructions together when we get around to that.
This causes some scheduling changes, as it allows tlb_color_reads to be
delayed past the discard condition setup. Since the tlb_color_read ends
up later, this may mean performance improvements, but I haven't tested.
total instructions in shared programs: 78114 -> 78035 (-0.10%)
instructions in affected programs: 1922 -> 1843 (-4.11%)
total estimated cycles in shared programs: 234318 -> 234329 (0.00%)
estimated cycles in affected programs: 8200 -> 8211 (0.13%)
Eric Anholt [Wed, 16 Mar 2016 01:58:43 +0000 (18:58 -0700)]
vc4: Don't make a temporary for setting flags.
The register allocator doesn't really do anything about the temp, so it
doesn't seem like it should matter. However, the scheduler would think
that a new def is being created.
This doesn't change anything yet, but it avoids a bunch of regressions in
the next commit.
Eric Anholt [Wed, 16 Mar 2016 01:57:20 +0000 (18:57 -0700)]
vc4: Add a safety check for setting flags.
If a pack was on the src reg, should it be a float, int, or mul unpack?
Just complain, instead.
Eric Anholt [Wed, 16 Mar 2016 01:50:32 +0000 (18:50 -0700)]
vc4: Reuse list_for_each_entry_safe_rev().
This didn't exist when I wrote the code.
Kenneth Graunke [Tue, 15 Mar 2016 18:13:25 +0000 (11:13 -0700)]
meta: Use ARB_explicit_attrib_location in the rest of the meta shaders.
This is cleaner than using glBindAttribLocation().
Not all drivers support the extension, but I don't think those drivers
use GLSL in the first place. Apparently some Meta shaders already use
GL_ARB_explicit_attrib_location, so I think it should be okay.
Honestly, I'm not sure how the old code worked anyway - we bound the
attribute location for "texcoords", while all the shaders capitalized
or spelled it differently.
v2: Convert another instance in brw_meta_fast_clear.c.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Plamena Manolova [Tue, 15 Mar 2016 18:39:49 +0000 (20:39 +0200)]
mesa: Ignore glPointSize when GL_POINT_SIZE_ARRAY_OES is enabled
When a user defines a point size array and enables it, the point
size value set via glPointSize should be ignored. To achieve this,
we can simply toggle ctx->VertexProgram.PointSizeEnabled.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42187
Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Varad Gautam [Mon, 7 Mar 2016 19:31:59 +0000 (01:01 +0530)]
vc4: Coalesce instructions using VPM reads into the VPM read.
This is done instead of copy propagating the VPM reads into the
instructions using them, because VPM reads have to stay in order.
shader-db results:
total instructions in shared programs: 78509 -> 78114 (-0.50%)
instructions in affected programs: 5203 -> 4808 (-7.59%)
total estimated cycles in shared programs: 234670 -> 234318 (-0.15%)
estimated cycles in affected programs: 5345 -> 4993 (-6.59%)
Signed-off-by: Varad Gautam <varadgautam@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Rhys Kidd <rhyskidd@gmail.com>
Varad Gautam [Mon, 7 Mar 2016 19:31:58 +0000 (01:01 +0530)]
vc4: rename file to group vpm optimizations together
This file will contain optimization passes for both vpm reads
and writes.
Signed-off-by: Varad Gautam <varadgautam@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Tue, 15 Mar 2016 19:48:55 +0000 (12:48 -0700)]
vc4: Fix failures with nir_extract_* since the addition of the opcodes.
Roland Scheidegger [Tue, 15 Mar 2016 15:39:55 +0000 (16:39 +0100)]
llvmpipe: fix lp_rast_plane alignment on 32bit
Some rasterization code relies (for sse) on the first and third planes
(but not the second for now) being 128bit aligned, and we didn't get that
on 32bit - I mistakenly thought the 64bit number in the struct would get
the thing aligned to 64bit even on 32bit archs.
Stephane Marchesin really figured this out.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
CC: <mesa-stable@lists.freedesktop.org>
Roland Scheidegger [Tue, 15 Mar 2016 18:40:44 +0000 (19:40 +0100)]
draw: fix line stippling
The logic was comparing actual ints, not true/false values.
This meant that it was emitting always multiple line segments instead of just
one even if the stipple test had the same result, which looks inefficient, and
the segments also overlapped thus breaking line aa as well.
(In practice, with the no-op default line stipple pattern, for a 10-pixel
long line from 0-9 it was emitting 10 segments, with the individual segments
ranging from 0-1, 0-2, 0-3 and so on.)
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=94193
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
CC: <mesa-stable@lists.freedesktop.org>
Roland Scheidegger [Sun, 13 Mar 2016 18:38:23 +0000 (19:38 +0100)]
softpipe: fix misleading TGSI_QUAD_SIZE usage
All these img filter loops iterate through NUM_CHANNELS, not QUAD_SIZE.
In practice both are of course the same unchangeable value (4), but it
makes the code look a bit confusing. Moreover, some of the functions were
actually given an array of 4 values according to the declaration, yet the
code was addressing values 0/4/8/12 out of it, so fix this by just saying
it's a pointer to floats like the other functions.
While here, also add comment about not quite correct filtering.
There's no actual code difference.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Sun, 13 Mar 2016 18:13:09 +0000 (19:13 +0100)]
softpipe: fix anisotropic filtering crash
The filt_args->offset wasn't assigned but was always used later leading
to a crash (as far as I can tell, texel offsets don't actually make much
sense with anisotropic filtering, but because there's no explicit setting
if offsets are enabled there the array is always accessed).
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=94481
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
CC: <mesa-stable@lists.freedesktop.org>
Nicolai Hähnle [Fri, 11 Mar 2016 23:20:00 +0000 (18:20 -0500)]
radeonsi: set DEPTH_BEFORE_SHADER based on FS_EARLY_DEPTH_STENCIL
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 9 Feb 2016 17:54:10 +0000 (12:54 -0500)]
tgsi: add tgsi_full_src_register_from_dst helper function
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 6 Feb 2016 21:49:17 +0000 (16:49 -0500)]
gallium/u_inlines: add util_copy_image_view
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sun, 13 Mar 2016 14:10:53 +0000 (09:10 -0500)]
st/mesa: set image access flags in st_bind_images
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 12 Mar 2016 01:04:19 +0000 (20:04 -0500)]
gallium: add access field to pipe_image_view
This allows drivers to make smarter decisions e.g. about whether the image
has to be decompressed.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 11 Mar 2016 23:11:35 +0000 (18:11 -0500)]
st/glsl_to_tgsi: set FS_EARLY_DEPTH_STENCIL when required
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 11 Mar 2016 23:11:22 +0000 (18:11 -0500)]
tgsi: add TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sun, 13 Mar 2016 02:47:35 +0000 (21:47 -0500)]
st/glsl_to_tgsi: set memory access type on image intrinsics
This is required to preserve the image variable's coherent/restrict/volatile
qualifiers in TGSI.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sun, 7 Feb 2016 18:28:01 +0000 (13:28 -0500)]
st/glsl_to_tgsi: provide Texture and Format information for image ops
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 10 Mar 2016 21:30:07 +0000 (16:30 -0500)]
tgsi: add Texture and Format to tgsi_instruction_memory
Frontends should have this information readily available, and it simplifies
image LOAD/STORE/ATOM* handling especially with indirect image access.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 10 Mar 2016 22:41:29 +0000 (17:41 -0500)]
get: reconcile aliasing enums for MaxCombinedShaderOutputResources
The enums MAX_COMBINED_IMAGE_UNITS_AND_FRAGMENT_OUTPUTS and
MAX_COMBINED_SHADER_OUTPUT_RESOURCES are equal and should therefore only
appear once.
Noticed while implementing ARB_shader_image_load_store without previously
implementing SSBO.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Mon, 7 Mar 2016 03:03:56 +0000 (19:03 -0800)]
i965/fs: Restrict inequality that can only hold equal in saturate propagation.
Should have no functional change. The IP value of an instruction that
reads src_var cannot possibly be after the end of the live interval of
the variable it's reading from, by the definition of live interval.
Might save future readers a momentary WTF while trying to understand
this code.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Mon, 14 Mar 2016 02:15:45 +0000 (19:15 -0700)]
i965/vec4: Consider removal of no-op MOVs as progress during register coalesce.
Bug found by the liveness analysis validation pass that will be
introduced in a later commit. The no-op MOV check in
opt_register_coalesce() was removing instructions which makes the
cached liveness analysis calculation inconsistent with the shader IR.
We were failing to set progress to true in that case though, which
means that invalidate_live_intervals() wouldn't necessarily be called
at the end of the function.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Fri, 11 Mar 2016 23:27:22 +0000 (15:27 -0800)]
i965/fs: Add missing analysis invalidation in fixup_3src_null_dest().
Bug found by the liveness analysis validation pass that will be
introduced in a later commit. fixup_3src_null_dest() was allocating
registers which makes the cached liveness analysis calculation
incomplete, so it must be invalidated.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Fri, 11 Mar 2016 23:22:56 +0000 (15:22 -0800)]
i965/fs: Add missing analysis invalidation in opt_sampler_eot().
Bug found by the liveness analysis validation pass that will be
introduced in a later commit. opt_sampler_eot() was allocating
registers and inserting and removing instructions, which makes the
cached liveness analysis calculation inconsistent with the shader IR,
so it must be invalidated.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
Hans de Goede [Mon, 14 Mar 2016 14:01:05 +0000 (15:01 +0100)]
clover: Fix pipe_grid_info.indirect not being initialized.
After pipe_grid_info.indirect was introduced, clover was not modified
to set it causing it to pass uninitialized memory for it to launch_grid.
This commit fixes this by zero-ing the entire pipe_grid_info struct when
declaring it, to avoid similar problems popping-up in the future.
Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
[ Francisco Jerez: Trivial codestyle fix. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Sarah Sharp [Thu, 29 Oct 2015 23:11:54 +0000 (16:11 -0700)]
mesa: docs: Intel i965 hardware limits.
This should help the next person working on hardware enabling figure out
where in the Intel PRMs to find the magic platform hardware values.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Sarah Sharp [Thu, 29 Oct 2015 19:12:40 +0000 (12:12 -0700)]
mesa: docs: i965: Use correct doxygen groupings syntax
When reading the source code, it's useful to indicate that a group of
fields in a struct are related in someway. There were several places
where people tried to group related structure members with the {@
syntax, without realizing they also needed to add the \name syntax in
order to generate correct doxygen html.
There are several files with groupings that look like this:
struct foo {
/**
* Related fields description
* @{
*/
int bar;
char baz;
/** @} */
long qux;
}
However, the doxygen syntax for grouping is:
struct foo {
/**
* \name Related fields description
* @{
*/
int bar;
char baz;
/** @} */
long qux;
}
https://www.stack.nl/~dimitri/doxygen/manual/grouping.html
Without the group name definition, the fields don't get properly
grouped. Instead, the group description is applied to the first field.
Fix the Intel hardware information structure, brw_device_info to
properly group the GPU hardware limitations and hardware quirks fields.
Once you've run `cd doxygen; make clean; make all`,
updated documentation can be found at
mesa/doxygen/i965/structbrw__device__info.html
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Bruce Cherniak [Thu, 10 Mar 2016 01:30:00 +0000 (19:30 -0600)]
gallium/swr: Resource management
Better tracking of resource state and synchronization.
A follow on commit will clean up resource functions into a new
swr_resource.cpp file.
Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
Marek Olšák [Mon, 14 Mar 2016 15:41:54 +0000 (16:41 +0100)]
configure.ac: require libdrm 2.4.66 for drmGetDevice
since
737b6ed13e8f813987b5566004f0f45e9c55f1e8
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c no longer compiles:
error: unknown type name ‘drmDevicePtr’
Francisco Jerez [Wed, 9 Mar 2016 01:23:37 +0000 (17:23 -0800)]
i965: Remove useless IR self-destruct backend_shader method.
From the point it's constructed the CFG contains the only existing
copy of the program IR, and it never becomes invalid. Calling
backend_shader::invalidate_cfg would have destroyed the program
structure irrecoverably -- We weren't calling it at all for a good
reason.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
Pierre Moreau [Sun, 13 Mar 2016 21:11:30 +0000 (22:11 +0100)]
nv50,nvc0: Set only NEW_CP_GLOBALS upon binding
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Rob Clark [Sun, 13 Mar 2016 18:03:04 +0000 (14:03 -0400)]
freedreno/ir3: lower extract_byte/word
The following commits broke things by starting to feed us unhandled
extract_u16/extract_u8 opcodes:
commit
905ff861982450831a56d112036f68a751337441
Author: Matt Turner <mattst88@gmail.com>
AuthorDate: Wed Feb 3 14:28:31 2016 -0800
Commit: Matt Turner <mattst88@gmail.com>
CommitDate: Fri Mar 4 11:52:34 2016 -0800
nir: Recognize open-coded extract_u16.
commit
76289fbfa84a06ef4db8ad44ea0eb88ad0be8d5c
Author: Matt Turner <mattst88@gmail.com>
AuthorDate: Thu Jan 21 09:09:48 2016 -0800
Commit: Matt Turner <mattst88@gmail.com>
CommitDate: Fri Mar 4 11:52:34 2016 -0800
nir: Recognize open-coded extract_u8.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Sun, 13 Mar 2016 02:26:21 +0000 (21:26 -0500)]
nv50,nvc0: handle SQRT lowering inside the driver
First off, st/mesa lowers DSQRT incorrectly (it uses CMP to attempt to
find out whether the input is less than 0). Secondly the current
approach (x * rsq(x)) behaves poorly for x = inf - a NaN is produced
instead of inf.
Instead we switch to the less accurate rcp(rsq(x)) method - this behaves
nicely for all valid inputs. We still don't do this for DSQRT since the
RSQ/RCP ops are *really* inaccurate, and don't even have Newton-Raphson
steps right now. Eventually we should have a separate library function
for DSQRT that does it more precisely (and perhaps move this lowering to
the post-opt phase).
This fixes a number of dEQP precision tests that were expecting better
behavior for infinite inputs.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ilia Mirkin [Sun, 13 Mar 2016 01:53:34 +0000 (20:53 -0500)]
nv50/ir: avoid folding mul + add if the mul has a dnz
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ilia Mirkin [Sat, 12 Mar 2016 02:26:31 +0000 (21:26 -0500)]
nvc0: fix blit triangle size to fully cover FB's > 8192x8192
The idea is that a single triangle will cover the whole area being
drawn, allowing the blit shader to do its work. However the max fb size
is 16384x16384, which means that the triangle we draw needs to be twice
that in order to cover the whole area fully. Increase the size of the
triangle to 32768x32768.
This fixes a number of dEQP tests that were failing because a blit was
involved which would miss some of the resulting texture.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Rob Clark [Wed, 9 Mar 2016 09:07:51 +0000 (04:07 -0500)]
freedreno: OUT_RELOC vs OUT_RELOCW fixes
Make sure we use OUT_RELOCW() in cases where the buffer is written to.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 5 Mar 2016 21:53:11 +0000 (16:53 -0500)]
freedreno/a4xx: hw binning
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 5 Mar 2016 21:50:09 +0000 (16:50 -0500)]
freedreno/a4xx: use generated headers for draw initiator
No need to open-code this.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 5 Mar 2016 21:47:26 +0000 (16:47 -0500)]
freedreno/a4xx: remove RB_RENDER_CONTROL patching
Bitfields where shuffled around for the better on a4xx, so we don't need
any patching on this one. It appears to be something we set entirely in
the gmem code so no conflict between tiling and render state like we had
in a3xx.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 5 Mar 2016 21:41:21 +0000 (16:41 -0500)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sun, 13 Mar 2016 16:15:28 +0000 (12:15 -0400)]
freedreno/a3xx: move where we deal w/ binning FS
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 7 Mar 2016 05:52:03 +0000 (00:52 -0500)]
freedreno/a4xx: move where we deal w/ binning FS
Move where we pick dummy FS for binning pass, so the whole driver sees
the same dummy/no-op FS stage.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sun, 13 Mar 2016 16:09:51 +0000 (12:09 -0400)]
freedreno/a3xx: constify the shader variants
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 7 Mar 2016 05:50:21 +0000 (00:50 -0500)]
freedreno/a4xx: constify the shader variants
Most of the driver just needs read-only access, so constify..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sun, 6 Mar 2016 03:11:26 +0000 (22:11 -0500)]
freedreno/a3xx: remove duplicate mark of end of binning cmds
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Nicolai Hähnle [Fri, 11 Mar 2016 16:07:38 +0000 (11:07 -0500)]
radeonsi: avoid crash when a sampler state is bound for a buffer texture
Sampler states don't really make sense with buffer textures, but they
can be set anyway, so we need to be defensive here. This bug was lurking
for a while and was finally noticed due to PBO uploads setting sampler
states.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94284
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Laurent Carlier <lordheavym@gmail.com>
Tested-by: Shawn Starr <shawn.starr@rogers.com>
Matt Turner [Mon, 15 Feb 2016 06:28:51 +0000 (22:28 -0800)]
i965: Use foreach_in_list_reverse_safe() macro.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Sat, 13 Feb 2016 04:51:50 +0000 (20:51 -0800)]
nir/clone: Add support for cloning a single function_impl
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sun, 14 Feb 2016 02:08:30 +0000 (18:08 -0800)]
nir/validate: Better function validation
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sat, 13 Feb 2016 04:41:19 +0000 (20:41 -0800)]
nir/print: Better function argument printing
Since we aren't going to put the function parameters or the return variable
in the list of locals, it won't get a proper declaration. This changes
nir_print to print the type along with each parameter or return variable.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sat, 26 Dec 2015 18:26:29 +0000 (10:26 -0800)]
nir/print: Factor variable name lookup into a helper
Otherwise, we have a problem when we go to print functions with arguments
because their names get added to the hash table during declaration which
happens after we print the prototype.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Mon, 15 Feb 2016 05:42:34 +0000 (21:42 -0800)]
nir: Create function parameters in function_impl_create
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Wed, 28 Oct 2015 04:34:56 +0000 (21:34 -0700)]
nir: Add a helper for creating a "bare" nir_function_impl
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Fri, 12 Feb 2016 19:58:06 +0000 (11:58 -0800)]
nir: Add a new "param" variable mode for parameters and return variables
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>