mesa.git
9 years agonir: Try commutative sources in CSE
Ian Romanick [Mon, 13 Apr 2015 23:16:10 +0000 (16:16 -0700)]
nir: Try commutative sources in CSE

Shader-db results:

GM45 NIR:
total instructions in shared programs: 4082044 -> 4081919 (-0.00%)
instructions in affected programs:     27609 -> 27484 (-0.45%)
helped:                                44

Iron Lake NIR:
total instructions in shared programs: 5678776 -> 5678646 (-0.00%)
instructions in affected programs:     27406 -> 27276 (-0.47%)
helped:                                45

Sandy Bridge NIR:
total instructions in shared programs: 7329995 -> 7329096 (-0.01%)
instructions in affected programs:     142035 -> 141136 (-0.63%)
helped:                                406
HURT:                                  19

Ivy Bridge NIR:
total instructions in shared programs: 6769314 -> 6768359 (-0.01%)
instructions in affected programs:     140820 -> 139865 (-0.68%)
helped:                                423
HURT:                                  2

Haswell NIR:
total instructions in shared programs: 6183693 -> 6183298 (-0.01%)
instructions in affected programs:     96538 -> 96143 (-0.41%)
helped:                                303
HURT:                                  4

Broadwell NIR:
total instructions in shared programs: 7501711 -> 7498170 (-0.05%)
instructions in affected programs:     266403 -> 262862 (-1.33%)
helped:                                705
HURT:                                  5
GAINED:                                4

v2: Rebase on top of Connor's fix.

v3: Convert the if-test for num_inputs == 2 to an assertion.  Suggested
by Jason after some comments / questions by Ilia.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> [v1]
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: Connor Abbott <cwabbott0@gmail.com>
9 years agoglx: Create proper server dependency for GLX_EXT_create_context_es2_profile
Ian Romanick [Tue, 14 Apr 2015 16:24:06 +0000 (09:24 -0700)]
glx: Create proper server dependency for GLX_EXT_create_context_es2_profile

Previously GLX_EXT_create_context_es2_profile was marked as "direct
only" so that it would not depend on server support.  Since the
extension required functions that are part of
GLX_ARB_create_context_profile, support for the EXT was disabled if the
ARB was not supported.

This was complete rubbish.  If the server supported the ARB but not the
EXT, sending a request with GLX_CONTEXT_ES2_PROFILE_BIT_EXT would result
in GLXBadProfileARB.

Instead of the misguided hack, make GLX_EXT_create_context_es2_profile
properly depend on server support by not marking it as "direct only."

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
9 years agovc4: Don't try to use color load/stores to blit across format changes.
Eric Anholt [Wed, 15 Apr 2015 05:01:55 +0000 (22:01 -0700)]
vc4: Don't try to use color load/stores to blit across format changes.

We could potentially support the right combination of 8888 to 565, but the
important thing for now is to not mix up our orderings of 8888.  Fixes
fbo-copyteximage regressions.

9 years agovc4: Don't try to use color load/stores to do depth/stencil blits.
Eric Anholt [Wed, 15 Apr 2015 04:59:46 +0000 (21:59 -0700)]
vc4: Don't try to use color load/stores to do depth/stencil blits.

Fixes regressions in fbo-generatemipmap-formats on depth/stencil (which
does blits to work around baselevel/lastlevel).

9 years agovc4: Update the shadow texture for public textures on every draw.
Eric Anholt [Tue, 14 Apr 2015 18:31:11 +0000 (11:31 -0700)]
vc4: Update the shadow texture for public textures on every draw.

We don't know who else has written to it, so we'd better update it every
time.  This makes the gears spin in X again.

9 years agovc4: Hook up VC4_DEBUG=perf to some useful printfs.
Eric Anholt [Tue, 14 Apr 2015 18:24:00 +0000 (11:24 -0700)]
vc4: Hook up VC4_DEBUG=perf to some useful printfs.

9 years agost/mesa: log shaders, GLSL info log with _mesa_log()
Brian Paul [Tue, 14 Apr 2015 16:54:34 +0000 (10:54 -0600)]
st/mesa: log shaders, GLSL info log with _mesa_log()

As with previous patch.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
9 years agomesa: log shaders, GLSL info log with _mesa_log()
Brian Paul [Tue, 14 Apr 2015 16:41:56 +0000 (10:41 -0600)]
mesa: log shaders, GLSL info log with _mesa_log()

Now, if we set MESA_LOG_FILE and MESA_GLSL=dump, all the shader info
will get logged to the named file instead of stderr.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
9 years agomesa: add _mesa_log(), _mesa_get_log_file() functions
Brian Paul [Tue, 14 Apr 2015 16:24:22 +0000 (10:24 -0600)]
mesa: add _mesa_log(), _mesa_get_log_file() functions

_mesa_log() simply writes log information to stderr or MESA_LOG_FILE.
_mesa_get_log_file() returns the file handle to use for logging.

This will be used for shader dumping/logging instead of always printing
to stderr.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
9 years agotgsi: also dump label for TGSI_OPCODE_BGNSUB opcode
Brian Paul [Thu, 9 Apr 2015 19:45:18 +0000 (13:45 -0600)]
tgsi: also dump label for TGSI_OPCODE_BGNSUB opcode

So we can see the label associated with subroutines.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
9 years agost/wgl: Couple of fixes to opengl32.dll's wglCreateContext/wglDeleteContext dispatch.
Jose Fonseca [Tue, 14 Apr 2015 13:25:21 +0000 (14:25 +0100)]
st/wgl: Couple of fixes to opengl32.dll's wglCreateContext/wglDeleteContext dispatch.

- Use GetModuleHandle instead of LoadLibrary to avoid incrementing the
  opengl32.dll reference count (otherwise the opengl32.dll will linger
  in memory forever.)

- Ensure we use our fake wglCreateContext/wglDeleteContext when using
  Mesa as a drop-in replacement for opengl32.dll

Untested.  Just noticed by accident.

Reviewed-by: Brian Paul <brianp@vmware.com>
9 years agomesa: Enable _mesa_dlopen on MSVC too.
Jose Fonseca [Tue, 14 Apr 2015 13:25:06 +0000 (14:25 +0100)]
mesa: Enable _mesa_dlopen on MSVC too.

As pointed out by Shervin Sharifi.

Reviewed-by: Brian Paul <brianp@vmware.com>
9 years agoglsl: fix assignment of multiple scalar and vecs to matrices.
Samuel Iglesias Gonsalvez [Thu, 27 Nov 2014 08:39:05 +0000 (09:39 +0100)]
glsl: fix assignment of multiple scalar and vecs to matrices.

When a vec has more elements than row components in a matrix, the
code could end up failing an assert inside assign_to_matrix_column().

This patch makes sure that when there is still room in the matrix for
more elements (but in other columns of the matrix), the data is actually
assigned.

This patch fixes the following dEQP test:

  dEQP-GLES3.functional.shaders.conversions.matrix_combine.float_bvec4_ivec2_bool_to_mat4x2_vertex
  dEQP-GLES3.functional.shaders.conversions.matrix_combine.float_bvec4_ivec2_bool_to_mat4x2_fragment

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
9 years agonir: Fix typo in "ushr by 0" algebraic replacement
Ian Romanick [Tue, 14 Apr 2015 15:40:22 +0000 (08:40 -0700)]
nir: Fix typo in "ushr by 0" algebraic replacement

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Cc: "10.5" <mesa-stable@lists.freedestkop.org>
9 years agonir: Silence unused parameter warnings
Ian Romanick [Mon, 13 Apr 2015 23:42:59 +0000 (16:42 -0700)]
nir: Silence unused parameter warnings

nir/nir.h: In function 'nir_validate_shader':
nir/nir.h:1567:56: warning: unused parameter 'shader' [-Wunused-parameter]
 static inline void nir_validate_shader(nir_shader *shader) { }
                                                        ^
nir/nir_opt_cse.c: In function 'src_is_ssa':
nir/nir_opt_cse.c:165:32: warning: unused parameter 'data' [-Wunused-parameter]
 src_is_ssa(nir_src *src, void *data)
                                ^
nir/nir_opt_cse.c: In function 'dest_is_ssa':
nir/nir_opt_cse.c:171:35: warning: unused parameter 'data' [-Wunused-parameter]
 dest_is_ssa(nir_dest *dest, void *data)
                                   ^

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
9 years agonir/cse: fix bug with comparing non-per-component sources
Connor Abbott [Tue, 14 Apr 2015 19:44:24 +0000 (15:44 -0400)]
nir/cse: fix bug with comparing non-per-component sources

We weren't comparing the right number of components when checking
swizzles. Use nir_ssa_alu_instr_num_src_components() to do the right
thing.

No piglit regressions, and no fixes either.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
9 years agoi965/fs: Combine tex/fb_write operations (opt)
Ben Widawsky [Sun, 8 Feb 2015 21:59:57 +0000 (13:59 -0800)]
i965/fs: Combine tex/fb_write operations (opt)

Certain platforms support the ability to sample from a texture, and write it out
to the file RT - thus saving a costly send instructions (note that this is a
potnential win if one wanted to backport to a tag that didn't have the patch
from Topi which removed excess MOVs from LOAD_PAYLOAD - 97caf5fa04dbd2),

v2: Modify the algorithm. Instead of iterating in reverse through blocks and
insts, since the last block/inst is the only thing which can benefit. Rebased
on top of Ken's patching modifying is_last_send

v3: Rebased over almost 2 months, and Incorporated feedback from Matt:
Some comment typo fixes and rewordings.
Whitespace
Move the optimization pass outside of the optimize loop

v4: Some cosmetic changes requested from Ken. These changes ensured that the
optimization function always returned true when an optimization occurred, and
false when one did not. This behavior did not exist with the original patch. As
a result, having the separate helper function which Matt did not like no longer
made sense, and so now I believe everyone should be happy.

Benchmark (n=20)   %diff
*OglBatch5         -1.4
*OglBatch7         -1.79
OglFillTexMulti    5.57
OglFillTexSingle   1.16
OglShMapPcf        0.05
OglTexFilterAniso  3.01
OglTexFilterTri    1.94

No piglit regressions:
(http://otc-gfxtest-01.jf.intel.com:8080/view/dev/job/bwidawsk/112/)

[*] I believe my measurements are incorrect for Batch5-7. If I add this new
optimization, but never emit the new instruction I see similar results.

v5: Remove declaration of combine_tex_header since v4 dropped that function
(Ben)
Remove check for impossible case of an empty block (Matt)
Set dest earlier to avoid extra special-casing in generate_tex (Matt)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Only emit FS_OPCODE_PLACEHOLDER_HALT if there are discards
Ben Widawsky [Fri, 10 Apr 2015 17:04:55 +0000 (10:04 -0700)]
i965/fs: Only emit FS_OPCODE_PLACEHOLDER_HALT if there are discards

Based originally on a patch from Ken in May 2014 of the same title. Things
changed enough that I didn't feel comfortable leaving his authorship.

v2: Replace fp->UsesKill with wm_prog_data->uses_kill. Since Ken took the time
to also explain the difference to me, here is his explanation for posterity:

"fp->UsesKill indicates that a ARB_fragment_program shader uses the KIL
instruction, or that a GLSL shader uses the "discard" insntruction
(which are analogous).

On Gen4-5, we sometimes have to simulate OpenGL's "Alpha Test" feature
by emitting shader code that implicitly does a "discard" instruction.

In the key setup, we do:

   /* key->alpha_test_func means simulating alpha testing via discards,
    * so the shader definitely kills pixels.
    */
   prog_data.uses_kill = fp->program.UsesKill || key->alpha_test_func;

Even though the shader may not technically contain a "discard", we need
to act as if it does.

I've also been trying to move the i965 state setup code to use
brw_wm_prog_key for everything, rather than poking at core Mesa's
gl_program/gl_fragment_program/gl_shader/gl_shader_program structures.

--Ken"

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Create a has_side_effects for fs_inst
Ben Widawsky [Tue, 31 Mar 2015 22:49:42 +0000 (15:49 -0700)]
i965/fs: Create a has_side_effects for fs_inst

When an instruction has a side effect, it impacts the available options when
reordering an instruction. As the EOT flag is an implied write to the render
target in the FS, it can be considered a side effect.

This patch shouldn't actually have any impact on the current code since the EOT
flag implies that the opcode is already one with side effects,
FS_OPCODE_FB_WRITE. The next patch however will introduce an optimization
whereby the EOT flag can occur with an opcode SHADER_OPCODE_TEX, and as that
instruction will perform the same implied write to the render target, it cannot
be reordered.

v2: Remove extra whitespace (Matt)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965: replace __FUNCTION__ with __func__
Marius Predut [Tue, 7 Apr 2015 19:05:28 +0000 (22:05 +0300)]
i965: replace __FUNCTION__ with __func__

Consistently just use C99's __func__ everywhere.
No functional changes.

Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Marius Predut <marius.predut@intel.com>
9 years agoi915: replace __FUNCTION__ with __func__
Marius Predut [Tue, 7 Apr 2015 19:05:44 +0000 (22:05 +0300)]
i915: replace __FUNCTION__ with __func__

Consistently just use C99's __func__ everywhere.
No functional changes.

Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Marius Predut <marius.predut@intel.com>
9 years agoglx: replace __FUNCTION__ with __func__
Marius Predut [Tue, 7 Apr 2015 19:06:01 +0000 (22:06 +0300)]
glx: replace __FUNCTION__ with __func__

Consistently just use C99's __func__ everywhere.
No functional changes.

Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Marius Predut <marius.predut@intel.com>
9 years agomain: replace __FUNCTION__ with __func__
Marius Predut [Tue, 7 Apr 2015 19:04:58 +0000 (22:04 +0300)]
main: replace __FUNCTION__ with __func__

Consistently just use C99's __func__ everywhere.
The patch was verified with Microsoft Visual studio 2013
redistributable package(RTM version number: 18.0.21005.1)
Next MSVC versions intends to support __func__.
No functional changes.

Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Marius Predut <marius.predut@intel.com>
9 years agostate_tracker: replace __FUNCTION__ with __func__
Marius Predut [Tue, 7 Apr 2015 19:04:38 +0000 (22:04 +0300)]
state_tracker: replace __FUNCTION__ with __func__

Consistently just use C99's __func__ everywhere.
The patch was verified with Microsoft Visual studio 2013
redistributable package(RTM version number: 18.0.21005.1)
Next MSVC versions intends to support __func__.
No functional changes.

Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Marius Predut <marius.predut@intel.com>
9 years agoswrast: replace __FUNCTION__ with __func__
Marius Predut [Tue, 7 Apr 2015 19:03:52 +0000 (22:03 +0300)]
swrast: replace __FUNCTION__ with __func__

Consistently just use C99's __func__ everywhere.
The patch was verified with Microsoft Visual studio 2013
redistributable package(RTM version number: 18.0.21005.1)
Next MSVC versions intends to support __func__.
No functional changes.

Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Marius Predut <marius.predut@intel.com>
9 years agovbo: replace __FUNCTION__ with __func__
Marius Predut [Fri, 3 Apr 2015 12:02:33 +0000 (15:02 +0300)]
vbo: replace __FUNCTION__ with __func__

Consistently just use C99's __func__ everywhere.
The patch was verified with Microsoft Visual studio 2013
redistributable package(RTM version number: 18.0.21005.1)
Next MSVC versions intends to support __func__.
No functional changes.

Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Marius Predut <marius.predut@intel.com>
9 years agotnl: replace __FUNCTION__ with __func__
Marius Predut [Fri, 3 Apr 2015 13:11:57 +0000 (16:11 +0300)]
tnl: replace __FUNCTION__ with __func__

Consistently just use C99's __func__ everywhere.
The patch was verified with Microsoft Visual studio 2013
redistributable package(RTM version number: 18.0.21005.1)
Next MSVC versions intends to support __func__.
No functional changes.

Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Marius Predut <marius.predut@intel.com>
9 years agoi965/fs: Correct mistake in determining whether a MUL is negated.
Matt Turner [Mon, 13 Apr 2015 18:29:14 +0000 (11:29 -0700)]
i965/fs: Correct mistake in determining whether a MUL is negated.

a * b is equivalent to -a * -b, and the previous code was failing at
that.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89961
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
9 years agoi965/skl: Use an exec size of 8 to initialise the message header
Neil Roberts [Fri, 10 Apr 2015 16:20:21 +0000 (17:20 +0100)]
i965/skl: Use an exec size of 8 to initialise the message header

Commit e93566a15c61c33faa changed the message header code needed to
make Skylake use SIMD4x2 so that it uses a register with width 4
instead of 8 as the source register in the send message. However it
also changed the width for the dest in the MOV instruction which is
used to initialise the header register with the values from g0. The
width of the destination is used to determine the exec size in
brw_set_dest so this would end up making the MOV have an exec size of
4. I think this would end up leaving the top half of the register
uninitialised. The top half of the header has meaningful values so
this probably isn't a good idea.

This patch just casts the dest register for the MOV instruction back
to a vec8 to fix it. It doesn't cause any changes to a Piglit run.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
9 years agoi965/fs: Always invert predicate of SEL with swapped arguments
Ian Romanick [Mon, 23 Mar 2015 19:03:56 +0000 (12:03 -0700)]
i965/fs: Always invert predicate of SEL with swapped arguments

Commit b616164 added an optimization of b2f generation of a comparison.
It also included an extra optimization of one of the comparison values
is a constant of zero.  The trick was that some value was known to be
zero, so that value could be used in the SEL instruction instead of
potentially loading 0.0 into a register.

This change switched the order of the arguments to the SEL, and, for
some unknown reason, I thought that the predicate should therefore
only be inverted for the == case.  Clearly, it should always be
inverted.

Fixes piglit fs-notEqual-of-expression.shader_test and
fs-equal-of-expression.shader_test.

v2: Don't do the "register already has zero" optimization for the '== 0'
case.  In that case, the register does not have zero when we want to
produce a zero result.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89722
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v1]
Tested-by: Lu Hua <huax.lu@intel.com>
9 years agoradeon/llvm: Improve codegen for KILL_IF
Tom Stellard [Mon, 13 Apr 2015 13:25:41 +0000 (13:25 +0000)]
radeon/llvm: Improve codegen for KILL_IF

Rather than emitting one kill instruction per component of KILL_IF's src
reg, we now or the components of the src register together and use the
result as a condition for just one kill instruction.

shader-db stats (bonaire):

979 shaders
Totals:
SGPRS: 34872 -> 34848 (-0.07 %)
VGPRS: 20696 -> 20676 (-0.10 %)
Code Size: 749032 -> 748452 (-0.08 %) bytes
LDS: 11 -> 11 (0.00 %) blocks
Scratch: 12288 -> 12288 (0.00 %) bytes per wave

Totals from affected shaders:
SGPRS: 1184 -> 1160 (-2.03 %)
VGPRS: 600 -> 580 (-3.33 %)
Code Size: 13200 -> 12620 (-4.39 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave

Increases:
SGPRS: 2 (0.00 %)
VGPRS: 0 (0.00 %)
Code Size: 0 (0.00 %)
LDS: 0 (0.00 %)
Scratch: 0 (0.00 %)

Decreases:
SGPRS: 5 (0.01 %)
VGPRS: 5 (0.01 %)
Code Size: 25 (0.03 %)
LDS: 0 (0.00 %)
Scratch: 0 (0.00 %)

*** BY PERCENTAGE ***

Max Increase:

SGPRS: 32 -> 40 (25.00 %)
VGPRS: 0 -> 0 (0.00 %)
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave

Max Decrease:

SGPRS: 32 -> 24 (-25.00 %)
VGPRS: 16 -> 12 (-25.00 %)
Code Size: 116 -> 96 (-17.24 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave

*** BY UNIT ***

Max Increase:

SGPRS: 64 -> 72 (12.50 %)
VGPRS: 0 -> 0 (0.00 %)
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave

Max Decrease:

SGPRS: 32 -> 24 (-25.00 %)
VGPRS: 16 -> 12 (-25.00 %)
Code Size: 424 -> 356 (-16.04 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
9 years agoradeon/llvm: Run LLVM's instruction combining pass
Tom Stellard [Fri, 10 Apr 2015 17:07:16 +0000 (17:07 +0000)]
radeon/llvm: Run LLVM's instruction combining pass

This should improve code quality in general and will help with some
future changes to how we emit kill instructions.

shader-db shows a few regressions, but these don't seem to be the result
of deficiencies in instcombine.  They're mostly caused by the scheduler
making different decisions than before.

shader-db stats (bonaire):

979 shaders
Totals:
SGPRS: 35056 -> 34872 (-0.52 %)
VGPRS: 20624 -> 20696 (0.35 %)
Code Size: 764372 -> 749032 (-2.01 %) bytes
LDS: 11 -> 11 (0.00 %) blocks
Scratch: 12288 -> 12288 (0.00 %) bytes per wave

Totals from affected shaders:
SGPRS: 13264 -> 13072 (-1.45 %)
VGPRS: 8248 -> 8316 (0.82 %)
Code Size: 486320 -> 470992 (-3.15 %) bytes
LDS: 11 -> 11 (0.00 %) blocks
Scratch: 11264 -> 11264 (0.00 %) bytes per wave

Increases:
SGPRS: 6 (0.01 %)
VGPRS: 20 (0.02 %)
Code Size: 14 (0.01 %)
LDS: 0 (0.00 %)
Scratch: 0 (0.00 %)

Decreases:
SGPRS: 32 (0.03 %)
VGPRS: 8 (0.01 %)
Code Size: 244 (0.25 %)
LDS: 0 (0.00 %)
Scratch: 0 (0.00 %)

*** BY PERCENTAGE ***

Max Increase:

SGPRS: 32 -> 48 (50.00 %)
VGPRS: 12 -> 20 (66.67 %)
Code Size: 216 -> 224 (3.70 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave

Max Decrease:

SGPRS: 40 -> 32 (-20.00 %)
VGPRS: 16 -> 12 (-25.00 %)
Code Size: 368 -> 280 (-23.91 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave

*** BY UNIT ***

Max Increase:

SGPRS: 32 -> 48 (50.00 %)
VGPRS: 28 -> 36 (28.57 %)
Code Size: 39320 -> 40132 (2.07 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave

Max Decrease:

SGPRS: 72 -> 64 (-11.11 %)
VGPRS: 48 -> 40 (-16.67 %)
Code Size: 6272 -> 5852 (-6.70 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
9 years agoradeonsi: Add header and footer to shader stat dump
Tom Stellard [Mon, 13 Apr 2015 12:56:37 +0000 (12:56 +0000)]
radeonsi: Add header and footer to shader stat dump

This makes it easier to parse.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
9 years agoi965: Fix software primitive restart with indirect draws.
Kenneth Graunke [Sat, 11 Apr 2015 09:21:48 +0000 (02:21 -0700)]
i965: Fix software primitive restart with indirect draws.

new_prim was declared as a stack variable within a nested scope; we
tried to retain a pointer to that data beyond the scope, which is bogus.

GCC with -O1 eliminated most of the code that set new_prim's fields.

Move the declaration to fix the bug.

v2: Also fix new_ib (thanks to Matt Turner and Ben Widawsky).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81025
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Cc: mesa-stable@lists.freedesktop.org
9 years agoi965: Implement proper workaround for Gen4 GPU CONSTANT_BUFFER hangs.
Kenneth Graunke [Mon, 13 Apr 2015 01:39:07 +0000 (18:39 -0700)]
i965: Implement proper workaround for Gen4 GPU CONSTANT_BUFFER hangs.

I finally managed to dig up some information on our mysterious GPU hangs.
A wiki page from the Crestline validation team mentions that they found
a GPU hang in "Serious Sam 2" (on Windows) with remarkably similar
conditions to the ones we've seen in Google Chrome and glmark2.

Apparently, if WM_STATE has "PS Use Source Depth" enabled, CC_STATE has
most depth state disabled, and you issue a CONSTANT_BUFFER command and
immediately draw, the depth interpolator makes a small mistake that
leads to hangs.

Most of the traces I looked at contained a CONSTANT_BUFFER packet
immediately followed by 3DPRIMITIVE, or at least very few packets.
It appears they also have "PS Use Source Depth" enabled - either at the
hang, or a little before it.  So I think this is our bug.

The workaround is to emit a non-pipelined state packet after issuing a
CONSTANT_BUFFER packet.  This is really similar to the workaround I
developed in commit c4fd0c9052dd391d6f2e9bb8e6da209dfc7ef35b.

v2: Fix word-wrapping issues.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965: Fix INTEL_DEBUG=shader_time for SIMD8 VS.
Kenneth Graunke [Sun, 12 Apr 2015 10:52:39 +0000 (03:52 -0700)]
i965: Fix INTEL_DEBUG=shader_time for SIMD8 VS.

In commit 4ebeb71573ad44f7657810dc5dd2c9030e3e63db, I deleted the
emit_shader_time_end() call in emit_urb_writes().  But I failed to add
it to run_vs(), as I intended.  So no data was recorded at all.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agovc4: Add a blitter path using just the render thread.
Eric Anholt [Mon, 6 Apr 2015 22:12:58 +0000 (15:12 -0700)]
vc4: Add a blitter path using just the render thread.

This accelerates the path for generating the shadow tiled texture when
asked to sample from a raster texture (typical in glamor).

9 years agovc4: Allow submitting jobs with no bin CL in validation.
Eric Anholt [Thu, 9 Apr 2015 20:35:57 +0000 (13:35 -0700)]
vc4: Allow submitting jobs with no bin CL in validation.

For blitting, we want to fire off an RCL-only job.  This takes a bit of
tweaking in our validation and the simulator support (and corresponding
new code in the kernel).

9 years agovc4: Move the blit code to a separate file.
Eric Anholt [Thu, 9 Apr 2015 19:12:20 +0000 (12:12 -0700)]
vc4: Move the blit code to a separate file.

There will be other blit code showing up, and it seems like the place
you'd look.

9 years agovc4: Separate out a bit of code for submitting jobs to the kernel.
Eric Anholt [Mon, 6 Apr 2015 19:58:51 +0000 (12:58 -0700)]
vc4: Separate out a bit of code for submitting jobs to the kernel.

I want to be able to have multiple jobs being set up at the same time (for
example, a render job to do a little fixup blit in the course of doing a
render to the main FBO).

9 years agovc4: When asked to sample from a raster texture, make a shadow tiled copy.
Eric Anholt [Wed, 8 Apr 2015 19:49:24 +0000 (12:49 -0700)]
vc4: When asked to sample from a raster texture, make a shadow tiled copy.

So, it turns out my simulator doesn't *quite* match the hardware.  And the
errata about raster textures tells you most of what's wrong, but there's
still stuff wrong after that.  Instead, if we're asked to sample from
raster, we'll just blit it to a tiled temporary.

Raster textures should only be screen scanout, and word is that it's
faster to copy to tiled using the tiling engine first than to texture from
an entire raster texture, anyway.

9 years agovc4: Fix off-by-one in branch target validation.
Eric Anholt [Thu, 9 Apr 2015 20:43:55 +0000 (13:43 -0700)]
vc4: Fix off-by-one in branch target validation.

9 years agovc4: Use NIR-level lowering for idiv.
Eric Anholt [Mon, 13 Apr 2015 21:12:59 +0000 (14:12 -0700)]
vc4: Use NIR-level lowering for idiv.

This fixes the idiv tests in piglit.

9 years agovc4: Add a bunch of type conversions.
Eric Anholt [Wed, 1 Apr 2015 22:35:13 +0000 (15:35 -0700)]
vc4: Add a bunch of type conversions.

These are required to get piglit's idiv tests working.  The
unsigned<->float conversions are wrong, but are good enough to get
piglit's small ranges of values working.

9 years agost/mesa: align cube map arrays layers
Dave Airlie [Wed, 8 Apr 2015 00:00:27 +0000 (10:00 +1000)]
st/mesa: align cube map arrays layers

We create textures internally for texsubimage, and we use
the values from sub image to create a new texture, however
we don't align these to valid sizes, and cube map arrays
must have an array size aligned to 6.

This fixes texsubimage cube_map_array on CAYMAN at least,
(it was causing  GPU hang and bad values), it probably
also fixes it on radeonsi and evergreen.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89957
Tested-by: Tom Stellard <thomas.stellard@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
9 years agost/mesa: convert sub image for cube map arrays to 2d arrays for upload
Dave Airlie [Wed, 8 Apr 2015 00:59:20 +0000 (10:59 +1000)]
st/mesa: convert sub image for cube map arrays to 2d arrays for upload

Since we can subimage upload a number of cube map array layers,
that aren't a complete cube map array, we should specify things
as a 2D array and blit from that.

Suggested by Ilia Mirkin as an alternate fix for texsubimage
cube map array issues.

seems to work just as well.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
9 years agoi965: Flush batchbuffer containing the query on glQueryCounter.
Mathias Froehlich [Sun, 12 Apr 2015 16:23:58 +0000 (18:23 +0200)]
i965: Flush batchbuffer containing the query on glQueryCounter.

This change fixes a regression with timer queries introduced with
commit 3eb6258. There the pending batchbuffer is flushed
only if glEndQuery is executed. This present change adds such
a flush to glQueryCounter which also schedules a value query
just like glEndQuery does. The patch fixes GPU timer queries
going mad from within osgviewer.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
Cc: mesa-stable@lists.freedesktop.org
9 years agovc4: Use the blit interface for updating shadow textures.
Eric Anholt [Wed, 8 Apr 2015 20:11:01 +0000 (13:11 -0700)]
vc4: Use the blit interface for updating shadow textures.

This lets us plug in a better blit implementation and have it impact the
shadow update, too.

9 years agovc4: Remove dead fields from vc4_surface.
Eric Anholt [Thu, 9 Apr 2015 20:13:23 +0000 (13:13 -0700)]
vc4: Remove dead fields from vc4_surface.

9 years agovc4: Skip sending down the clear colors if not clearing.
Eric Anholt [Mon, 6 Apr 2015 22:19:30 +0000 (15:19 -0700)]
vc4: Skip sending down the clear colors if not clearing.

9 years agovc4: Sync with kernel changes to relax BCL versus RCL validation.
Eric Anholt [Thu, 9 Apr 2015 20:41:29 +0000 (13:41 -0700)]
vc4: Sync with kernel changes to relax BCL versus RCL validation.

There was no reason to tie the two packets' values together.

9 years agovc4: Fix another space allocation mistake.
Eric Anholt [Thu, 9 Apr 2015 20:05:00 +0000 (13:05 -0700)]
vc4: Fix another space allocation mistake.

We're over-allocating our BCL in vc4_draw.c, so this never mattered.
However, new RCL-only blit support might end up here without having set up
any BCL contents.

9 years agovc4: Add missed accounting for the size of the semaphore.
Eric Anholt [Mon, 6 Apr 2015 22:15:37 +0000 (15:15 -0700)]
vc4: Add missed accounting for the size of the semaphore.

This wouldn't have mattered except in the worst case scenario RCL setup.

9 years agoswrast: Mark MAX_GLUINT literal with u suffix.
Matt Turner [Sat, 11 Apr 2015 17:14:00 +0000 (10:14 -0700)]
swrast: Mark MAX_GLUINT literal with u suffix.

Coverity is confused by the "float < int / 2" expression and suggests
casting MAX_GLUINT to unsigned, which I believe it was supposed to have
been already.

Reviewed-by: Brian Paul <brianp@vmware.com>
9 years agoi965: Don't bother freeing NULL.
Matt Turner [Sat, 11 Apr 2015 17:05:31 +0000 (10:05 -0700)]
i965: Don't bother freeing NULL.

Commit e16c5c90 was replacing 'region' with 'mt', leaving this
nonsensical code.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965: Lift some restrictions on dma_buf EGLImages
Chad Versace [Fri, 10 Apr 2015 03:29:59 +0000 (20:29 -0700)]
i965: Lift some restrictions on dma_buf EGLImages

Allow glEGLImageTargetRenderbufferStorageOES and
glEGLImageTargetTexture2DOES for dma_buf EGLImages if the image is
a single RGBA8 unorm plane. This is safe, despite fast color clears,
because i965 disables allocation of auxiliary buffers for EGLImages.

Chrome OS needs this, because its compositor uses dma_buf EGLImages for
its scanout buffers.

Testing:
  - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
    YouTube.
  - No Piglit regressions on Broadwell with `piglit run -p gbm
    tests/quick.py`, with my Piglit patches that update the
    EGL_EXT_image_dma_buf_import tests.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
9 years agoi965: Disable aux buffers for EGLImage-backed miptrees
Chad Versace [Mon, 6 Apr 2015 15:07:27 +0000 (08:07 -0700)]
i965: Disable aux buffers for EGLImage-backed miptrees

EGL does not yet have extensions to manage the flushing and invalidating
of driver-internal aux buffers. So we must disable aux buffers of
dma_buf-backed EGLImages in order to safely render into them.

This patch is obviously needed for renderbufers. It's also needed for
textures because the user can attach the texture to a framebuffer and
because the driver sometimes renders to textures for internal reasons.

Testing:
  - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
    YouTube.
  - No Piglit regressions on Broadwell with `piglit run -p gbm
    tests/quick.py`.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
9 years agoi965: Change intel_miptree_create_for_bo() signature
Chad Versace [Mon, 6 Apr 2015 15:11:43 +0000 (08:11 -0700)]
i965: Change intel_miptree_create_for_bo() signature

Add parameter 'bool disable_aux_buffers'.

This is a refactor patch. The patch changes no behavior because the new
parameter is false in every call.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
9 years agoi965: Add field intel_mipmap_tree::disable_aux_buffers
Chad Versace [Mon, 6 Apr 2015 13:46:09 +0000 (06:46 -0700)]
i965: Add field intel_mipmap_tree::disable_aux_buffers

The new field disables allocation of auxiliary buffers, such as the HiZ
buffer and MCS buffer. This is useful for sharing the miptree bo with an
external client that doesn't understand auxiliary buffers.

We need this field to safely render to a buffer that was imported with
EGL_EXT_image_dma_buf_import, because EGL does not yet have extensions
to manage flushing and invalidating auxiliary buffers.

Nothing yet enables this field. That's left to follow-up patches.

Testing:
  - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
    YouTube.
  - No Piglit regressions on Broadwell with `piglit run -p gbm
    tests/quick.py`.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
9 years agoi965: Refactor brw_is_hiz_depth_format()
Chad Versace [Mon, 6 Apr 2015 13:54:30 +0000 (06:54 -0700)]
i965: Refactor brw_is_hiz_depth_format()

Every caller of this function uses it to determine if the current
miptree needs a hiz buffer to be allocated. Strangely, the function
doesn't take a miptree argument. So, this function effectively decides
if and when a miptree's hiz buffer gets allocated without inspecting the
miptree itself.  Luckily, the driver behaves correctly despite the
brw_is_hiz_depth_format's quirk.

I will soon make some changes to the miptree that will require
inspecting the miptree to determine if it needs a hiz buffer. So this
patch renames
    brw_is_hiz_depth_format -> intel_miptree_wants_hiz_buffer
and gives it a miptree parameter.

This patch shouldn't change any behavior.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
9 years agoi965: Declare intel_miptree_create_layout() as static
Chad Versace [Mon, 6 Apr 2015 14:13:53 +0000 (07:13 -0700)]
i965: Declare intel_miptree_create_layout() as static

It's not used outside intel_mipmap_tree.c.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
9 years agoi965: Declare intel_miptree_alloc_mcs() as static
Chad Versace [Mon, 6 Apr 2015 14:04:06 +0000 (07:04 -0700)]
i965: Declare intel_miptree_alloc_mcs() as static

It's not used outside of intel_mipmap_tree.c, nor should it ever be.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
9 years agodocs: Improve LLVM_USE_CRT_xxx instructions.
Jose Fonseca [Mon, 13 Apr 2015 12:08:13 +0000 (13:08 +0100)]
docs: Improve LLVM_USE_CRT_xxx instructions.

9 years agoglx: Include util/macros.h instead of redefining PRINTFLIKE.
Jose Fonseca [Thu, 2 Apr 2015 10:25:06 +0000 (11:25 +0100)]
glx: Include util/macros.h instead of redefining PRINTFLIKE.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
9 years agoutil/ralloc: Fix `extern "C"` usage.
Jose Fonseca [Thu, 2 Apr 2015 10:24:26 +0000 (11:24 +0100)]
util/ralloc: Fix `extern "C"` usage.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agomesa: Remove pointless USE_EXTERNAL_DXTN_LIB macro.
Jose Fonseca [Thu, 2 Apr 2015 09:09:38 +0000 (10:09 +0100)]
mesa: Remove pointless USE_EXTERNAL_DXTN_LIB macro.

I'm not sure what was the original intention, but currently
USE_EXTERNAL_DXTN_LIB always ends up defined, one way or another.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
9 years agodocs: add news item and link release notes for mesa 10.5.3
Emil Velikov [Sun, 12 Apr 2015 22:16:42 +0000 (23:16 +0100)]
docs: add news item and link release notes for mesa 10.5.3

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
9 years agodocs: Add 256 sums for the 10.5.3 release
Emil Velikov [Sun, 12 Apr 2015 22:10:42 +0000 (23:10 +0100)]
docs: Add 256 sums for the 10.5.3 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 65776421fe59a0ffd5388c0968c9b0b1c1b230ed)

9 years agoAdd release notes for the 10.5.3 release
Emil Velikov [Sun, 12 Apr 2015 21:29:06 +0000 (22:29 +0100)]
Add release notes for the 10.5.3 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit c4b8bff6e24c6661a8a05ec05f8ed5762e95021b)

9 years agodocs: remove the --with-max-{width,height} note
Emil Velikov [Thu, 2 Apr 2015 08:37:12 +0000 (08:37 +0000)]
docs: remove the --with-max-{width,height} note

Missed out with commit d99135b2e9b(configure: nuke
--with-max-{width,height})

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
9 years agoconfigure.ac: remove deprecated --with-libclc-path
Emil Velikov [Wed, 1 Apr 2015 16:46:09 +0000 (17:46 +0100)]
configure.ac: remove deprecated --with-libclc-path

The option was deprecated with commit 959e83d6507(clover: Adapt libclc's
INCLUDEDIR and LIBEXECDIR to make use of the new introduced libclc.pc.)
back in 2012 with mesa 9.2.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
9 years agoi965/nir: Make INTEL_DEBUG=ann work with NIR.
Kenneth Graunke [Sat, 24 Jan 2015 10:05:56 +0000 (02:05 -0800)]
i965/nir: Make INTEL_DEBUG=ann work with NIR.

Now that we store a copy of the NIR shader, and don't immediately free
it, we can use it in annotations as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
9 years agoi965: Create NIR during LinkShader() and ProgramStringNotify().
Kenneth Graunke [Tue, 7 Apr 2015 22:15:09 +0000 (15:15 -0700)]
i965: Create NIR during LinkShader() and ProgramStringNotify().

Previously, we translated into NIR and did all the optimizations and
lowering as part of running fs_visitor.  This meant that we did all of
that work twice for fragment shaders - once for SIMD8, and again for
SIMD16.  We also had to redo it every time we hit a state based
recompile.

We now generate NIR once at link time.  ARB programs don't have linking,
so we instead generate it at ProgramStringNotify time.

Mesa's fixed function vertex program handling doesn't bother to inform
the driver about new programs at all (which is rather mean), so we
generate NIR at the last minute, if it hasn't happened already.

shader-db runs ~9.4% faster on my i7-5600U, with a release build.

v2: Check NirOptions != NULL in ProgramStringNotify().  Don't bother
    using _mesa_program_enum_to_shader_stage as we already know it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Store num_direct_uniforms in the nir_shader.
Kenneth Graunke [Wed, 8 Apr 2015 00:13:45 +0000 (17:13 -0700)]
nir: Store num_direct_uniforms in the nir_shader.

Storing this here is pretty sketchy - I don't know if any driver other
than i965 will want to use it.  But this will make it a lot easier to
generate NIR code at link time.  We'll probably rework it anyway.

(Ian suggested making nir_assign_var_locations_scalar_direct_first
 simply modify the nir_shader's fields, rather than passing pointers
 to them.  If this stays long term, we should do that.  But Jason and
 I suspect we'll be reworking this area again in the near future.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965: Move lower_output_reads to brw_link_shader().
Kenneth Graunke [Tue, 7 Apr 2015 22:05:12 +0000 (15:05 -0700)]
i965: Move lower_output_reads to brw_link_shader().

This makes it so emit_nir_code() doesn't modify the GLSL IR.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
9 years agoglsl: Mark path as unreachable.
Matt Turner [Sat, 11 Apr 2015 17:11:13 +0000 (10:11 -0700)]
glsl: Mark path as unreachable.

9 years agoi965: Remove useless null check.
Matt Turner [Sat, 11 Apr 2015 16:54:38 +0000 (09:54 -0700)]
i965: Remove useless null check.

If it were null, we'd have just derefernced it two lines above.

9 years agoi965/fs/nir: Mark fallthrough.
Matt Turner [Sat, 11 Apr 2015 16:49:36 +0000 (09:49 -0700)]
i965/fs/nir: Mark fallthrough.

9 years agoi965: Remove useless reg_offset >= 0 tests.
Matt Turner [Sat, 11 Apr 2015 16:47:39 +0000 (09:47 -0700)]
i965: Remove useless reg_offset >= 0 tests.

Commit eb9bd3a1 changed the type of this field to uint16_t.

9 years agofreedreno/ir3/nir: couple little fixes
Rob Clark [Sat, 11 Apr 2015 14:04:50 +0000 (10:04 -0400)]
freedreno/ir3/nir: couple little fixes

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/nir: handle system values
Rob Clark [Fri, 10 Apr 2015 19:57:29 +0000 (15:57 -0400)]
freedreno/ir3/nir: handle system values

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/nir: handle txs and query_levels tex ops
Rob Clark [Fri, 10 Apr 2015 00:32:14 +0000 (20:32 -0400)]
freedreno/ir3/nir: handle txs and query_levels tex ops

These correspond to the tgsi TXQ opcode

(plus sneak in a fix for two-sided color)

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/nir: split out tex helpers
Rob Clark [Thu, 9 Apr 2015 20:44:38 +0000 (16:44 -0400)]
freedreno/ir3/nir: split out tex helpers

We'll need these in one or two other spots.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/nir: simplify emit_tex()
Rob Clark [Thu, 9 Apr 2015 16:55:49 +0000 (12:55 -0400)]
freedreno/ir3/nir: simplify emit_tex()

Just build up arrays for src0/src1, and use create_collect()..

Also add back missing .3d flag for 3d/cube textures.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/cp: handle indirect properly
Rob Clark [Wed, 8 Apr 2015 18:10:00 +0000 (14:10 -0400)]
freedreno/ir3/cp: handle indirect properly

I noticed some cases where we where trying to copy-propagate indirect
src's into places they cannot go, like 2nd src for cat3 (mad, etc).
Expand out valid_flags() to be aware of relativ flag, and fix up a few
related spots.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/sched: avoid getting stuck on addr conflicts
Rob Clark [Wed, 8 Apr 2015 15:04:37 +0000 (11:04 -0400)]
freedreno/ir3/sched: avoid getting stuck on addr conflicts

When we get in a scenario where we cannot schedule any more instructions
due to address register conflict, clone the instruction that writes the
address register, and switch the remaining unscheduled users for the
current address register over to the new clone.

This is simpler and more robust than the previous attempt (which tried
and sometimes failed to ensure all other dependencies of users of the
address register were scheduled first).. hint it would try to schedule
instructions that were not actually needed for any output value.

We probably need to do the same with predicate register, although so far
it isn't so heavily used so we aren't running into problems with it
(yet).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/nir: add variable-indexing support
Rob Clark [Wed, 8 Apr 2015 00:41:48 +0000 (20:41 -0400)]
freedreno/ir3/nir: add variable-indexing support

A bit fugly.. try and make this cleaner..  note if we hoist all the
get_addr() out of the loop we can drop the hashtable and just use
create_addr()..

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/asm: change assert to warning
Rob Clark [Mon, 6 Apr 2015 15:42:57 +0000 (11:42 -0400)]
freedreno/ir3/asm: change assert to warning

It probably *should* be an assert, but for now TGSI f/e isn't very good
about dealing w/ CONST vs ABS/NEG.  So for debug builds, print a warning
instead of crashing with an assert for now.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/nir: set first_driver_param
Rob Clark [Mon, 6 Apr 2015 14:54:30 +0000 (10:54 -0400)]
freedreno/ir3/nir: set first_driver_param

Without this, a3xx breaks.. a4xx would too if it had already implemented
support for passing driver params.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/cp: support to swap mad src's
Rob Clark [Mon, 6 Apr 2015 14:48:11 +0000 (10:48 -0400)]
freedreno/ir3/cp: support to swap mad src's

For a normal MAD (ie. not MADSH), if first source is gpr and second
source is const, we can swap the first two sources to avoid needing a
mov instruction.

This gives back the biggest advantage TGSI f/e had over NIR f/e for
common shaders, since TGSI f/e had this logic in the f/e.  Note that
doing this in copy-prop step has the advantage that it will also work
for cases like:

   MOV TEMP[b], CONST[x]
   MAD TEMP[d], TEMP[a], TEMP[b], TEMP[c]

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agonir: fix bit of cargo-culting in lower_idiv
Rob Clark [Fri, 10 Apr 2015 20:39:30 +0000 (16:39 -0400)]
nir: fix bit of cargo-culting in lower_idiv

I guess I was looking too much at how lower_system_values worked when
writing lower_idiv.

Since ttn wasn't emitting load_var for sysvals and the only drivers
using lower_idiv were using ttn, I think nothing was broken as a result.
But might as well fix this before it becomes a problem.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: split out lower_sub from lower_negate
Rob Clark [Sat, 4 Apr 2015 12:13:44 +0000 (08:13 -0400)]
nir: split out lower_sub from lower_negate

Originally you had to have one or the other.  But actually I don't want
either.  (Or rather I want whatever is the minimum # of instructions.)

TODO: not sure where the best place to insert a check that driver hasn't
set *both* lower_negate and lower_sub?

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agogallium/ttn: add support for system values
Rob Clark [Fri, 10 Apr 2015 19:01:16 +0000 (15:01 -0400)]
gallium/ttn: add support for system values

So far just the system values that freedreno supports, so we may add
more later.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agogallium/ttn: fix TXD
Rob Clark [Fri, 10 Apr 2015 18:19:22 +0000 (14:19 -0400)]
gallium/ttn: fix TXD

With TXD we also have the ddx/ddy sources (before the sampler).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agogallium/ttn: add TXQ support (v2)
Rob Clark [Thu, 9 Apr 2015 19:41:31 +0000 (15:41 -0400)]
gallium/ttn: add TXQ support (v2)

Split out from ttn_tex() since it is kind of a weird instruction that
maps to two NIR opcodes, and it was cleaner this way.

v2: query_levels doesn't take any args

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agogallium/ttn: split out helper to get texture info
Rob Clark [Thu, 9 Apr 2015 19:16:17 +0000 (15:16 -0400)]
gallium/ttn: split out helper to get texture info

We'll need this as well for TXQ.  Split this out first to reduce noise
in the next patch.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agogallium/ttn: add support for temp arrays
Rob Clark [Tue, 7 Apr 2015 15:38:23 +0000 (11:38 -0400)]
gallium/ttn: add support for temp arrays

Since the rest of NIR really would rather have these as variables rather
than registers, create a nir_variable per array.  But rather than
completely re-arrange ttn to be variable based rather than register
based, keep the registers.  In the cases where there is a matching var
for the reg, ttn_emit_instruction will append the appropriate intrinsic
to get things back from the shadow reg into the variable.

NOTE: this doesn't quite handle TEMP[ADDR[]] when the DCL doesn't give
an array id.  But those just kinda suck, and should really go away.
AFAICT we don't get those from glsl.  Might be an issue for some other
state tracker.

v2: rework to use load_var/store_var with deref chains
v3: create new "burner" reg for temporarily holding the (potentially
writemask'd) dest after each instruction; add load_var to initialize
temporary dest in case not all components are overwritten
v4: review comments: asserts and use ttn_src_for_indirect() in
ttn_array_deref() so we can drop later patch converting to use vec1 for
addr reg (since ttn_src_for_indirect() handles the imov to vec1 from
tgsi addr component that we want)
v5: rebase: new requirements about parent mem ctx for derefs

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agogallium/ttn: minor cleanup
Rob Clark [Wed, 8 Apr 2015 17:17:30 +0000 (13:17 -0400)]
gallium/ttn: minor cleanup

Extract tgsi_dst->Index into a local.. split out from 'gallium/ttn: add
support for temp arrays' for noise reduction..

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agoi965: Use NIR by default for fragment shaders
Jason Ekstrand [Fri, 10 Apr 2015 23:24:11 +0000 (16:24 -0700)]
i965: Use NIR by default for fragment shaders

GLSL IR vs. NIR shader-db results on i965:

   total instructions in shared programs: 2889747 -> 2890782 (0.04%)
   instructions in affected programs:     2425446 -> 2426481 (0.04%)
   helped:                                3698
   HURT:                                  5341

GLSL IR vs. NIR shader-db results on g4x:

   total instructions in shared programs: 2547252 -> 2550440 (0.13%)
   instructions in affected programs:     1984482 -> 1987670 (0.16%)
   helped:                                2844
   HURT:                                  4776

GLSL IR vs. NIR shader-db results on Iron Lake:

   total instructions in shared programs: 4053381 -> 4063828 (0.26%)
   instructions in affected programs:     3026601 -> 3037048 (0.35%)
   helped:                                4110
   HURT:                                  8331
   GAINED:                                1287
   LOST:                                  9

GLSL IR vs. NIR shader-db results on Sandy Bridge:

   total instructions in shared programs: 5307041 -> 5236666 (-1.33%)
   instructions in affected programs:     3442908 -> 3372533 (-2.04%)
   helped:                                11829
   HURT:                                  5604
   GAINED:                                33
   LOST:                                  18

GLSL IR vs. NIR shader-db results on Ivy Bridge:

   total instructions in shared programs: 4926333 -> 4857017 (-1.41%)
   instructions in affected programs:     3144042 -> 3074726 (-2.20%)
   helped:                                11559
   HURT:                                  4774
   GAINED:                                46
   LOST:                                  25

GLSL IR vs. NIR shader-db results on Bay Trail:

   total instructions in shared programs: 4926333 -> 4857017 (-1.41%)
   instructions in affected programs:     3144042 -> 3074726 (-2.20%)
   helped:                                11559
   HURT:                                  4774
   GAINED:                                46
   LOST:                                  25

GLSL IR vs. NIR shader-db results on Haswell:

   total instructions in shared programs: 4392487 -> 4293476 (-2.25%)
   instructions in affected programs:     2800180 -> 2701169 (-3.54%)
   helped:                                13073
   HURT:                                  3383
   GAINED:                                46
   LOST:                                  23

GLSL IR vs. NIR shader-db results on Broadwell (FS only):

   total instructions in shared programs: 4378113 -> 4283025 (-2.17%)
   instructions in affected programs:     2743209 -> 2648121 (-3.47%)
   helped:                                12470
   HURT:                                  3609
   GAINED:                                64
   LOST:                                  27

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Don't set NirOptions for stages that will use the vec4 backend.
Kenneth Graunke [Fri, 10 Apr 2015 06:26:49 +0000 (23:26 -0700)]
i965: Don't set NirOptions for stages that will use the vec4 backend.

We've started using NirOptions != NULL to mean "we're using NIR for this
stage."  However, when INTEL_USE_NIR=1, we set it for a bunch of stages
that still use the vec4 backend, and thus definitely aren't using NIR.

For example, if INTEL_USE_NIR=1 we disable the GLSL IR cubemap
normalization pass, even for vertex shaders and geometry shaders.  This
is wrong, but breaks a very uncommon case.

When I started deleting GLSL IR for stages where we claimed to be using
NIR, this bug quickly became apparent.

For now, only set it for fragment shaders, and vertex shaders if
brw->scalar_vs is set.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>