Andreas Sandberg [Wed, 18 Sep 2013 15:08:35 +0000 (17:08 +0200)]
sim: Fix undefined behavior in the pseudo-inst interface
The order between updating and using arg_num in
PseudoInst::pseudoInst() is currently undefined. This changeset
explicitly updates arg_num after it has been used to extract an
argument.
--HG--
extra : rebase_source :
67c46dc3333d16ce56687ee8aea41ce6c6d133bb
Andreas Hansson [Wed, 18 Sep 2013 12:46:33 +0000 (08:46 -0400)]
mem: Fix scheduling bug in SimpleMemory
This patch ensures that a dequeue event is not scheduled if the memory
controller is waiting for a retry already. Without this check it is
possible for the controller to attempt sending something whilst
already having one packet that is in retry, thus causing the bus to
have an assertion failure.
Andreas Hansson [Wed, 18 Sep 2013 12:46:32 +0000 (08:46 -0400)]
swig: Warn on use of incompatible swig/gcc combinations
This patch removes the fixed swig warning concerning 2.0.9/2.0.10 and
adds a warning message for incompatible combinations of swig and gcc.
Andreas Hansson [Wed, 18 Sep 2013 12:46:31 +0000 (08:46 -0400)]
swig: Fix issue with circular import in 2.0.9/2.0.10
This patch fixes an issue which prevented gem5 from running when built
using swig 2.0.9 and 2.0.10. The generated event.py tried to import
m5.internal which in turn relied on importing event. This patch seems
to fix the problem, and so far has not caused any other issues.
Andreas Sandberg [Wed, 18 Sep 2013 09:28:28 +0000 (11:28 +0200)]
x86: Expose the raw hash map of MSRs
This patch allows the KVM CPU module to initialize it's MSRs by
enumerating the MSRs in the gem5 x86 implementation.
Andreas Sandberg [Wed, 18 Sep 2013 09:28:27 +0000 (11:28 +0200)]
x86: Add support for checking the raw state of an interrupt
In order to support hardware virtualization, we need to be able to
check if there are any interrupts pending irregardless of the
rflags.intf value. This changeset adds the checkInterruptsRaw() method
to the x86 interrupt control. It returns true if there are pending
interrupts that can be delivered as soon as the CPU is ready for
interrupt delivery.
Andreas Sandberg [Wed, 18 Sep 2013 09:28:24 +0000 (11:28 +0200)]
x86: Expose the interrupt vector in faults
This patch allows a hardware virtualized CPU to discover which interrupt
to deliver to the guest.
Joel Hestness [Wed, 18 Sep 2013 00:39:11 +0000 (19:39 -0500)]
configs: Fix ruby_fs.py cache line size
Recent changes added setting of system-wide cache line size and these settings
occur in the top-level configs (se.py and fs.py). This setting also needs to
take place in ruby_fs.py. This change sets the cache line size as appropriate.
Nilay Vaish [Sun, 15 Sep 2013 18:45:59 +0000 (13:45 -0500)]
stats: update sparc fs due to recent changes to memory class.
Andreas Hansson [Thu, 12 Sep 2013 21:49:12 +0000 (17:49 -0400)]
config: Add voltage domain to Ruby example scripts
This patch adds the minimum required voltage domain configuration to
the Ruby example scripts.
Joel Hestness [Wed, 11 Sep 2013 20:35:18 +0000 (15:35 -0500)]
ruby: Fix Topology throttle connections
The Topology source sets up input and output buffers for each of the external
nodes of a topology by indexing on Ruby's generated controller unique IDs.
These unique IDs are found by adding the MachineType_base_number to the version
number of each controller (see any generated *_Controller.cc - init() calls
getToNetQueue and getFromNetQueue using m_version + base). However, the
Topology object used the cntrl_id - which is required to be unique across all
controllers - to index the controllers list as they are being connected to
their input and output buffers. If the cntrl_ids did not match the Ruby unique
ID, the throttles end up connected to incorrectly indexed nodes in the network,
resulting in packets traversing incorrect network paths. This patch fixes the
Topology indexing scheme by using the Ruby unique ID to match that of the
SimpleNetwork buffer vectors.
Joel Hestness [Wed, 11 Sep 2013 20:34:50 +0000 (15:34 -0500)]
cpu: Dynamically instantiate O3 CPU LSQUnits
Previously, the LSQ would instantiate MaxThreads LSQUnits in the body of it's
object, but it would only initialize numThreads LSQUnits as specified by the
user. This had the effect of leaving some LSQUnits uninitialized when the
number of threads was less than MaxThreads, and when adding statistics to the
LSQUnit that must be initialized, this caused the stats initialization check to
fail. By dynamically instantiating LSQUnits, they are all initialized and this
avoids uninitialized LSQUnits from floating around during runtime.
Joel Hestness [Wed, 11 Sep 2013 20:34:21 +0000 (15:34 -0500)]
config: Initialize and check cpt_starttick
The previous changeset (9816) that fixes the use of max ticks introduced the
variable cpt_starttick, which is used for setting the relative max tick.
Unfortunately, with checkpointing at an instruction count or with simpoints,
the checkpoint tick is not stored conveniently, so to ensure that cpt_starttick
is initialized, set it to 0. Also, if using --rel-max-tick, check the use of
instruction counts or simpoints to warn the user that the max tick setting does
not include the checkpoint ticks.
Joel Hestness [Wed, 11 Sep 2013 20:33:27 +0000 (15:33 -0500)]
ruby: Statically allocate stats in SimpleNetwork, Switch, Throttle
The previous changeset (9863:
9483739f83ee) used STL vector containers to
dynamically allocate stats in the Ruby SimpleNetwork, Switch and Throttle. For
gcc versions before at least 4.6.3, this causes the standard vector allocator
to call Stats copy constructors (a no-no, since stats should be allocated in
the body of each SimObject instance). Since the size of these stats arrays is
known at compile time (NOTE: after code generation), this patch changes their
allocation to be static rather than using an STL vector.
Nilay Vaish [Mon, 9 Sep 2013 23:52:23 +0000 (18:52 -0500)]
stats: add operator= for DataWrapVec class
gcc/g++ 4.4.7 complained about the operator= being undefined.
This changeset adds the operator.
Nilay Vaish [Fri, 6 Sep 2013 21:21:36 +0000 (16:21 -0500)]
stats: ruby: updates due to recent changes.
Nilay Vaish [Fri, 6 Sep 2013 21:21:35 +0000 (16:21 -0500)]
ruby: network: convert to gem5 style stats
Nilay Vaish [Fri, 6 Sep 2013 21:21:33 +0000 (16:21 -0500)]
ruby: network: correct naming of routers
The routers are created before the network class. This results in the routers
becoming children of the first link they are connected to and they get generic
names like int_node and node_b. This patch creates the network object first
and passes it to the topology creation function. Now the routers are children
of the network object and names are much more sensible.
Nilay Vaish [Fri, 6 Sep 2013 21:21:32 +0000 (16:21 -0500)]
ruby: profiler: removes function resourceUsage()
Nilay Vaish [Fri, 6 Sep 2013 21:21:30 +0000 (16:21 -0500)]
ruby: remove undefined message size type
This message size type does not work well with one of the statistical
variables. It also seems unnecessary.
Nilay Vaish [Fri, 6 Sep 2013 21:21:30 +0000 (16:21 -0500)]
ruby: network: removes reset functionality
Nilay Vaish [Fri, 6 Sep 2013 21:21:29 +0000 (16:21 -0500)]
ruby: network: shorten variable names
Nilay Vaish [Fri, 6 Sep 2013 21:21:29 +0000 (16:21 -0500)]
stats: adds a Formula operator for division
Nilay Vaish [Fri, 6 Sep 2013 21:21:28 +0000 (16:21 -0500)]
ruby: converts sparse memory stats to gem5 style
Andreas Hansson [Thu, 5 Sep 2013 17:53:54 +0000 (13:53 -0400)]
sim: Fix clang warning for unused variable
This patch ensures the NULL ISA can build without causing issues with
an unused variable.
Andreas Hansson [Wed, 4 Sep 2013 17:23:00 +0000 (13:23 -0400)]
util: Add ini string as tooltip info in dot output
This patch adds the config ini string as a tooltip that can be
displayed in most browsers rendering the resulting svg. Certain
characters are modified for HTML output.
Tested on chrome and firefox.
Andreas Hansson [Wed, 4 Sep 2013 17:22:59 +0000 (13:22 -0400)]
util: Add colours to the dot output
This patch is adding a splash of colour to the dot output to make it
easier to distinguish objects of different types. As a bonus, the
pastel-colour palette also makes the output look like a something from
the 21st century.
Andreas Hansson [Wed, 4 Sep 2013 17:22:58 +0000 (13:22 -0400)]
util: Add class name to dot graph and output to svg
This patch adds the class name to the label, creates some more space
by increasing the rank separation, and additionally outputs the graph
as an editable SVG in addition to the PDF.
Andreas Hansson [Wed, 4 Sep 2013 17:22:57 +0000 (13:22 -0400)]
tests: Move ISA-independent tests to the NULL ISA
This patch simply takes a first step to use the NULL ISA build for
tests that do not make use of a CPU. Most of the Ruby tests could go
the same way, but to avoid duplicating a lot of compilation targets
that will have to wait until Ruby is built as a library and linked in
independently.
--HG--
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/null/none/memtest/simerr
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/null/none/memtest/simout
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simerr
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
Andreas Hansson [Wed, 4 Sep 2013 17:22:57 +0000 (13:22 -0400)]
arch: Resurrect the NOISA build target and rename it NULL
This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.
The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.
--HG--
rename : build_opts/NOISA => build_opts/NULL
rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts
rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh
rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
Andreas Hansson [Wed, 4 Sep 2013 17:22:56 +0000 (13:22 -0400)]
cpu: Move the branch predictor out of the BaseCPU
The branch predictor is guarded by having either the in-order or
out-of-order CPU as one of the available CPU models and therefore
should not be used in the BaseCPU. This patch moves the parameter to
the relevant CPU classes.
Andreas Hansson [Wed, 4 Sep 2013 17:22:55 +0000 (13:22 -0400)]
arch: Header clean up for NOISA resurrection
This patch is a first step to getting NOISA working again. A number of
redundant includes make life more difficult than it has to be and this
patch simply removes them. There are also some redundant forward
declarations removed.
Andreas Hansson [Wed, 4 Sep 2013 17:22:55 +0000 (13:22 -0400)]
alpha: Move system virtProxy to Alpha only
This patch moves the system virtual port proxy to the Alpha system
only to make the resurrection of the NOISA slightly less
painful. Alpha is the only ISA that is actually using it.
Andreas Hansson [Wed, 4 Sep 2013 17:22:54 +0000 (13:22 -0400)]
scons: Enable build on OSX
This patch changes the SConscript to build gem5 with libc++ on OSX as
the conventional libstdc++ does not have the C++11 constructs that the
current code base makes use of (e.g. std::forward).
Since this was the last use of the transitional TR1, the unordered map
and set header can now be simplified as well.
Ali Saidi [Mon, 26 Aug 2013 15:58:06 +0000 (10:58 -0500)]
ARM: Fix configuration files for bare-metal binaries.
Steve Reinhardt [Sat, 24 Aug 2013 16:03:10 +0000 (12:03 -0400)]
stats: update eio stats
Steve Reinhardt [Thu, 22 Aug 2013 00:31:08 +0000 (17:31 -0700)]
util/regress: set --no-lto on regressions
See comment for motivation.
Nilay Vaish [Tue, 20 Aug 2013 16:32:33 +0000 (11:32 -0500)]
stats: update ruby.stats, config.ini files for x86 fs test
Nilay Vaish [Tue, 20 Aug 2013 16:32:31 +0000 (11:32 -0500)]
ruby: add option for number of transitions per cycle
The number of transitions per cycle that a controller can carry out is
a proxy for the number of ports that a controller has. This value is
currently 32 which is way too high. The patch introduces an option
for the number of ports and uses this option in the protocol files
to set the number of transitions. The default value is being set to
4. None of the se regressions change. Ruby stats for the fs regression
change and are being updated.
Andreas Hansson [Tue, 20 Aug 2013 15:21:27 +0000 (11:21 -0400)]
cpu: Fix timing CPU isDrained comment formatting
This patch fixes up the comment formatting for isDrained in the timing
CPU.
Andreas Hansson [Tue, 20 Aug 2013 15:21:26 +0000 (11:21 -0400)]
base: Fix VectorPrint initialisation
This patch changes how the initialisation of the VectorPrint struct is
done so that gcc 4.4 is happy again.
Andreas Hansson [Mon, 19 Aug 2013 07:52:36 +0000 (03:52 -0400)]
stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.
The main reason for bundling them up is to minimise the changeset
size.
Lena Olson [Mon, 19 Aug 2013 07:52:35 +0000 (03:52 -0400)]
cpu: Accurately count idle cycles for simple cpu
Added a couple missing updates to the notIdleFraction stat. Without
these, it sometimes gives a (not) idle fraction that is greater than 1
or less than 0.
Andreas Hansson [Mon, 19 Aug 2013 07:52:34 +0000 (03:52 -0400)]
config: Command line support for multi-channel memory
This patch adds support for specifying multi-channel memory
configurations on the command line, e.g. 'se/fs.py
--mem-type=ddr3_1600_x64 --mem-channels=4'. To enable this, it
enhances the functionality of MemConfig and moves the existing
makeMultiChannel class method from SimpleDRAM to the support scripts.
The se/fs.py example scripts are updated to make use of the new
feature.
Andreas Hansson [Mon, 19 Aug 2013 07:52:33 +0000 (03:52 -0400)]
mem: Change AbstractMemory defaults to match the common case
This patch changes the default parameter value of conf_table_reported
to match the common case. It also simplifies the regression and config
scripts to reflect this change.
Sascha Bischoff [Mon, 19 Aug 2013 07:52:32 +0000 (03:52 -0400)]
cpu: Fix TrafficGen trace playback
This patch addresses an issue with trace playback in the TrafficGen
where the trace was reset but the header was not read from the trace
when a captured trace was played back for a second time. This resulted
in parsing errors as the expected message was not found in the trace
file.
The header check is moved to an init funtion which is called by the
constructor and when the trace is reset. This ensures that the trace
header is read each time when the trace is replayed.
This patch also addresses a small formatting issue in a panic.
Andreas Hansson [Mon, 19 Aug 2013 07:52:32 +0000 (03:52 -0400)]
mem: Use STL deque in favour of list for DRAM queues
This patch changes the data structure used for the DRAM read, write
and response queues from an STL list to deque. This optimisation is
based on the observation that the size is small (and fixed), and that
the structures are frequently iterated over in a linear fashion.
Andreas Hansson [Mon, 19 Aug 2013 07:52:31 +0000 (03:52 -0400)]
mem: Perform write merging in the DRAM write queue
This patch implements basic write merging in the DRAM to avoid
redundant bursts. When a new access is added to the queue it is
compared against the existing entries, and if it is either
intersecting or immediately succeeding/preceeding an existing item it
is merged.
There is currently no attempt made at avoiding iterating over the
existing items in determining whether merging is possible or not.
Amin Farmahini [Mon, 19 Aug 2013 07:52:30 +0000 (03:52 -0400)]
mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAM
This patch gets rid of bytesPerCacheLine parameter and makes the DRAM
configuration separate from cache line size. Instead of
bytesPerCacheLine, we define a parameter for the DRAM called
burst_length. The burst_length parameter shows the length of a DRAM
device burst in bits. Also, lines_per_rowbuffer is replaced with
device_rowbuffer_size to improve code portablity.
This patch adds a burst length in beats for each memory type, an
interface width for each memory type, and the memory controller model
is extended to reason about "system" packets vs "dram" packets and
assemble the responses properly. It means that system packets larger
than a full burst are split into multiple dram packets.
Andreas Hansson [Mon, 19 Aug 2013 07:52:30 +0000 (03:52 -0400)]
cpu: Fix timing CPU drain check
This patch modifies the SimpleTimingCPU drain check to also consider
the fetch event. Previously, there was an assumption that there is
never a fetch event scheduled if the CPU is not executing
microcode. However, when a context is activated, a fetch even is
scheduled, and microPC() is zero.
Andreas Hansson [Mon, 19 Aug 2013 07:52:29 +0000 (03:52 -0400)]
alpha: Check interrupts before quiesce
This patch adds a check to the quiesce operation to ensure that the
CPU does not suspend itself when there are unmasked interrupts
pending. Without this patch there are corner cases when the CPU gets
an interrupt before the quiesce is executed and then never wakes up
again.
Sascha Bischoff [Mon, 19 Aug 2013 07:52:29 +0000 (03:52 -0400)]
stats: Fix issue when printing 2D vectors
This patch addresses an issue with the text-based stats output which
resulted in Vector2D stats being printed without subnames in the event
that one of the dimensions was of length 1.
This patch also fixes the total printing for the 2D vector. Previously
totals were printed without explicitly stating that a total was being
printed. This has been rectified in this patch.
Akash Bagdia [Mon, 19 Aug 2013 07:52:28 +0000 (03:52 -0400)]
power: Add voltage domains to the clock domains
This patch adds the notion of voltage domains, and groups clock
domains that operate under the same voltage (i.e. power supply) into
domains. Each clock domain is required to be associated with a voltage
domain, and the latter requires the voltage to be explicitly set.
A voltage domain is an independently controllable voltage supply being
provided to section of the design. Thus, if you wish to perform
dynamic voltage scaling on a CPU, its clock domain should be
associated with a separate voltage domain.
The current implementation of the voltage domain does not take into
consideration cases where there are derived voltage domains running at
ratio of native voltage domains, as with the case where there can be
on-chip buck/boost (charge pumps) voltage regulation logic.
The regression and configuration scripts are updated with a generic
voltage domain for the system, and one for the CPUs.
Andreas Hansson [Mon, 19 Aug 2013 07:52:27 +0000 (03:52 -0400)]
config: Move the memory instantiation outside FSConfig
This patch moves the instantiation of the memory controller outside
FSConfig and instead relies on the mem_ranges to pass the information
to the caller (e.g. fs.py or one of the regression scripts). The main
motivation for this change is to expose the structural composition of
the memory system and allow more tuning and configuration without
adding a large number of options to the makeSystem functions.
The patch updates the relevant example scripts to maintain the current
functionality. As the order that ports are connected to the memory bus
changes (in certain regresisons), some bus stats are shuffled
around. For example, what used to be layer 0 is now layer 1.
Going forward, options will be added to support the addition of
multi-channel memory controllers.
Andreas Hansson [Mon, 19 Aug 2013 07:52:26 +0000 (03:52 -0400)]
mem: Warn instead of panic for tXAW violation
Until the performance bug is fixed, avoid killing simulations.
Andreas Hansson [Mon, 19 Aug 2013 07:52:26 +0000 (03:52 -0400)]
mem: Allow disabling of tXAW through a 0 activation limit
This patch fixes an issue where an activation limit of 0 was not
allowed. With this patch, setting the limit to 0 simply disables the
tXAW constraint.
Andreas Hansson [Mon, 19 Aug 2013 07:52:25 +0000 (03:52 -0400)]
mem: Add an internal packet queue in SimpleMemory
This patch adds a packet queue in SimpleMemory to avoid using the
packet queue in the port (and thus have no involvement in the flow
control). The port queue was bound to 100 packets, and as the
SimpleMemory is modelling both a controller and an actual RAM, it
potentially has a large number of packets in flight. There is
currently no limit on the number of packets in the memory controller,
but this could easily be added in a follow-on patch.
As a result of the added internal storage, the functional access and
draining is updated. Some minor cleaning up and renaming has also been
done.
The memtest regression changes as a result of this patch and the stats
will be updated.
Andreas Hansson [Mon, 19 Aug 2013 07:52:24 +0000 (03:52 -0400)]
cpu: Fix a bug in the O3 CPU introduced by the cache line patch
This patch fixes a bug in the O3 fetch stage that was introduced when
the cache line size was moved to the system. By mistake, the
initialisation and resetting of the fetch stage was merged and put in
the constructor. The resetting is now re-added where it should be.
Anthony Gutierrez [Wed, 14 Aug 2013 14:51:47 +0000 (10:51 -0400)]
arm: use -march when compiling m5op_arm.S
Using arm-linux-gnueabi-gcc 4.7.3-1ubuntu1 on Ubuntu 13.04 to compiled
the m5 binary yields the error:
m5op_arm.S: Assembler messages:
m5op_arm.S:85: Error: selected processor does not support ARM mode `bxj lr'
For each of of the SIMPLE_OPs. Apparently, this compiler doesn't like the
interworking of these code types for the default arch. Adding -march=armv7-a
makes it compile. Another alternative that I found to work is replacing the
bxj lr instruction with mov pc, lr, but I don't know how that affects the
KVM stuff and if bxj is needed.
Nilay Vaish [Wed, 7 Aug 2013 19:51:18 +0000 (14:51 -0500)]
ruby: slicc: remove double trigger, continueProcessing
These constructs are not in use and are not being maintained by any one.
In addition, it is not known if doubleTrigger works correctly with Ruby now.
Nilay Vaish [Wed, 7 Aug 2013 19:51:18 +0000 (14:51 -0500)]
ruby: slicc: move some code to AbstractController
Some of the code in StateMachine.py file is added to all the controllers and
is independent of the controller definition. This code is being moved to the
AbstractController class which is the parent class of all controllers.
Nilay Vaish [Wed, 7 Aug 2013 19:51:17 +0000 (14:51 -0500)]
x86: add tlb checkpointing
This patch adds checkpointing support to x86 tlb. It upgrades the
cpt_upgrader.py script so that previously created checkpoints can
be updated. It moves the checkpoint version to 6.
Andreas Sandberg [Fri, 19 Jul 2013 09:52:07 +0000 (11:52 +0200)]
cpu: Remove unused getBranchPred() method from BaseCPU
Remove unused virtual getBranchPred() method from BaseCPU as it is not
implemented by any of the CPU models. It used to always return NULL.
Joel Hestness [Thu, 18 Jul 2013 19:46:54 +0000 (14:46 -0500)]
Configs: Fix up maxtick and maxtime
This patch contains three fixes to max tick options handling in Options.py and
Simulation.py:
1) Since the global simulator frequency isn't bound until m5.instantiate()
is called, the maxtick resolution needs to happen after this call, since
changes to the global frequency will cause m5.simulate() to misinterpret the
maxtick value. Shuffling this also requires tweaking the checkpoint directory
handling to signal the checkpoint restore tick back to run(). Fixing this
completely and correctly will require storing the simulation frequency into
checkpoints, which is beyond the scope of this patch.
2) The maxtick option in Options.py was defaulted to MaxTicks, so the old code
would always skip over the maxtime part of the conditionals at the beginning
of run(). Change the maxtick default to None, and set the maxtick local
variable in run() appropriately.
3) To clarify whether max ticks settings are relative or absolute, split the
maxtick option into separate options, for relative and absolute. Ensure that
these two options and the maxtime option are handled appropriately to set the
maxtick variable in Simulation.py.
Andreas Hansson [Thu, 18 Jul 2013 12:31:19 +0000 (08:31 -0400)]
config: Update script to set cache line size on system
This patch changes the config scripts such that they do not set the
cache line size per cache instance, but rather for the system as a
whole.
Andreas Hansson [Thu, 18 Jul 2013 12:31:16 +0000 (08:31 -0400)]
mem: Set the cache line size on a system level
This patch removes the notion of a peer block size and instead sets
the cache line size on the system level.
Previously the size was set per cache, and communicated through the
interconnect. There were plenty checks to ensure that everyone had the
same size specified, and these checks are now removed. Another benefit
that is not yet harnessed is that the cache line size is now known at
construction time, rather than after the port binding. Hence, the
block size can be locally stored and does not have to be queried every
time it is used.
A follow-on patch updates the configuration scripts accordingly.
Xiangyu Dong [Thu, 18 Jul 2013 12:29:47 +0000 (08:29 -0400)]
mem: Add cache class destructor to avoid memory leaks
Make valgrind a little bit happier
Andreas Hansson [Thu, 18 Jul 2013 12:29:28 +0000 (08:29 -0400)]
scons: Use python-config instead of distutils
This patch changes how we determine the Python-related compiler and
linker flags. The previous approach used the internal LINKFORSHARED
which is not intended as part of the external API
(http://bugs.python.org/issue3588) and causes failures on recent OSX
installations.
Instead of using distutils we now rely on python-config and scons
ParseConfig. For backwards compatibility we also parse out the
includes and libs although this could safely be dropped. The drawback
of this patch is that Python 2.5 is now required, but hopefully that
is an acceptable compromise as any system with gcc 4.4 most likely
will have Python >= 2.5.
Andreas Hansson [Thu, 18 Jul 2013 12:29:08 +0000 (08:29 -0400)]
sim: Make MaxTick in Python match the one in C++
This patch aligns the MaxTick in Python with the one in C++. Thus,
both reflect the maximum value that an unsigned 64-bit integer can
have.
Deyuan Guo [Mon, 15 Jul 2013 22:08:57 +0000 (18:08 -0400)]
loader: Load weak symbols for function tracing
Umesh Bhaskar [Mon, 15 Jul 2013 15:08:34 +0000 (11:08 -0400)]
debug : Fixes the issue wherein Debug symbols were not getting dumped into trace files for SE mode
Steve Reinhardt [Fri, 12 Jul 2013 02:57:04 +0000 (21:57 -0500)]
dev: make BasicPioDevice take size in constructor
Instead of relying on derived classes explicitly assigning
to the BasicPioDevice pioSize field, require them to pass
a size value in to the constructor.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Steve Reinhardt [Fri, 12 Jul 2013 02:56:50 +0000 (21:56 -0500)]
dev: consistently end device classes in 'Device'
PciDev and IntDev stuck out as the only device classes that
ended in 'Dev' rather than 'Device'. This patch takes care
of that inconsistency.
Note that you may need to delete pre-existing files matching
build/*/python/m5/internal/param_* as scons does not pick up
indirect dependencies on imported python modules when generating
params, and the PciDev -> PciDevice rename takes place in a
file (dev/Device.py) that gets imported quite a bit.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Steve Reinhardt [Fri, 12 Jul 2013 02:56:39 +0000 (21:56 -0500)]
dev/arm: get rid of AmbaDev namespace
It was confusing having an AmbaDev namespace along with an
AmbaDevice class. The namespace stuff is now moved in to
a new base AmbaDevice class, which is a mixin for classes
AmbaPioDevice (the former AmbaDevice) and AmbaDmaDevice
to provide the readId function as an inherited member function.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Steve Reinhardt [Fri, 12 Jul 2013 02:56:24 +0000 (21:56 -0500)]
devices: make more classes derive from BasicPioDevice
A couple of devices that have single fixed memory mapped regions
were not derived from BasicPioDevice, when that's exactly
the functionality that BasicPioDevice provides. This patch
gets rid of a little bit of redundant code by making those
devices actually do so.
Also fixed the weird case of X86ISA::Interrupts, where
the class already did derive from BasicPioDevice but
didn't actually use all the features it could have.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Brad Beckmann [Thu, 11 Jul 2013 18:56:05 +0000 (13:56 -0500)]
ruby: removed the very old double trigger hack
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Tue, 2 Jul 2013 15:11:00 +0000 (10:11 -0500)]
regressions: update a couple stats.txt
The statistics for 30.eio-mp, pc-simple-timing-ruby tests are being updated
to incorporate the changes due to recent patches.
Nilay Vaish [Tue, 2 Jul 2013 15:10:58 +0000 (10:10 -0500)]
regressions: update a couple of configs
The configs for pc-simple-timing-ruby, t1000-simple-atomic had not been
updated correctly in the patch
6e6cefc1db1f.
Nilay Vaish [Sat, 29 Jun 2013 02:42:27 +0000 (21:42 -0500)]
ruby: append transition comment only when in opt/debug
Nilay Vaish [Sat, 29 Jun 2013 02:42:26 +0000 (21:42 -0500)]
configs: rearrange the available options in Options.py
It also changes the instantiation of physmem in se.py so as to make
use of the memory size supplied by the mem_size option.
Nilay Vaish [Sat, 29 Jun 2013 02:36:37 +0000 (21:36 -0500)]
ruby: network: remove reconfiguration code
This code seems not to be of any use now. There is no path in the simulator
that allows for reconfiguring the network. A better approach would be to
take a checkpoint and start the simulation from the checkpoint with the new
configuration.
Nilay Vaish [Sat, 29 Jun 2013 02:36:11 +0000 (21:36 -0500)]
ruby: check for compatibility between mem size and num dirs
The configuration scripts provided for ruby assume that the available
physical memory is equally distributed amongst the directory controllers.
But there is no check to ensure this assumption has been adhered to. This
patch adds the required check.
Andreas Hansson [Thu, 27 Jun 2013 09:49:51 +0000 (05:49 -0400)]
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Prakash Ramrakhyani [Thu, 27 Jun 2013 09:49:50 +0000 (05:49 -0400)]
mem: Reorganize cache tags and make them a SimObject
This patch reorganizes the cache tags to allow more flexibility to
implement new replacement policies. The base tags class is now a
clocked object so that derived classes can use a clock if they need
one. Also having deriving from SimObject allows specialized Tag
classes to be swapped in/out in .py files.
The cache set is now templatized to allow it to contain customized
cache blocks with additional informaiton. This involved moving code to
the .hh file and removing cacheset.cc.
The statistics belonging to the cache tags are now including ".tags"
in their name. Hence, the stats need an update to reflect the change
in naming.
Andreas Hansson [Thu, 27 Jun 2013 09:49:50 +0000 (05:49 -0400)]
mem: Remove the cache builder
This patch removes the redundant cache builder class.
Andreas Hansson [Thu, 27 Jun 2013 09:49:50 +0000 (05:49 -0400)]
config: Remove Clock parameter multiplication
This patch removes the multiplication operator support for Clock
parameters as this functionality is now achieved by creating derived
clock domains.
Nate, this one is for you.
Akash Bagdia [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
Andreas Hansson [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
config: Add a BaseSESystem builder for re-use in regressions
This patch extends the existing system builders to also include a
syscall-emulation builder. This builder is deployed in all
syscall-emulation regressions that do not involve Ruby,
i.e. o3-timing, simple-timing and simple-atomic, as well as the
multi-processor regressions o3-timing-mp, simple-timing-mp and
simple-atomic-mp (the latter are only used by SPARC at this point).
The values chosen for the cache sizes match those that were used in
the existing config scripts (despite being on the large
side). Similarly, a mem_class parameter is added to the builder base
class to enable simple-atomic to use SimpleMemory and o3-timing to use
the default DDR3 configuration.
Due to the different order the ports are connected, the bus stats get
shuffled around for the multi-processor regressions. A separate patch
bumps the port indices. Besides this, all behaviour is exactly the
same.
Akash Bagdia [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
config: Rename clock option to Ruby clock
This patch changes the 'clock' option to 'ruby-clock' as it is only
used by Ruby.
Akash Bagdia [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
config: Add a system clock command-line option
This patch adds a 'sys_clock' command-line option and use it to assign
clocks to the system during instantiation.
As part of this change, the default clock in the System class is
removed and whenever a system is instantiated a system clock value
must be set. A default value is provided for the command-line option.
The configs and tests are updated accordingly.
Akash Bagdia [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
config: Add a CPU clock command-line option
This patch adds a 'cpu_clock' command-line option and uses the value
to assign clocks to components running at the CPU speed (L1 and L2
including the L2-bus). The configuration scripts are updated
accordingly.
The 'clock' option is left unchanged in this patch as it is still used
by a number of components. In follow-on patches the latter will be
disambiguated further.
Akash Bagdia [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.
The main motivation for these simplifications is to ease the
introduction of clock domains.
Andreas Hansson [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
tests: Prune 00.gzip from the regressions
This patch prunes the 00.gzip regressions with the main motivation
being that it adds little (or no) coverage and requires a substantial
amount of run time.
A complete regression run, including compilation from a clean repo, is
almost 20% faster(!).
Andreas Hansson [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
mem: Tidy up the bridge with const and additional checks
This patch does a bit of tidying up in the bridge code, adding const
where appropriate and also removing redundant checks and adding a few
new ones.
There are no changes to the behaviour of any regressions.
Andreas Hansson [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
mem: Fix CommMonitor style and response check
This patch fixes the CommMonitor local variable names, and also
introduces a variable to capture if it expects to see a response. The
latter check considers both needsResponse and memInhibitAsserted.
Andreas Hansson [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
mem: Align cache timing to clock edges
This patch changes the cache timing calculations such that the results
are aligned to clock edges.
Plenty stats change as a results of this patch.
Andreas Hansson [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
cpu: Consider instructions waiting for FU completion in draining
This patch changes the IEW drain check to include the FU pool as there
can be instructions that are "stored" in FU completion events and thus
not covered by the existing checks. With this patch, we simply include
a check to see if all the FUs are considered non-busy in the next
tick.
Without this patch, the pc-switcheroo-full regression fails after
minor changes to the cache timing (aligning to clock edge).
Andreas Hansson [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
mem: Cycles converted to Ticks in atomic cache accesses
This patch fixes an outstanding issue in the cache timing calculations
where an atomic access returned a time in Cycles, but the port
forwarded it on as if it was in Ticks.
A separate patch will update the regression stats.
Andreas Hansson [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
scons: Identify runs that fail and runs with stats differences
This patch changes the regression script such that it is possible to
identify the runs that fail with an exit code, and those that finish
with stats differences. The ones that truly fail are reported as
FAILED, and those that finish with changed stats as CHANGED.
The yellow colour has been reclaimed from the skipped regressions and
is now used for the changed ones. With no obvious good option left the
skipped ones are now in cyan.
While I was editing the script I also bumped any occurence of M5 to
gem5.
Andreas Hansson [Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)]
base: Fix address range granularity calculation
This patch fixes a bug in the granularity calculation. For example, if
the high bit is 6 (counting from 0) and we have one interleaving bit,
then the granularity is now 2 ** (6 - 1 + 1) = 64.