Eric Engestrom [Fri, 22 May 2020 19:20:19 +0000 (21:20 +0200)]
docs: drop no-longer-relevant comment about bugzilla
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5172>
Eric Engestrom [Tue, 19 May 2020 23:02:52 +0000 (01:02 +0200)]
tree-wide: fix deprecated GitLab URLs
They will stop working in the next GitLab release, so let's update them
ASAP to make sure things are propagated to everyone by then.
See:
https://about.gitlab.com/releases/2020/05/06/gitlab-com-13-0-breaking-changes/#removal-of-deprecated-project-paths
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5111>
Marek Olšák [Tue, 19 May 2020 23:30:54 +0000 (19:30 -0400)]
radeonsi/gfx8: enable TC-compatible HTILE from the beginning as before
Fixes: 0d83e7f4b98 - radeonsi: enable TC-compatible HTILE on demand for best Z/S performance
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2921
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2967
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
Marek Olšák [Tue, 19 May 2020 23:29:21 +0000 (19:29 -0400)]
radeonsi: don't enable TC-compatible HTILE for stencil if stencil doesn't use it
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
Marek Olšák [Fri, 13 Mar 2020 23:28:58 +0000 (19:28 -0400)]
radeonsi: split si_all_descriptors_begin_new_cs and rename functions
A future commit will extend it.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
Marek Olšák [Tue, 10 Mar 2020 22:40:44 +0000 (18:40 -0400)]
radeonsi: move resetting tracked registers into a new function
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
Marek Olšák [Wed, 5 Feb 2020 21:55:41 +0000 (16:55 -0500)]
ac: update register and packet definitions for preemption
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
Marek Olšák [Tue, 19 May 2020 22:31:55 +0000 (18:31 -0400)]
Revert "radeonsi: don't wait for idle at the end of gfx IBs"
This reverts commit
266fec1307b26a544007423582afd8618791893c.
The kernel doesn't wait for idle as part of implicit sync.
Fixes: 266fec1307b26a544007423582afd8618791893c
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2950
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
Marek Olšák [Tue, 19 May 2020 01:55:06 +0000 (21:55 -0400)]
radeonsi: decrease the max GS invocation count to 32
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
Marek Olšák [Tue, 19 May 2020 03:14:03 +0000 (23:14 -0400)]
radeonsi: don't use INDIRECT_BUFFER within IBs
It's fragile. If I change the size or alignment, it hangs. Better safe than
sorry.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
Marek Olšák [Tue, 19 May 2020 05:32:38 +0000 (01:32 -0400)]
ac/surface: don't compute single-sample CMASK if it's unaligned
Displayable DCC can cause this and fail the assertion later.
Fixes: cf61f635ff6a38aad344ebe30551eaaac6fec038
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
Marek Olšák [Sun, 17 May 2020 06:38:02 +0000 (02:38 -0400)]
ac/gpu_info: compute the best safe IB alignment
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
Kristian H. Kristensen [Fri, 22 May 2020 22:03:55 +0000 (15:03 -0700)]
freedreno: Use the right amount of &'s
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5176>
Vinson Lee [Fri, 22 May 2020 18:22:19 +0000 (11:22 -0700)]
freedreno: Add missing break statement.
Reported-by: Coverity Scan
Fixes: 5a6beb6a24aa ("freedreno: add adreno 650")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5169>
Jason Ekstrand [Tue, 28 May 2019 19:40:35 +0000 (14:40 -0500)]
nir/copy_prop_vars: Record progress in more places
Fixes: 96c32d7776 "nir/copy_prop_vars: handle load/store of vector..."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5170>
Jason Ekstrand [Sat, 25 May 2019 04:29:15 +0000 (23:29 -0500)]
nir/opt_deref: Report progress if we remove a deref
Fixes: a1c688517de "nir/opt_deref: Properly optimize ptr_as_array..."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5170>
Jason Ekstrand [Fri, 24 May 2019 14:05:32 +0000 (09:05 -0500)]
nir/lower_double_ops: Rework the if (progress) tree
Fixes: d7d35a9522 "nir/lower_doubles: Use the new NIR lowering..."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5170>
Thong Thai [Thu, 21 May 2020 23:40:13 +0000 (19:40 -0400)]
frontends/va: Fix deinterlace bottom field first flag
Fixes an issue with mpv, where deinterlacing causes the picture to be
offset by one line every other frame in the video.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5157>
Alyssa Rosenzweig [Fri, 15 May 2020 20:24:45 +0000 (16:24 -0400)]
pan/mdg: Allow DCE on ld_color_buffer masks
Helps with blend shader register pressure.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>
Alyssa Rosenzweig [Thu, 21 May 2020 21:51:06 +0000 (17:51 -0400)]
pan/mdg: Ensure we don't DCE into impossible masks
We round up for ld/st.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>
Alyssa Rosenzweig [Thu, 14 May 2020 17:30:25 +0000 (13:30 -0400)]
pan/mdg: Lower shifts to 32-bit
Kind of a hack..
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>
Alyssa Rosenzweig [Thu, 14 May 2020 17:29:22 +0000 (13:29 -0400)]
pan/mdg: Add pack_colour_32 opcode
Seen for RGB10_A2UI packing.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>
Alyssa Rosenzweig [Fri, 15 May 2020 16:19:22 +0000 (12:19 -0400)]
panfrost: Handle !independent_blend for blend shaders
Fixes MRT blending.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>
Alyssa Rosenzweig [Thu, 14 May 2020 16:27:12 +0000 (12:27 -0400)]
panfrost: Use _mesa_roundevenf when packing clear colours
Match blend shader approach.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>
Alyssa Rosenzweig [Tue, 12 May 2020 19:39:38 +0000 (15:39 -0400)]
panfrost: Fix dated comment
Work register counts are not explicitly stored for blend shaders, and
blend shaders are used for far more than UNORM8.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>
Hanno Böck [Thu, 21 May 2020 16:51:06 +0000 (18:51 +0200)]
Properly check mmap return value
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5150>
Eric Anholt [Fri, 15 May 2020 23:27:01 +0000 (16:27 -0700)]
ci: Improve baremetal's logging of the job env var passthrough.
Trying to read the sh -x script output was rough, just cat the file once
we're done setting it up.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5089>
Eric Anholt [Fri, 15 May 2020 23:15:07 +0000 (16:15 -0700)]
ci: Enable a fractional run with UBO-to-constbuf disabled on a3xx.
This gets us coverage of an important case in the HW that the CTS
otherwise basically doesn't hit.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5089>
Eric Anholt [Fri, 15 May 2020 18:20:44 +0000 (11:20 -0700)]
ci: Don't forget to set NIR_VALIDATE in baremetal runs.
Given that a530 doesn't have cpufreq, we really don't have the time to be
running the validator on all of deqp. This also helps explain why I had
to go to such a small fraction on the a3xx gles3 run (which we can now
increase). However, a3xx gles2 seems to be fast enough that we can leave
it enabled and get coverage for older chips.
Because we run more tests now, clear out some stale xfails from the a3xx
list.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5089>
Eric Anholt [Fri, 15 May 2020 23:01:15 +0000 (16:01 -0700)]
ci: Do an explicit NIR validation-enabled pass on freedreno a630.
We disable it for most of the CTS because it's slow, but let's do a
fractional run to make sure that we don't hit any obvious failures.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5089>
Eric Anholt [Sat, 16 May 2020 00:18:12 +0000 (17:18 -0700)]
ci: Fix DEQP_CASELIST_FILTER (used by a630 noubo run)
We were doing sed -i /filter/p, which printed everything but printed the
filtered things twice (though they'd only get tested once). Now that the
filter works, run all the UBO tests instead of doing a 1/5 run, revealing
a new failure.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5089>
Krzysztof Raszkowski [Fri, 22 May 2020 15:29:01 +0000 (17:29 +0200)]
gallium/swr: Fix building swr with MSVC
Fix building swr with MSVC by turning off
UNICODE before including windows.h.
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5166>
Danylo Piliaiev [Fri, 22 May 2020 10:36:31 +0000 (13:36 +0300)]
mesa: Fix double-lock of Shared->FrameBuffers and usage of wrong mutex
Fixes: 7534c536ca0f4b2b123200f421460094034f37a3
Fixes: 8cfb3e4ee57070ff45e7534a986a20c5fd649dc7
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3024
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5160>
Erik Faye-Lund [Wed, 20 May 2020 13:59:26 +0000 (09:59 -0400)]
zink: hammer in an explicit wait when retrieving buffer contents for reading
this ensures that the buffer returned is synchronized as expected, though
it incurs a significant performance hit and will hopefully be improved in future
patches
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5120>
Mike Blumenkrantz [Wed, 20 May 2020 13:53:45 +0000 (09:53 -0400)]
zink: reset query on-demand when beginning a new query from resume
the current query pool implementation expects queries to be reset at
the time they're initiated, which means queries started at this point
need to also be explicitly reset
the zink_begin_query() function can't be reused here or else the
query will be double-added to the active list, triggering an infinite loop
ref mesa/mesa#3000
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5120>
Mike Blumenkrantz [Wed, 20 May 2020 13:52:24 +0000 (09:52 -0400)]
zink: fix vkCmdResetQueryPool usage
the final parameter here is the number of queries to reset, not the
index of the last query, meaning that the value passed needs to be
(curr_query + 1) in order to reset the query corresponding to
curr_query
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5120>
Mike Blumenkrantz [Wed, 20 May 2020 13:45:39 +0000 (09:45 -0400)]
zink: flush active queries on destroy and free query object
queries with a valid active_list pointer are likely to still be active,
and vk spec requires them to have completed prior to being destroyed
this isn't completely accurate, as it's currently possible for queries
to remain in the active list while not actually being active, but it
resolves driver crashes that can occur from destroying a stilll-running
query pool object
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5120>
Mike Blumenkrantz [Wed, 20 May 2020 13:41:22 +0000 (09:41 -0400)]
zink: add SpvId returns to a couple ntv functions
this is helpful for debugging
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5120>
Mike Blumenkrantz [Wed, 20 May 2020 13:39:45 +0000 (09:39 -0400)]
zink: explicitly zero some arrays in ntv
just to be safe
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5120>
Pierre-Eric Pelloux-Prayer [Wed, 20 May 2020 13:34:12 +0000 (15:34 +0200)]
radeonsi/sdma: remove useless compare
clang warning:
result of comparison of constant 65536 with expression of type 'uint16_t'
(aka 'unsigned short') is always true
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5119>
Pierre-Eric Pelloux-Prayer [Wed, 20 May 2020 13:32:05 +0000 (15:32 +0200)]
amdgpu: fix unitialized variable
clang warning:
variable 'va_handle' is used uninitialized whenever 'if' condition is false
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5119>
Pierre-Eric Pelloux-Prayer [Wed, 20 May 2020 13:30:37 +0000 (15:30 +0200)]
radeonsi: fix inversed arguments in si_test_gds_memory_management
clang warning:
implicit conversion from enumeration type 'enum radeon_bo_usage'
to different enumeration type 'enum radeon_bo_domain'
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5119>
Pierre-Eric Pelloux-Prayer [Wed, 20 May 2020 13:26:29 +0000 (15:26 +0200)]
amd/addrlib: fix forgotten char -> enum conversions
clang warning:
result of comparison of constant 115 with expression of type
'const enum Dim' is always false
Fixes: e3e704c7e7e ("amd/addrlib: Use enum instead of sparse chars to identify dimensions")
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5119>
Ian Romanick [Wed, 20 May 2020 20:39:57 +0000 (13:39 -0700)]
glsl: Remove integer matrix support from ir_dereference_array::constant_expression_value
It looks like this code has existed since day 1, but I have no idea why.
There have never been integer matrices in GLSL.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5135>
Eric Anholt [Tue, 19 May 2020 23:26:37 +0000 (16:26 -0700)]
freedreno/a5xx: Define the 2D blit UBWC pitch fields
Syncing up with my changes to envytools for decoding texturator output.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5127>
Eric Anholt [Tue, 19 May 2020 23:21:20 +0000 (16:21 -0700)]
freedreno/a5xx: Set MIN_LAYERSZ on 3D textures like we do on a6xx.
These fields (TILE_ALL and MIN_LAYERSZ) seem to be the same on a5xx as
a6xx, having looked at some UBWC vs non-UBWC texturator cases. Setting
MIN_LAYERSZ does fix the 3D fail we see in the CTS.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5127>
Eric Anholt [Tue, 19 May 2020 22:52:11 +0000 (15:52 -0700)]
freedreno/a5xx: Add the outline of a unit test for a5xx layout.
Includes a few 3D cases from CTS layouts (since I was looking at CTS
failures) which do justify that a5xx's 3D layout workaround is actually
different from a6xx's.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5127>
Eric Anholt [Tue, 19 May 2020 22:45:05 +0000 (15:45 -0700)]
freedreno/fdl: Separate the list of a6xx testcases from the the test code.
I'll be reusing the test code for a5xx.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5127>
Eric Anholt [Tue, 19 May 2020 22:23:54 +0000 (15:23 -0700)]
freedreno/a5xx: Move resource layout to fdl.
I'm working on fixing the 3D layouts in CI so we can stabilize it, but I
wanted unit tests using the texturator scripts to make sure I don't break
things. This also makes a5xx and a6xx layout easily comparable again.
This is a straightforward move of the code with prsc references replaced
by arguments in the style of fdl6.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5127>
Alyssa Rosenzweig [Thu, 21 May 2020 22:16:15 +0000 (18:16 -0400)]
pan/mdg: Eliminate remaining divisions from compiler
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5154>
Alyssa Rosenzweig [Thu, 21 May 2020 22:09:53 +0000 (18:09 -0400)]
pan/mdg: Avoid division in printing helpers
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5154>
Alyssa Rosenzweig [Thu, 21 May 2020 22:05:29 +0000 (18:05 -0400)]
pan/mdg: Eliminate 64-bit swizzle packing division
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5154>
Alyssa Rosenzweig [Thu, 21 May 2020 22:04:36 +0000 (18:04 -0400)]
pan/mdg: Eliminate expand_writemask division
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5154>
Alyssa Rosenzweig [Thu, 21 May 2020 22:02:38 +0000 (18:02 -0400)]
pan/mdg: Cleanup comments that look like division
Don't use a /.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5154>
Alyssa Rosenzweig [Thu, 21 May 2020 19:27:21 +0000 (15:27 -0400)]
panfrost: Fix transform feedback types
Don't assume float for everything.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5152>
Alyssa Rosenzweig [Wed, 20 May 2020 16:40:02 +0000 (12:40 -0400)]
panfrost: Don't set CAN_DISCARD for MFBD
It's likely harmless but let's match the blob.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
Alyssa Rosenzweig [Thu, 21 May 2020 19:49:30 +0000 (15:49 -0400)]
panfrost: Avoid redundant shader executions with mask=0x0
Only works for a few Midgard GPUs, but hey.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
Alyssa Rosenzweig [Wed, 20 May 2020 16:56:01 +0000 (12:56 -0400)]
panfrost: Disable tib read/write when colourmask = 0x0
There might still be Z/S updates so we can't drop the whole shader but
we can shortcircuit the colour pipeline.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
Alyssa Rosenzweig [Wed, 20 May 2020 18:19:41 +0000 (14:19 -0400)]
panfrost: Remove dated comment about leaks
It's been fixed for a while.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
Alyssa Rosenzweig [Thu, 21 May 2020 19:48:03 +0000 (15:48 -0400)]
panfrost: Limit blend shader work count
To 8, but later we should go much lower.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
Alyssa Rosenzweig [Tue, 19 May 2020 23:07:36 +0000 (19:07 -0400)]
panfrost: Allow tiling on RECT textures
Except for the norm coords bit, they're identical to 2D.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
Alyssa Rosenzweig [Tue, 19 May 2020 21:52:29 +0000 (17:52 -0400)]
panfrost: Allow bpp24 tiling
It's dumb that we have to but it does help RGB8 nontrivially. Alas.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
Alyssa Rosenzweig [Tue, 19 May 2020 21:39:09 +0000 (17:39 -0400)]
panfrost: Don't zero staging buffer for tiling
It's a little less safe but the memset does take time during
initialization. v3d doesn't either, so I think it's ok.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
Alyssa Rosenzweig [Tue, 19 May 2020 21:29:23 +0000 (17:29 -0400)]
panfrost: Don't set PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
I'm not aware of any reason this might be necessary, let's avoid the
translate.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
Alyssa Rosenzweig [Tue, 19 May 2020 21:25:14 +0000 (17:25 -0400)]
panfrost: Fill in SCALED formats to format table
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
Alyssa Rosenzweig [Tue, 19 May 2020 21:12:13 +0000 (17:12 -0400)]
panfrost: Remove deadcode
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
Alyssa Rosenzweig [Tue, 19 May 2020 19:06:52 +0000 (15:06 -0400)]
panfrost: Keep cached BOs mmap'd
It doesn't make sense to munmap/mmap repeatedly; they're mapped GPU-side
anyway. So just munmap on free, which will happen in low-mem regardless.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
Alyssa Rosenzweig [Wed, 6 May 2020 23:48:05 +0000 (19:48 -0400)]
panfrost: Guard experimental fp16 behind debug flag
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Wed, 13 May 2020 22:24:25 +0000 (18:24 -0400)]
pan/mdg: Pack 8-bit swizzles in 16-bit ops
Let's inch closer to 8-bit.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 14 May 2020 17:29:54 +0000 (13:29 -0400)]
pan/mdg: Implement condense_writemask for 8-bit
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 14 May 2020 17:30:05 +0000 (13:30 -0400)]
pan/mdg: Implement vector constant printing for 8-bit
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Wed, 20 May 2020 20:14:17 +0000 (16:14 -0400)]
pan/mdg: Use shifts instead of division for RA sizes
We're only dealing with powers-of-two, so this eliminates potential
issues with divisions-by-zero that are otherwise hacked around. Probably
faster too.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Wed, 13 May 2020 15:05:49 +0000 (11:05 -0400)]
pan/mdg: Pack barriers correctly
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Wed, 13 May 2020 15:05:34 +0000 (11:05 -0400)]
pan/mdg: Fix type checking issues with compute
SSBO and barriers.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Mon, 11 May 2020 20:05:48 +0000 (16:05 -0400)]
pan/mdg: Separately pack constants to the upper half
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Mon, 11 May 2020 19:58:58 +0000 (15:58 -0400)]
pan/mdg: Only combine 16-bit constants to lower half
We can't swizzle both halves simultaneously.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Mon, 11 May 2020 19:52:18 +0000 (15:52 -0400)]
pan/mdg: Factor out mir_adjust_constant
Each source is semi-independent, we don't need the extra indentation
when the logic is already so complex.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Mon, 11 May 2020 19:33:43 +0000 (15:33 -0400)]
pan/mdg: Print constant vectors less wrong
For !32-bit types, we need to pay attention to rep_low/high/half to
determine the effective swizzle.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Mon, 11 May 2020 17:49:03 +0000 (13:49 -0400)]
pan/mdg: Round up bytemasks when spilling
So we can pack the spills for <32-bit types.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Mon, 11 May 2020 16:56:43 +0000 (12:56 -0400)]
pan/mdg: Print mask when dest=0
Forgot this convention differs from Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Mon, 11 May 2020 19:07:25 +0000 (15:07 -0400)]
pan/mdg: Set RA bounds for fp16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Mon, 11 May 2020 19:06:53 +0000 (15:06 -0400)]
pan/mdg: Eliminate load_64
It can always be inferred from the types.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Mon, 11 May 2020 19:05:27 +0000 (15:05 -0400)]
pan/mdg: Use type size to determine alignment
Generally, f16 needs to be aligned to 16-bit, f32 to 32-bit, ...
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Mon, 11 May 2020 19:03:58 +0000 (15:03 -0400)]
pan/lcra: Allow per-variable bounds to be set
Different variables need to respect different bounds. In general,
16-bytes is okay, but for 4-channel 16-bit vectors, we can't cross 8
byte boundaries (else the swizzles will not be packable after), so we
update LCRA to allow this more general form.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Wed, 6 May 2020 22:17:02 +0000 (18:17 -0400)]
pan/lcra: Remove unused alignment parameters
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Mon, 11 May 2020 19:02:10 +0000 (15:02 -0400)]
pan/mdg: Ignore dest.type when offseting load swizzle
It's always as-if 32-bit.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 7 May 2020 19:43:21 +0000 (15:43 -0400)]
pan/mdg: Don't generate conversions for fp16 LUTs
We can just set the register mode appropriately and then we don't have
to care anywhere else, and there's no extra NIR to chew through. Make
sure we include sqrt too.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Fri, 8 May 2020 21:42:40 +0000 (17:42 -0400)]
pan/mdg: Implement b2f16
...as iand
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Fri, 8 May 2020 21:41:49 +0000 (17:41 -0400)]
pan/mdg: Streamline dest_override handling
We can pass it all off to emit time, and let the types in the IR do the
heavylifting in the meantime, which is a lot easier to get right.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 7 May 2020 23:11:38 +0000 (19:11 -0400)]
pan/mdg: Remove redundant redundancy
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 21 May 2020 16:38:27 +0000 (12:38 -0400)]
pan/mdg: Defer modifier packing until emit time
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 21 May 2020 16:32:20 +0000 (12:32 -0400)]
pan/mdg: Remove promote_float pass
Now unused.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 21 May 2020 16:31:40 +0000 (12:31 -0400)]
pan/mdg: Promote imov to fmov on a NIR level
Avoids dedicated MIR promote_fmov pass which is unnecessary.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 21 May 2020 16:24:42 +0000 (12:24 -0400)]
pan/mdg: Identify scalar integer mods
Symmetric with vector mods, except for normal which is packed as
sign-extend. (flag 2 never seen in the wild)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 21 May 2020 16:19:56 +0000 (12:19 -0400)]
pan/mdg: Use type to determine triviality of a move
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 21 May 2020 16:16:48 +0000 (12:16 -0400)]
pan/mdg: Use src_types to determine size in scheduling
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 21 May 2020 16:15:09 +0000 (12:15 -0400)]
pan/mdg: Add abs/neg/shift modifiers to IR
Rather than twiddling them into the ALU packed field.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 21 May 2020 16:13:38 +0000 (12:13 -0400)]
pan/mdg: Explain ld/st sign/zero extension
Now we know why there are duplicates :-)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 7 May 2020 20:10:09 +0000 (16:10 -0400)]
pan/mdg: Respect !32-bit sizes in RA
So we can take advantage of mediump.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Alyssa Rosenzweig [Thu, 7 May 2020 20:09:47 +0000 (16:09 -0400)]
pan/mdg: Handle dest up/lower correctly with swizzles
During emit time.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
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