intel/perf: create a vtable entry for batch_references

Iris and i965 variants of this method need to be called by perf
routines.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: refactor gen_perf_end_query into gen_perf

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: refactor gen_perf_begin_query into gen_perf

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: move perf-related state into gen_perf_context

To move more operations into intel/perf, several state items are
needed.  Save references to that state in the perf_ctxt, rather than
passing them in for every operation.

This commit includes an initializer for gen_perf_context, to set those
references and also encapsulate the initialization of the sample
buffer state.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: create a vtable entries for buffer object map/unmap

These operations are needed to refactor subsequent methods into perf

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: move client reference counts into perf

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: move open_perf into perf

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: move close_perf into perf

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: create a vtable entry for emit_mi_flush

This method is needed to move subsequent methods into perf.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: use temporary pointers to simplify access to perf state

Most accesses to perf state were made through repeated dereferences of
brw_context members.  Prefering temporary variables of perf_ctx and
perf_cfg has the following advantages:

 - more concise implementation
 - easier refactor when moving subsequent methods to perf

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: move snapshot_statistics_registers into perf

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: move query_object into perf

Query objects can now be encapsulated within the perf subsystem.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: create a vtable entry for store_register_mem64

This method is needed to move subsequent methods into perf.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: move free_sample_bufs into perf

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: move reap_old_sample_buffers into perf

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: move get_free_sample_buf into perf

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: move the perf context into perf

The "context" that is necessary to submit and process perf commands to
the hardware was previously present in the brw_context.perfquery
struct.  This commit moves it into perf and provides a more
understandable name.

The intention is for this struct to be private, when all methods that
access it are migrated into perf.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: move get_metric_id to perf

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: move oa_sample_buf structure to perf

oa_sample_buf holds the data provided by the kernel that will be
collated into performance metrics.  Since this functionality will be
implemented in perf, the struct needs to be defined there.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: enumerate query-based metrics in perf

Iris and i965 both need to enumerate the available metrics, so these
routines must be located in perf.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: move perf-related constants to common location

The perf subsystem needs several macro definitions that were
duplicated in Iris and i965 headers.  Place these macros within perf,
if the perf implementation contains the only references to the values.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: create a vtable entry for capture_frequency_stat_register

In preparation for calling both Iris and i965 implementions from perf.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: create a vtable entry for batchbuffer_flush

In preparation for calling both Iris and i965 implementions from perf.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: create a vtable entry for emit_report_count

In preparation for calling both Iris and i965 implementions from perf.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: create a vtable entry for bo_unreference

In preparation for calling both Iris and i965 implementions from perf.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: create a vtable for low-level driver functions

Performance metrics collections requires several actions (eg bo_map())
that have different implementations for Iris and i965.  The perf
subsystem needs a vtable for each of these actions, so it can invoke
the corresponding implementation for each driver.

The first call to be added to the table is bo_alloc.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: use common ioctl wrapper

There were multiple ioctl-wrapper functions, so a common
implementation was put in gen_gem.h.   With a common implementation,
perf no longer needs the caller to configure one for it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/perf: rename gen_perf to gen_perf_config

This structure contains the configurations of the metrics for the
current platform, and the settings needed for the perf subsystem to
query that configuration from the device.  This data is available
without a rendering context, and needed to support MDAPI metrics for
Vulkan.

A gen_perf_context struct will be added later, which holds additional
state from the rendering context necessary for metric data
collection.  The gen_perf struct needs a more precise name to reduce
confusion.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nvc0: fix program dumping, use _debug_printf

This debug situation is unforunate. debug_printf only does something
with DEBUG set, but in practice all that needs to be moved to !NDEBUG.
For now, use _debug_printf which always prints. However the whole
function is guarded by !NDEBUG.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: add support for ATOMC_WRAP TGSI operations

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

gallium: redefine ATOMINC_WRAP to be more hardware-friendly

Both AMD and NVIDIA hardware define it this way. Instead of replicating
the logic everywhere, just fix it up in one place.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: relax EXT_shader_image_load_store enable

There's no reason to bring format-less load requirement into this
extension. It requires a size to be provided, and a compatible format is
computed from the size + data type. For example

  layout(size1x32) uniform iimage1D image;

becomes

  DCL IMAGE[0], 1D, PIPE_FORMAT_R32_SINT, WR

whereas PIPE_CAP_IMAGE_LOAD_FORMATTED is designed to allow
PIPE_FORMAT_NONE to be provided as a format and still enable LOAD
operations to be performed.

So the shader has all the information it needs about the format.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965/perf: restore mdapi statistics query metrics

Registration of mdapi metrics based on statistics query registers was
inadvertently removed in the commit that checks for OA kernel support.

The statistics queries are not dependent on OA.

Fixes: 96e1c945f2b ("i965: Move device info initialization to common code")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

util: add anon_file.h for all memfd/temp file usage

Move the Weston os_create_anonymous_file code from egl/wayland into util,
add support for Linux memfd and FreeBSD SHM_ANON,
use that code in anv/aubinator instead of explicit memfd calls for portability.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

radeonsi: limit DPBB context_states_per_bin batches when using gfx9 workaround

It seems that using 'context_states_per_bin = 1' for DPBB fixes the reported issue.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110214

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: reduce DPBB persistent_states_per_bin value for APUs

Fixes some reported GPU hangs on RAVEN.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111231

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: fix typo in DPBB register field

Also only set FLUSH_ON_BINNING_TRANSITION for GPU families that needs it (matches
what si_emit_dpbb_disable is doing).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: fix S_028C48_MAX_ALLOC_COUNT value

This field uses "value minus 1" encoding.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

etnaviv: drop struct etna_3d_state

Also drop #if 0 code block.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <philipp.zabel@gmail.com>

mesa: Use _mesa_delete_transform_feedback_object in drivers

Function _mesa_delete_transform_feedback_object called from within
drivers once driver-specific clean-up has been done. Brings into
conformity with how other GL objects are handled.

CC: Eric Anholt <eric@anholt.net>
CC: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

mesa: use _mesa_delete_query in drivers

Now drivers can call _mesa_delete_query once driver-specific
clean-up has been done. Brings into conformity with how other GL
objects are handled.

CC: Eric Anholt <eric@anholt.net>
CC: Kenneth Graunke <kenneth@whitecape.org>
Suggested-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

docs: update calendar, add news item and link release notes for 19.1.4

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

docs: add sha256 checksums for 19.1.4

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 7fcb69a33c6c6d1658de3e0fd9c40363584c8c7b)

docs: add release notes for 19.1.4

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit b84ffa028d09c1bba1add468fd68886ee243d428)

meson,i965: Link with android deps when building for android.

The DBG marco in brw_blorp.c ends up calling an android log function:

error: undefined reference to '__android_log_print'

v2: On suggestion from Lionel, hang the Android dependency onto a new
    libintel_common dependency.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

gallium/dump: add missing query-type to short-list

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 3f6b3d9db72 ("gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/dump: add missing query-type to short-list

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: a677799e51a ("gallium: add PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE
                     and corresponding cap")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gitlab-ci: don't install autotools deps

These could've been deleted a long time ago, but apparent we forgot.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

util: fix mem leak of program path

Fixes: 759b94038987bb983398 ("util: Get program name based on path when possible")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

meson: build intel-ui tools as part of `all` tools

Reported-by: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111289
Cc: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

gitlab-ci: add gtk3 dev files for `-D tools=intel-ui`

We also need to update wayland-protocols and libXrandr (and randrproto),
as they are too old for gdk3 (which gtk3 depends on).

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

clover: Fix build after clang r367864

v2: Drop special case of llvm-9
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Acked-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Aaron Watry <awatry@gmail.com>

mesa: remove super old TODOs from shaderapi.c

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: freedreno: Android.registers.mk: Fix up register xml.h file generation

The current Androdi.registers.mk file causes build failures that
look like:
 FAILED:
 external/mesa3d/src/freedreno/Android.registers.mk:49: error: implicit rules are obsolete: out/target/product/linaro_db845c/gen/STATIC_LIBRARIES/libfreedreno_registers_intermediates/registers/%.xml.h

Caused by the following Android build rule change:
https://android.googlesource.com/platform/build/+/HEAD/Changes.md#implicit_rules

I tried to replace this with something similar to the static
pattern suggested in the URL above, but ended up getting all the
xml.h files generated using only the first a2xx.xml source file.

So I've fallen back to explicitly defining the make rules for
each.

Additionally, we needed to provide the proper
LOCAL_EXPORT_C_INCLUDE_DIRS and add the defined static library
to the components that depend on the register headers.

Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: John Stultz <john.stultz@linaro.org>

mesa: Add ir3/ir3_nir_imul.c generation to Android.mk

With current master we're seeing build failures with AOSP:
  error: undefined symbol: ir3_nir_lower_imul

This is due to the ir3_nir_imul.c file not being generated
in the Android.mk files.

This patch simply adds it to the Android build, after which
thigns build and book ok on db410c.

Cc: Rob Clark <robdclark@chromium.org>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Amit Pundir <amit.pundir@linaro.org>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Greg Hartman <ghartman@google.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: John Stultz <john.stultz@linaro.org>

panfrost: Take into account a index_bias for glDrawElementsBaseVertex calls

Midgard does not accept a index_bias directly and relies instead on a
bias correction offset (offset_bias_correction) in order to calculate
the unbiased vertex index.

We need to make sure we adjust offset_start and vertex_count in order to
take into account the index_bias as required by a
glDrawElementsBaseVertex call and then supply a additional
offset_bias_correction to the hardware.

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

radv/gfx10: Enable DCC for storage images.

v2: Hide it behind a perftest flag.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Add device argument for dcc compression check.

Because it is about to be generation dependent.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Disable compression for compute DCC decompress store.

Previously we relied on stores not using DCC but that is going to
change, so disable compression explicitly.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Add extra struct to image view creation.

For extra args. Unlike image creation, I'm not embedding the vk
struct in there, so all the inline structs can be kept.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Do not decompress on LAYOUT_GENERAL.

We handle render loops properly now and STORAGE still disables
DCC/TC-compat HTILE in general.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Pass through render loop detection to internal layout decisions.

And do nothing with it yet.

Everything outside a renderpass has no render loop.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Add render loop detection in renderpass.

VK spec 7.3:

"Applications must ensure that all accesses to memory that backs
image subresources used as attachments in a given renderpass instance
either happen-before the load operations for those attachments, or
happen-after the store operations for those attachments."

So the only renderloops we can have is with input attachments. Detect
these.

Reviewed-by: Dave Airlie <airlied@redhat.com>

drirc: Add vendor workaround for Divinity: Original Sin EE

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93551

mesa/gallium: add dric option to allow overriding GL vendor string

Will be used in the following patch.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93551

relnotes/19.2: document EXT_texture_dhadow_lod

radv: Fix config reg assert.

Using the wrong bounds

Fixes: "219d6939df8 radv: add more assertions to make sure packets are correctly emitted"
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

tgsi_to_nir: add a few needed double opcodes

for internal radeonsi shaders

v2 (Connor):
- Split out prep work from adding opcodes, and rewrite the former

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

tgsi_to_nir: implement a few needed 64-bit integer opcodes

for internal radeonsi shaders

v2 (Connor):
- Split this out from the prep work, and rework the former
- Add support for U64SNE

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ttn: Prepare for 64-bit sources and destinations

v2: Properly handle 32->64 bit conversions

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ttn: Use 1-bit NIR comparison opcodes

We shouldn't be using the versions that output a 32-bit boolean, since
nir_opt_algebraic won't optimize them as well. Drivers will lower these
to the 32-bit versions after optimizing, if appropriate. Also, this will
make implementing 64-bit comparisons easier.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nir/builder: Add nir_b2i

Same as nir_b2f but for integers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: enable EXT_shader_image_load_store

This depends on LLVM 10 because this needs https://reviews.llvm.org/D65283

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: add support for nir atomic_inc_wrap/atomic_dec_wrap

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: add support for tgsi ATOMDEC_WRAP / ATOMINC_WRAP opcodes

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac: add ac_atomic_inc_wrap / ac_atomic_dec_wrap support

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nir: add atomic_inc_wrap/atomic_dec_wrap image intrinsics

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: add EXT_shader_image_load_store new image functions

This extension has 2 functions that are missing from the ARB versions:
- imageAtomicIncWrap
- imageAtomicDecWrap

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: add EXT_shader_image_load_store keywords to lexer

All of them already existed for ARB_shader_image_load_store.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: add size qualifiers from EXT_shader_image_load_store

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: handle differences between ARB/EXT versions of shader_image_load_store

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: add EXT_shader_image_load_store glBindImageTextureEXT function

The implementation is almost identical to glBindImageTexture except for error
checking.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glapi: add EXT_shader_image_load_store

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: add PIPE_CAP_TGSI_ATOMINC_WRAP to indicate support

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

tgsi: add ATOMICINC_WRAP/ATOMICDEC_WRAP opcode

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi/gfx10: enable all CUs for GS if NGG is never used

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi/gfx10: add global use_ngg and use_ngg_streamout flags

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi/gfx10: remove an obsolete VGT_REUSE_OFF workaround

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi/gfx10: disable LATE_ALLOC_GS on Navi14

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi/gfx10: implement a bug workaround for GE_PC_ALLOC

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi/gfx10: implement a bug workaround for NGG -> legacy transitions

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi/gfx10: implement a GE bug workaround

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi/gfx10: set GE_CNTL for tessellation correctly

to match PAL

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi/gfx10: simplify NGG code in si_update_shaders

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi/gfx10: fix input VGPRs for legacy VS

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: make sure that rasterizer state != NULL and remove all NULL checking

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: make sure that DSA state != NULL and remove all NULL checking

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: make sure that blend state != NULL and remove all NULL checking

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: DCC MSAA blending bug - include logic op, limit to Navi14 and older

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: determine accurately whether logic op is enabled

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>