intel/blorp: Satisfy HIZ_CCS fast-clear alignments

Prevent the piglit test,
amd_vertex_shader_layer-layered-depth-texture-render, from regressing in
in a future commit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Refactor blorp_can_hiz_clear_depth()

Prepare this function to be used in iris and to handle new Gen12 behavior.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

isl: Add isl_surf_supports_hiz_ccs_wt()

Add a helper to determine if an ISL surface supports the write-through
mode of HIZ_CCS.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Enable HIZ_CCS in depth buffer instructions

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Define initial HIZ_CCS state and transitions

Make it match those of HIZ.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Create an unusable secondary aux surface

The HIZ_CCS and MCS_CCS auxiliary surface modes require that drivers
store information about two aux buffers. We choose to represent this as
HiZ/MCS being the primary aux surface and the CCS as an secondary/extra
aux surface. This representation has the effect of placing most of the
code that will have to choose between the two aux surfaces around the
aux-map entry points.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Don't guess the aux_usage

Instead of guessing an aux_usage, then confirming it if the
isl_surf_get_*_surf functions are successful, just call the ISL
functions up-front. This will help us to more easily determine if a
depth buffer supports HIZ_CCS.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/blorp: Treat HIZ_CCS like HiZ

Allow it in depth buffer instructions but disable it for blits.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/blorp: Assert against HiZ in surface states

Avoid unexpected behavior if the caller happens to pass in a HiZ aux
usage.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Support HIZ_CCS in isl_surf_get_ccs_surf

Add an extra aux parameter which will be filled out with CCS if the
first two isl_surf parameters fit the requirements for HiZ_CCS.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

isl: Reduce assertions during aux surf creation

Return false more often to reduce the burden on the caller.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Enable CCS_E for R24_UNORM_X8_TYPELESS on TGL+

While this format isn't listed in BSpec: 53911, other documentation and
empirical evidence suggest that it's fine to remap it to R32_FLOAT. I've
filed a bug for the BSpec page.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Use 3DSTATE_DEPTH_BUFFER::ControlSurfaceEnable

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/isl: Support HIZ_CCS in emit_depth_stencil_hiz

v2. Remove undocumented CCS_E-only mode for depth. (Nanley)

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Use RENDER_SURFACE_STATE::DepthStencilResource

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Update alignment restrictions for HiZ surfaces.

v2 (Nanley):
* Maintain a chronological ordering for HiZ alignments. Suggested by
  Ken.

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Clear ::has_hiz when disabling aux

Fixes: 2cddc953cd0 ("iris: some initial HiZ bits")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/blorp: Disable depth testing for slow depth clears

We'll start doing slow depth clears more often on HIZ_CCS buffers in a
future commit. Reduce the performance impact by making them use less
bandwidth.

From the Depth Test section of the BSpec:

   This function is enabled by the Depth Test Enable state variable. If
   enabled, the pixel's ("source") depth value is first computed. After
   computation the pixel's depth value is clamped to the range defined
   by Minimum Depth and Maximum Depth in the selected CC_VIEWPORT state.
   Then the current ("destination") depth buffer value for this pixel is
   read.

and from the Depth Buffer Updates section of the BSpec:

   If depth testing is disabled or the depth test passed, the incoming
   pixel's depth value is written to the Depth Buffer.

Taken together, it's clear that depth testing isn't necessary to perform
a depth buffer clear. Mark Janes and I analyzed this patch with
frameretrace and a depthrange piglit test. I disabled HiZ to ensure we'd
get slow depth clears. We've observed the bandwidth consumption by the
depth buffer access to be cut ~50% on BDW and SKL during depth clears.
On a more graphically intensive workload, the Shadowmapping Sascha
benchmark, I took the average of 3 runs on a BDW with a display
resolution of about 1920x1200 (minus some desktop environment
decorations). I measured a 22.61% FPS improvement when HiZ is disabled.

v2. The BSpec doesn't mandate this behavior, update comment accordingly.
    (Ken)

Fixes: bc4bb5a7e30 ("intel/blorp: Emit more complete DEPTH_STENCIL state")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Enable CCS_E for some formats on Gen12

In ISL:
   Update the format table to add CCS_E support for some 8BPP formats,
   some 16BPP formats, and R10G10B10A2_UNORM_SRGB.

   In the helper for determining CCS_E support, we return false for some
   16BPP formats because they aren't properly handled in blorp_copy().

In BLORP:
   Allow the new and non-problematic formats for CCS_E-enabled copies.

v2. Update other fields for A1B5G5R5_UNORM and A4B4G4R4_UNORM in table.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)

isl: Redefine the CCS layout for Gen12

The CCS could be described in a number of ways, but this format was
chosen to minimize churn in the drivers. We may decide on an different
direction in the future.

v2. Increase alignment for display surfaces. (Nanley)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

isl: Add and use isl_tiling_flag_to_enum()

Use a helper that will automatically handle Gen12's CCS tiling when
creating a CCS isl_surf.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

iris: Allow for non-Y-tiled aux allocation

The Gen12 CCS is not Y-tiled.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

isl/drm: Map HiZ and CCS tilings to Y

In the function which translates ISL tilings to i915 tilings, map ISL's
HiZ and CCS tilings to Y instead of NONE (linear). The HW docs describe
HiZ and pre-Gen12 CCS surfaces as being Y-tiled in memory.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/isl: Update surf_fill_state for gen12

v2 (Nanley):
* Avoid driver churn for now.
* Include some media compression changes.

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/isl/fill_state: Separate aux_mode handling from aux_surf

v2. Avoid driver churn for now. (Nanley)

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/isl: Add new aux modes available on gen12

v2. Add media compression. (Nanley)

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965/miptree: Avoid -Wswitch for the Gen12 aux modes

Avoid the compiler warnings for the new enums that will be introduced in
a future commit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

anv/private: Modify aux slice helpers for Gen12 CCS

The isl_surf structs for Gen12's CCS won't describe how many slices in
the main surface can be compressed. All slices will be compressable if
CCS is enabled, so lookup the main surface's logical dimension.

v2. Add a space before a `?`. (Jordan)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/blorp: Don't assert aux slices match main slices

This isn't accurate enough for HiZ which can have a discontiguous range
of supported aux slices. This also won't work with the plan to represent
Gen12 CCS as a single slice surface.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/blorp: Use surf instead of aux_surf for image dimensions

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/blorp: Halve the Gen12 fast-clear/resolve rectangle

Update their dimensions according to the Bspec.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/blorp/gen12: Set FWCC when storing the clear color.

From "Render Target Fast Clear" description for Gen12:

   "SW must store clear color using MI_STORE_DATA_IMM with
   ForceWriteCompletionCheck bit set."

From Instruction_MI_STORE_DATA_IMM, bitfield 10 (when set to 1):

   "Following the last write from this command, Command Streamer
   will wait for all previous writes are completed and in global
   observable domain before moving to next command."

We use 4 SDIs to store the clear color (one per channel). From the
description, it looks to me that setting that flag only on the last SDI
should be enough.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

isl: Round up some pitches to 512B for Gen12's CCS

Gen12's CCS requires that the main surface have a pitch aligned to 512B.

v2. Provide a BSpec citation. (Ken)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Don't assume CCS_E includes CCS_D

There's no longer a clear-only compression mode of CCS on Gen12+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

anv/cmd_buffer: Don't assume CCS_E includes CCS_D

There's no longer a clear-only compression mode of CCS on Gen12+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv/image: Disable CCS_D on Gen12+

Clear-only compression no longer exists on TGL.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

isl: Disable CCS_D on Gen12+

Clear-only compression no longer exists on TGL.

v2. Add BSpec reference. (Sagar)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

iris: Drop support for I915_FORMAT_MOD_Y_TILED_CCS on TGL+

The format of the CCS has changed.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

anv/formats: Disable I915_FORMAT_MOD_Y_TILED_CCS on TGL+

The format of the CCS has changed.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

anv: Properly allocate aux-tracking space for CCS_E

add_aux_state_tracking_buffer() actually checks the aux usage when
determining how many dwords to allocate for state tracking. Move the
function call to the point after the CCS_E aux usage is assigned.

Fixes: de3be618016 ("anv/cmd_buffer: Rework aux tracking")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv/blorp: Use BLORP_BATCH_NO_UPDATE_CLEAR_COLOR

Avoid failing the `info->use_clear_address` assertion in ISL on Gen12+.

Fixes: 6c9f9a82d78 ("intel/genxml,isl: Add gen12 render surface state changes")
Reported-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv: Add support for depth bounds testing.

In gen12 we use the 3DSTATE_DEPTH_BOUNDS instruction
to enable depth bounds testing.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

iris: Add support for depth bounds testing.

In gen12 we use the 3DSTATE_DEPTH_BOUNDS instruction
to enable depth bounds testing.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Add 3DSTATE_DEPTH_BOUNDS instruction.

In gen12 we add the 3DSTATE_DEPTH_BOUNDS instruction
which enables support for depth bounds testing.

Signed-off-by: Plamena Manolova <plamena.manolova@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Initialize all fields of ir_variable in constructor

Better be safe, even if we could technically avoid this for
some fields.

Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1999
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Tested-by: Witold Baryluk <witold.baryluk@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

util: remove LIST_IS_EMPTY macro

Just use the inlined function directly. The new function was introduced
in addcf410.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: rename list_empty() to list_is_empty()

This makes it clear that it's a boolean test and not an action
(eg. "empty the list").

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: remove LIST_DEL macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: remove LIST_DELINIT macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: remove LIST_REPLACE macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: remove LIST_ADD macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: remove LIST_ADDTAIL macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: remove LIST_INITHEAD macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

gitlab-ci: fixup debian tags

When resolving a merge-conflict, I accidentally only updated the
ARM64-tag tag. Let's correct this.

Fixes: 3d529c17393 ("gitlab-ci: also build Zink on CI")

intel/compiler: Fix C++ one definition rule violations

When building with "-flto" brw::block_data definitions
were colliding.

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

gitlab-ci: also build Zink on CI

This prevents accidentally breaking the driver-build while working on
other drivers.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>

zink: simplify gl-to-vulkan lowering

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: more complete sampler-dim handling

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: fixup scissoring

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: limited uniform buffer size so the limits is not exceeded.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: do not set lineWidth to invalid value

Some implementations don't support the lineWidth-feature, so let's
avoid setting invalid state to them. But since we don't have a fallback
for this, inform the user.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: pass screen to zink_create_gfx_pipeline

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: respect ubo buffer alignment requirement

The driver can report a minimum alignment for UBOs, and that can be
larger than 64, which we've currently been using. Let's play ball, and
use the reported value instead.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: fix line-width calculation

There's two things that goes wrong in this code on some drivers:
1. Rounding off the line-width to granularity can push it outside the
   legal range.
2. A granularity of 0.0 results in NaN, because we divide by zero.

So let's make this code a bit more robust.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: fixup return-value

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: refactor blitting

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: implement resource_from_handle

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: use VK_FORMAT_B8G8R8A8_UNORM for PIPE_FORMAT_B8G8R8X8_UNORM

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: do not set VK_IMAGE_CREATE_2D_ARRAY_COMPATIBLE_BIT for non-3D textures

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: alias var0 on tex0 etc instead

This fixes Quake3, and is more in line with directx semantics.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: lower two-sided coloring

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: alias generic varyings on non-generic ones

This gets rid of the nasty location-allocation hack.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: implement load_front_face

We're now adding interface-types during code-emitting, so we need to
defer emitting the entry-point. No biggie, spirv_builder is prepares for
this.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: fixup b2i32

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: do not lower bools to float

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: prepare for 1-bit booleans

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: fixup b2i32 and implement b2f32

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: clean up get_[fu]vec_constant

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: inline get_uvec_constant into emit_load_const

This is the only call-site that wants to specify unique values per
component for any of the get_*_constant functions. So let's give this
its own implementation instead, so we can ease the burden for the rest.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: add emit_uint_const-helper

While we're at it, let's move emit_float_const to the same location as
this needs to be defined at.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: add emit_bitcast-helper

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: use bit_size instead of hard-coding

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: implement emit_float_const helper

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: implement emit_select helper

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: implement b2i32

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: implement bitwise ops

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: implement bcsel

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: assert bit-size

This is going to make it easier to verify that 1-bit float sizes don't
leak into the rest of the code.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: implement f2b1

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: use ordered compares

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: lower point-size

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: add missing sRGB DXT-formats

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: disable PIPE_CAP_QUERY_TIME_ELAPSED for now

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: support shadow-samplers

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: fix rendering to 3D-textures

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: initialize nr_samples for pipe_surface

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: use primconvert to get rid of 8-bit indices

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: also accept txl

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

HACK: zink: suspend / resume queries on batch-boundaries

HACK because we assert that we don't overrun the pool. We need a
fallback here instead.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink: move set_active_query_state-stub to zink_query.c

Acked-by: Jordan Justen <jordan.l.justen@intel.com>