isl: Take the slice0_extent shortcut for interleaved MSAA

The shortcut works just fine for MSAA and the comment even says so.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

isl: Remove duplicate px->sa conversions

In all three cases, we start with width and height taken from
isl_surf::phys_slice0_extent_sa which is already in samples.  There is no
need to do the conversion and doing so gives us an incorrect value.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

i965/blorp: Use the isl_view from the blorp_surface_info

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Get rid of brw_blorp_surface_info::width/height

Instead, we manually mutate the surface size as needed.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Move surface offset calculations into a helper

The helper does a full transformation on the surface to turn it into a new
2-D single-layer single-level surface representing the original layer and
level in memory.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Use ISL to compute image offsets

For the moment, we still call the old miptree function; we just assert that
the two are equal.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

isl: Add functions for computing surface offsets in samples

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

isl: Fix get_image_offset_sa_gen4_2d for multisample surfaces

The function takes a logical array layer but was assuming it was a physical
array layer.  While we'er here, we also make it not assert-fail on gen9 3-D
surfaces.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Add an isl_view to blorp_surface_info

Eventually, this will be the actual view that gets passed into isl to
create the surface state.  For now, we just use it for the format and the
swizzle.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Move intratile offset calculations out of surface state setup

Previously we multiplied full x/y offsets, resolved tile aligned buffer
offset and intra tile offset based on that.  Now we let ISL to take into
account the msaa setting and we only multiply the resolved intra tile
offsets.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Refactor interleaved multisample destination handling

We put all of the code for fake IMS together.  This requires moving a bit
of the program key setup code further down so that it gets the right values
out of the final surface.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Get rid of brw_blorp_surface_info::array_layout

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Use isl_msaa_layout instead of intel_msaa_layout

We also remove brw_blorp_surface_info::msaa_layout.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Use the ISL aux_layout for deciding whether to do an MCS fetch

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Get rid of brw_blorp_surface_info::num_samples

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Make sample count asserts a bit more lazy

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Get rid of brw_blorp_surface_info::map_stencil_as_y_tiled

Now that we're carrying around the isl_surf, we can just modify it
directly instead of passing an extra bit around.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Remove compute_tile_offsets

We have a handy little function is ISL that does exactly the same thing.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Create the isl_surf up-front

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp/clear: Initialize surface info after allocating an MCS

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

isl/state: Use a valid alignment for 1-D textures

The alignment we use doesn't matter (see the comment) but it should at
least be an alignment we can represent with the enums.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masks

It's only used to stomp the tiling to Y and it's only used by blorp so
there's no reason why blorp can't do it itself.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

isl: Fix the parameter names for get_intratile_offset

It's been in elements for a while but, for whatever reason, the parameter
names in the header file never got updated.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

util: try to use SSE instructions with MSVC and 32-bit gcc

The lrint() and lrintf() functions are pretty slow and make some
texture transfers very inefficient.  This patch makes a better effort
at using those intrisics for 32-bit gcc and MSVC.

Note, this patch doesn't address the use of SSE4.1 with MSVC.

v2: get rid of the ROUND_WITH_SSE symbol, per Matt.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

svga: fix src/dst typo in can_blit_via_copy_region_vgpu10()

The function was always returning false because of this typo.

Retested with piglit.  There's some sRGB-related blit failures, but
that seems unrelated.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>

svga: initialize a variable to silence a gcc warning

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

glsl: Pull enum ir_expression_operation out to its own file

No change except to the copyright symbol.  The next patch will generate
this file with Python, and Unicode + Python = pure rage.

v2: Massive rebase... I guess a lot can change in a year.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Make the generated sources build rules more like NIR

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa/st: use llabs instead of abs for long args (v2)

v2: long has 32bit on Windows (Marek)
Signed-off-by: Francesco Ansanelli <francians@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: fix up buffer descriptor upper-bound checking

st/mesa does this too, so we're safe.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium: change pipe_image_view::first_element/last_element -> offset/size

This is required by OpenGL. Our hardware supports this.

Example: Bind RGBA32F with offset = 4 bytes.

Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium: change pipe_sampler_view::first_element/last_element -> offset/size

This is required by OpenGL. Our hardware supports this.

Example: Bind RGBA32F with offset = 4 bytes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97305

Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: assign the highest priority to scratch; make rings second

just FYI, the kernel receives priority/4

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/winsys: re-number winsys priority flags

free 60..63, move CP_DMA up

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: mark shader rings as highest-priority buffers

and rename the enum

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: set SHADER_RW_BUFFER priority for streamout buffers

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: use current context for DCC feedback-loop decompress, fixes Elemental

This is just a workaround. The problem is described in the code.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96541

v2: say that it's only between the current context and aux_context

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)

radeonsi: simplify CB_TARGET_MASK logic

we can now rely on CB_COLORn_INFO to disable empty slots.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't set CB_COLOR1_INFO for dual src blending

Vulkan doesn't do this. The reason may be that CB_COLOR1_INFO.SOURCE_FORMAT
from NI was moved to SPI_SHADER_COL_FORMAT for SI.

I asked CB guys about this 2 days ago and they still haven't replied.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: eliminate PS OUT[1] if dual src blending is off and CB1 is not bound

All VP DX9 ports benefit from this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: use unflushed fences for PIPE_QUERY_GPU_FINISHED

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: use lp_build_alloca_undef

Avoid building all those store 0 / store undef instruction pairs that
end up getting removed anyway.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallivm: add lp_build_alloca_undef

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallivm: add create_builder_at_entry helper function

Reduces code duplication.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: protect against out of bounds temporary array accesses

They can lead to VM faults and worse, which goes against the GL robustness
promises.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: add radeon_llvm_bound_index for bounds checking

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: reduce alloca of temporaries based on usagemask

v2: take actual writemasks into account

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: use tgsi_scan_arrays for temp arrays

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: allocate temps array info in radeon_llvm_context_init

Also, prepare for using tgsi_array_info.

This also opens the door for properly handling allocation failures, but I'm
leaving that for a separate change.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: always do the full store in store_value_to_array

Doing the write-back of the temporary vector in radeon_llvm_emit_store makes
no sense.

This also allows us to get rid of get_alloca_for_array.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: extract common getelementptr logic into get_pointer_into_array

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: pass indirect register info into get_alloca_for_array

To have the same signature as get_array_range.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: extract common lookup code into get_temp_array function

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: clarify the comment on the array alloca heuristic

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: more descriptive names for LLVM temporaries in debug builds

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: simplify radeon_llvm_emit_store for direct array addressing

We can use the pointer stored in the temps array directly.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: simplify radeon_llvm_emit_fetch for direct array addressing

We can use the pointer stored in the temps array directly.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: clean up emit_declaration for temporaries

In the alloca'd array case, no longer create redundant and unused allocas
for the individual elements; create getelementptrs instead.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st_glsl_to_tgsi: use calloc the way it's meant to be used

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

tgsi/scan: add tgsi_scan_arrays

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: Add missing ir_quadop_vector constant evaluation for Boolean types

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Fix typo in ir_unop_f2u implementation

This won't affect the output, but it was, technically, wrong.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Fix typo in ir_unop_b2i implementation

This won't affect the output, but it was, technically, wrong.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Don't support integer types for operations that can't handle them

ir_unop_fract already forbade integer types in ir_validate.  ir_unop_rcp,
ir_unop_rsq, and ir_unop_sqrt should also forbid them in ir_validate.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Don't support ir_unop_abs or ir_unop_sign for unsigned integers

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nir/algebraic: Optimize common array indexing sequence

Some shaders include code that looks like:

   uniform int i;
   uniform vec4 bones[...];

   foo(bones[i * 3], bones[i * 3 + 1], bones[i * 3 + 2]);

CSE would do some work on this:

   x = i * 3
   foo(bones[x], bones[x + 1], bones[x + 2]);

The compiler may then add '<< 4 + base' to the index calculations.
This results in expressions like

   x = i * 3
   foo(bones[x << 4], bones[(x + 1) << 4], bones[(x + 2) << 4]);

Just rearranging the math to produce (i * 48) + 16 saves an
instruction, and it allows CSE to do more work.

   x = i * 48;
   foo(bones[x], bones[x + 16], bones[x + 32]);

So, ~6 instructions becomes ~3.

Some individual shader-db results look pretty bad.  However, I have a
really, really hard time believing the change in estimated cycles in,
for example, 3dmmes-taiji/51.shader_test after looking that change in
the generated code.

G45
total instructions in shared programs: 4020840 -> 4010070 (-0.27%)
instructions in affected programs: 177460 -> 166690 (-6.07%)
helped: 894
HURT: 0

total cycles in shared programs: 98829000 -> 98784990 (-0.04%)
cycles in affected programs: 3936648 -> 3892638 (-1.12%)
helped: 894
HURT: 0

Ironlake
total instructions in shared programs: 6418887 -> 6408117 (-0.17%)
instructions in affected programs: 177460 -> 166690 (-6.07%)
helped: 894
HURT: 0

total cycles in shared programs: 143504542 -> 143460532 (-0.03%)
cycles in affected programs: 3936648 -> 3892638 (-1.12%)
helped: 894
HURT: 0

Sandy Bridge
total instructions in shared programs: 8357887 -> 8339251 (-0.22%)
instructions in affected programs: 432715 -> 414079 (-4.31%)
helped: 2795
HURT: 0

total cycles in shared programs: 118284184 -> 118207412 (-0.06%)
cycles in affected programs: 6114626 -> 6037854 (-1.26%)
helped: 2478
HURT: 317

Ivy Bridge
total instructions in shared programs: 7669390 -> 7653822 (-0.20%)
instructions in affected programs: 388234 -> 372666 (-4.01%)
helped: 2795
HURT: 0

total cycles in shared programs: 68381982 -> 68263684 (-0.17%)
cycles in affected programs: 1972658 -> 1854360 (-6.00%)
helped: 2458
HURT: 307

Haswell
total instructions in shared programs: 7082636 -> 7067068 (-0.22%)
instructions in affected programs: 388234 -> 372666 (-4.01%)
helped: 2795
HURT: 0

total cycles in shared programs: 68282020 -> 68164158 (-0.17%)
cycles in affected programs: 1891820 -> 1773958 (-6.23%)
helped: 2459
HURT: 261

Broadwell
total instructions in shared programs: 9002466 -> 8985875 (-0.18%)
instructions in affected programs: 658784 -> 642193 (-2.52%)
helped: 2795
HURT: 5

total cycles in shared programs: 78503092 -> 78450404 (-0.07%)
cycles in affected programs: 2873304 -> 2820616 (-1.83%)
helped: 2275
HURT: 415

Skylake
total instructions in shared programs: 9156978 -> 9140387 (-0.18%)
instructions in affected programs: 682625 -> 666034 (-2.43%)
helped: 2795
HURT: 5

total cycles in shared programs: 75591392 -> 75550574 (-0.05%)
cycles in affected programs: 3192120 -> 3151302 (-1.28%)
helped: 2271
HURT: 425

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

glx: Don't use current context in __glXSendError

There's no guarantee that there is one, and we don't need one anyway.

Fixes piglit tests:

glx@glx-fbconfig-bad
glx@glx_ext_import_context@import context, multi process
glx@glx_ext_import_context@import context, single process

Fixes: 2e3f067458e4 ("glx: fix error code when there is no context bound")
Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

nv50/ir: fix bb positions after exit instructions

It's fairly rare that the BB layout puts BBs after the exit block, which
is likely the reason these issues lingered for so long.

This fixes a fraction of issues with the giant pixmark piano shader.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>

nv50/ir: properly clear upper bits of a bitset fill

Found by inspection. In practice, val is always == 0, so this never got
triggered.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

i965/fs: Estimate maximum sampler message execution size more accurately.

The current logic used to determine the execution size of sampler
messages was based on special-casing several argument and opcode
combinations, which unsurprisingly missed the possibility that some
messages could exceed the payload size limit or not depending on the
number of coordinate components present.  In particular:

 - The TXL, TXB and TEX messages (the latter on non-FS stages only)
   would attempt to use SIMD16 on Gen7+ hardware even if a shadow
   reference was present and the texture was a cubemap array, causing
   it to overflow the maximum supported sampler payload size and
   crash.

 - The TG4_OFFSET message with shadow comparison was falling back to
   SIMD8 regardless of the number of coordinate components, which is
   unnecessary when two coordinates or less are present.

Both cases have been handled incorrectly ever since cubemap arrays and
texture gather were respectively enabled (the current logic used by
the SIMD lowering pass is almost unchanged from the previous no16
fall-back logic used pre-SIMD lowering times).

Fixes the following GL4.5 conformance test on Gen7-8 (the bug also
affects Gen9+ in principle, but SKL passes the test by luck because it
manages to use the TXL_LZ message instead of TXL):

 GL45-CTS.texture_cube_map_array.sampling

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97267
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Return zero from fs_inst::components_read for non-present sources.

This makes it easier for the caller to find out how many scalar
components are actually read by the instruction.  As a bonus we no
longer need to special-case BAD_FILE in the implementation of
fs_inst::regs_read.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Lower TEX to TXL during NIR translation.

This simplifies the code slightly and will allow the SIMD lowering
pass to find out easily what the actual texturing opcode is in order
to determine the maximum execution size of texturing instructions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

freedreno/a3xx: fix generic clear path

Signed-off-by: Rob Clark <robdclark@gmail.com>

st/mesa: use pipe var instead of st->pipe in st_create_context_priv()

As is done in most other places in the function.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: remove unused u_clear.h file

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/i915: inline the util_clear() code into i915_clear_blitter()

This is the only place the util_clear() function was used.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/util: minor reformatting in u_box.h

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

svga: remove unused var in svga_mark_surfaces_dirty()

Signed-off-by: Brian Paul <brianp@vmware.com>

svga: avoid a calloc in svga_buffer_transfer_map()

Just initialize the two other pipe_transfer fields explicitly.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: don't call os_get_time() when not needed by Gallium HUD

The calls to os_get_time() were showing up higher than expected in
profiles.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: remove unneeded memset() call in draw_vgpu10()

All three fields of the vbuffer_attrs[] array are assigned in the following
loop.  The remaining elements of the array are not used.

Tested with full Piglit run, Heaven 4.0, etc.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: reduce looping in svga_mark_surfaces_dirty()

We don't need to loop over the max number of color buffers, just the
current number (which is usually one).

Tested with full Piglit run, Heaven 4.0, etc.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: minor clean-ups in define_rasterizer_object()

Add const qualifiers, new comment.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: remove incorrect buffer invalidation code

Fixes regression with team_fortress_2 trace.
This change has been in our in-house tree for some time.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: additional comments for svga_hw_draw_state members

And re-order a few fields.

Signed-off-by: Brian Paul <brianp@vmware.com>

svga: use the sws local var to simplify some code

Signed-off-by: Brian Paul <brianp@vmware.com>

svga: minor whitespace and code clean-ups

Signed-off-by: Brian Paul <brianp@vmware.com>

freedreno/a4xx: use generic clear path

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a3xx: use generic clear path

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: support for using generic clear path

Since clears are more or less just normal draws, there isn't that much
benefit in having hand-rolled clear path.  Add support to use u_blitter
instead if gen specific backend doesn't implement ctx->clear().

Signed-off-by: Rob Clark <robdclark@gmail.com>

gallium/u_blitter: split out a helper for common clear state

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/u_blitter: add helper to save FS const buffer state

Not (currently) state that is overwridden by u_blitter itself, but
drivers with custom blit/clear which are reusing part of the u_blitter
infrastructure will use it.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/u_blitter: export some functions

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

egl/dri2: dri2_make_current: Release previous context's display

eglMakeCurrent can also be used to change the active display. In that
case, we need to decrement ref_count of the previous display (possibly
destroying it), and increment it on the next display.

Also, old_dsurf/old_rsurf cannot be non-NULL if old_ctx is NULL, so
we only need to test if old_ctx is non-NULL.

v2: Save the old display before destroying the context.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97214
Fixes: 9ee683f877 (egl/dri2: Add reference count for dri2_egl_display)
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reported-by: Alexandr Zelinsky <mexahotabop@w1l.ru>
Tested-by: Alexandr Zelinsky <mexahotabop@w1l.ru>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>

st/vdpau: change the order in which filters are applied(v3)

Apply the median and matrix filter before the compostioning
we apply the deinterlacing first to avoid the extra overhead
in processing the past and the future surfaces in deinterlacing.

v2: apply the filters on all the surfaces (Christian)
v3: use get_sampler_view_planes() instead of
    get_sampler_view_components() and iterate over
    VL_MAX_SURFACES (Christian)

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

glcpp: Update tests for new #undef of built-in macro rules.

Ian recently changed the preprocessor to allow this in most GLSL
versions, but not GLSL ES 3.00+.  This patch converts the existing
test that expects a failure to a #version 300 es shader, and adds
a #version 110 shader to make sure that it's allowed.

Fixes 'make check'.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97307
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>

anv: fix writemask on blit fragment shader.

I'm not sure if anything even uses this, but I found this on radv, so
just fix it on anv for consistency.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>

egl/android: Set dpy->DriverData to NULL on error

Avoid use-after-free on error.

Fixes: 9ee683f877 (egl/dri2: Add reference count for dri2_egl_display)
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl/drm: Set disp->DriverData to NULL on error

Avoid use-after-free on error.

Fixes: 9ee683f877 (egl/dri2: Add reference count for dri2_egl_display)
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl/surfaceless: Set disp->DriverData to NULL on error

Avoid use-after-free on error.

Fixes: 9ee683f877 (egl/dri2: Add reference count for dri2_egl_display)
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>