i965/nir/vec4: Implement nir_emit_jump

This implementation is taken as-is from fs_nir.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Mark as unreachable ops that should be already lowered

NIR ALU operations:
   * nir_op_fabs
   * nir_op_iabs
   * nir_op_fneg
   * nir_op_ineg
   * nir_op_fsat
        should be lowered by lower_source mods

   * nir_op_fdiv
        should be lowered in the compiler by DIV_TO_MUL_RCP.

   * nir_op_fmod
        should be lowered in the compiler by MOD_TO_FLOOR.

   * nir_op_fsub
   * nir_op_isub
        should be handled by ir_sub_to_add_neg.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement vector "any" operation

Adds NIR ALU operations:
   * nir_op_bany2
   * nir_op_bany3
   * nir_op_bany4

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement the dot product operation

Adds NIR ALU operations:
   * nir_op_fdot2
   * nir_op_fdot3
   * nir_op_fdot4

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement conditional select

Adds NIR ALU operations:
   * nir_op_bcsel

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement linear interpolation

Adds NIR ALU operation:
   * nir_op_flrp

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/vec4: Return the emitted instruction in emit_lrp()

Needed in the NIR backend to set the "saturate" value of the
instruction.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement floating-point fused multiply-add

Adds NIR ALU operation:
   * nir_op_ffma

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement "shift" operations

Adds NIR ALU operations:
   * nir_op_ishl
   * nir_op_ishr
   * nir_op_ushr

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement the "sign" operation

Follows the vec4_visitor IR implementation but
sets the saturate value in addition.

Adds NIR ALU operations:
   * nir_op_fsign
   * nir_op_isign

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement bit operations

Same implementation than the IR case.

Adds NIR ALU operations:
   * nir_op_bitfield_reverse
   * nir_op_bit_count
   * nir_op_ufind_msb
   * nir_op_ifind_msb
   * nir_op_find_lsb
   * nir_op_ubitfield_extract
   * nir_op_ibitfield_extract
   * nir_op_bfm
   * nir_op_bfi
   * nir_op_bitfield_insert

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement pack/unpack operations

* Lowered floating-point pack and unpack operations are not valid in VS.

* Pack and unpack 2x16 operations should be handled by lower_packing_builtins.

* Adds NIR ALU operations:
   * nir_op_pack_half_2x16
   * nir_op_unpack_half_2x16
   * nir_op_unpack_unorm_4x8
   * nir_op_unpack_snorm_4x8
   * nir_op_pack_unorm_4x8
   * nir_op_pack_snorm_4x8

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: "noise" ops should already be lowered

Marked them as unreachable.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement "bool<->int,float" format conversion

Used the same implementation than the vec4_visitor NIR.

Adds NIR ALU operations:
   * nir_op_b2i
   * nir_op_b2f
   * nir_op_f2b
   * nir_op_i2b

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement logical operators

Adds NIR ALU operations:
   * nir_op_inot
   * nir_op_ixor
   * nir_op_ior
   * nir_op_iand

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement non-equality ops on vectors

Adds NIR ALU operations:
   * nir_op_bany_fnequal2
   * nir_op_bany_inequal2
   * nir_op_bany_fnequal3
   * nir_op_bany_inequal3
   * nir_op_bany_fnequal4
   * nir_op_bany_inequal4

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement equality ops on vectors

Adds NIR ALU operations:
   * nir_op_ball_fequal2
   * nir_op_ball_iequal2
   * nir_op_ball_fequal3
   * nir_op_ball_iequal3
   * nir_op_ball_fequal4
   * nir_op_ball_iequal4

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement non-vector comparison ops

Adds NIR ALU operations:
   * nir_op_flt
   * nir_op_ilt
   * nir_op_ult
   * nir_op_fge
   * nir_op_ige
   * nir_op_uge
   * nir_op_feq
   * nir_op_ieq
   * nir_op_fne
   * nir_op_ine

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir: Add utility method for comparisons

This method returns the brw_conditional_mod value used when emitting
comparative ALU operations.

It could be moved to brw_nir in the future to reuse it in fs_nir backend.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Derivatives are not allowed in VS

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement min/max operations

Adds NIR ALU operations:
   * nir_op_fmin
   * nir_op_imin
   * nir_op_umin
   * nir_op_fmax
   * nir_op_imax
   * nir_op_umax

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/vec4: Return the emitted instruction in emit_minmax()

Needed in the NIR backend to set the "saturate" value of the
instruction.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement various rounding functions

Adds NIR ALU operations:
   * nir_op_ftrunc
   * nir_op_fceil
   * nir_op_ffloor
   * nir_op_ffrac
   * nir_op_fround_even

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement carry/borrow for addition/subtraction

Adds NIR ALU operations:
   * nir_op_uadd_carry
   * nir_op_usub_borrow

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement more math operations

Adds NIR ALU operations:
   * nir_op_frcp
   * nir_op_fexp2
   * nir_op_flog2
   * nir_op_fexp
   * nir_op_flog
   * nir_op_fsin
   * nir_op_fcos
   * nir_op_idiv
   * nir_op_udiv
   * nir_op_umod
   * nir_op_ldexp
   * nir_op_fsqrt
   * nir_op_frsq
   * nir_op_fpow

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/vec4: Return the last emitted instruction in emit_math()

Needed in the NIR backend to set the "saturate" value of the
instruction.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement multiplication

Implementation based on the vec4_visitor IR implementation
for the operations ir_binop_mul and ir_binop_imul_high.

Adds NIR ALU operations:
   * nir_op_fmul
   * nir_op_imul
   * nir_op_imul_high
   * nir_op_umul_high

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement the addition operation

Adds NIR ALU operations:
   * nir_op_fadd
   * nir_op_iadd

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement int<->float format conversion ops

Adds NIR ALU operations:
   * nir_op_f2i
   * nir_op_f2u
   * nir_op_i2f
   * nir_op_u2f

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Lower "vecN" instructions and mark them unreachable

This enables NIR pass "lower_vec_to_movs" on shaders that work on vec4.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement single-element "mov" operations

Adds NIR ALU operations:
   * nir_op_imov
   * nir_op_fmov

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir: Disable alu_to_scalar pass on non-scalar shaders

Disables nir_lower_alu_to_scalar when the shader stage being processed work
on vec4 vectors, like the upcoming NIR->vec4 backend.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Prepare source and destination registers for ALU operations

This patch resolves and initializes the destination and the source
registers that are common to most ALU operations.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement loading values from an UBO

Based on the vec4_visitor IR implementation for the ir_binop_load_ubo
operation. Notice that unlike the vec4_visitor IR, adding the !=0
comparison for UBO bools is not needed here because that comparison is
already added by the nir_visitor when processing the ir_binop_load_ubo
(in UBOs "true" is any value different from zero, but for us is ~0).

Adds NIR instrinsics:

   * nir_intrinsic_load_ubo_indirect
   * nir_intrinsic_load_ubo

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement atomic counter intrinsics (read, inc and dec)

The implementation is based on its fs_nir counterpart.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement load_uniform intrinsic

For the indirect case we need to take the index delivered by
NIR and compute the parent uniform that we are accessing (the one
that we uploaded to a surface) and the constant offset into that
surface.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement intrinsics that load system values

These include:

nir_intrinsic_load_vertex_id_zero_base
nir_intrinsic_load_base_vertex
nir_intrinsic_load_instance_id

The source register is fetched from the nir_system_values map initialized
during nir_setup_system_values stage.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement store_output intrinsic

This implementation is based on the current URB setup in vec4_visitor, which
requires the output register to be stored in the output_reg array at variable's
original shader location index. But since nir_lower_io() pass uses the value
in var->data.driver_location, we need to put there var->data.location instead,
prior to calling nir_lower_io(), so that we end up with the correct index
in const_index[0].

The driver_location is not used at all, so this patch also disables the
nir_assign_var_locations pass on non-scalar shaders.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/vec4: Make sure that register types always match during emit_urb_slot()

Instead of relying on backends (currently vec4_visitor and soon NIR-vec4) to
store registers in output_reg with the correct type, this patch makes sure
that the common code in emit_urb_slot() always emit MOVs from output registers
using the same type on source and destination.

Since the actual type is not important, only that they match, we default to
float.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement load_input intrinsic

The source register is fetched from the nir_inputs map built during
nir_setup_inputs stage.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement loop statements (nir_cf_node_loop)

This is taken as-is from fs_nir.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement conditional statements (nir_cf_node_if)

The same we do in the FS NIR backend, only that here we need to consider
the number of components in the condition and adjust the swizzle
accordingly.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Add get_nir_dst() and get_nir_src() methods

These methods are essential for the implementation of the NIR->vec4 pass. They
work similar to their fs_nir counter-parts.

When processing instructions, these methods are invoked to resolve the
brw registers (source or destination) corresponding to the NIR sources
or destination. It uses the map of NIR register index to brw register for
all registers locally allocated in a block.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir: Move brw_type_for_nir_type() to brw_nir to allow reuse

Upcoming NIR->vec4 pass can benefit from this method, so lets move it up.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Implement load_const intrinsic

Similar to fs_nir backend, a nir_local_values map will be filled with
newly allocated registers as the load_const instrinsic instructions are
processed. Later, get_nir_src() will fetch the registers from this map
for sources that are ssa.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/vec4: Add auxiliary func to build a writemask from a component size

New method brw_writemask_for_size() will return a writemask with the first
'size' components activated.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir: Dot not assign direct uniform locations first for vec4-based shaders

In the vec4 backend we want uniform locations to be assigned consecutively
since that way the offsets produced by nir_lower_io are exactly what we
need to implement nir_intrinsic_load_uniform. Otherwise we would need a
mapping to match the output of nir_lower_io to the actual uniform registers
we need to use.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

nir/nir_lower_io: Add vec4 support

The current implementation operates in scalar mode only, so add a vec4
mode where types are padded to vec4 sizes.

This will be useful in the i965 driver for its vec4 nir backend
(and possbly other drivers that have vec4-based shaders).

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir: Pass a is_scalar boolean to brw_create_nir()

The upcoming introduction of NIR->vec4 pass will require that some NIR
lowering passes are enabled/disabled depending on the type of shader
(scalar vs. vector).

With this patch we pass a 'is_scalar' variable to the process of
constructing the NIR, to let an external context decide how the shader
should be handled.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Add shader function implementation

It basically allocates registers local to a function in a nir_locals map,
then emits all its control-flow blocks.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Add setup for system values

Similar to other variable setups, system values will initialize the
corresponding register inside a 'nir_system_values' map, which will then
be queried later when processing the different system value intrinsics
for the appropriate register.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/vec4: Redefine make_reg_for_system_value() to allow reuse in NIR->vec4 pass

The new virtual method is more flexible, it has a signature:

dst_reg *make_reg_for_system_value(int location, const glsl_type *type);

v2 (Jason Ekstrand):
   Use the new version in unit tests so make check passes again

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Add setup of uniform variables

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Add setup of input variables in NIR->vec4 pass

This implementation sets up a map of input variable offsets to source registers
that are already initialized with the corresponding register offset.

This map will then be queried when processing load_input intrinsic operations,
to obtain the correct register source from which the input data will be loaded.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/vec4: Move type_size() method to brw_vec4_visitor class

The type_size() method is currently accessible only in the implementation
of vec4_visitor. Since we need to reuse it in the upcoming NIR->vec4 pass,
lets make it a method of the class instead.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Select between new nir_vec4 or current vec4_visitor code-paths

The NIR->vec4 pass will be activated if both the following conditions are met:

* INTEL_USE_NIR environment variable is defined and is positive (1 or true)
* The stage is vertex shader (support for geometry shaders and
  ARB_vertex_program will be added later).

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/nir/vec4: Add implementation placeholders for a new NIR->vec4 pass

This patch will add a brw_vec4_nir.cpp file filled with entry point methods to
the main functionality, following a structure similar to brw_fs_nir.cpp.

Subsequent patches in this series will be adding the implementations for these
methods, incrementally.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

mesa: Replace F_TO_I() with _mesa_lroundevenf().

I'm not sure what the true meaning of "The rounding mode may vary." is,
but it is the case that the IROUND() path rounds differently than the
other paths (and does it wrong, at that).

Like _mesa_roundeven{f,}(), just add an use _mesa_lroundeven{f,}() that
has known semantics.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: Add -fno-trapping-math to CFLAGS.

Cuts about 1k of .text size.

   text    data     bss     dec     hex filename
4983676  197808   26328 5207812  4f7704 i965_dri.so before
4982522  197800   26328 5206650  4f727a i965_dri.so after

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: Add -fno-math-errno to CFLAGS.

Cuts about 9k of .text size.

   text    data     bss     dec     hex filename
4992804  197808   26328 5216940  4f9aac i965_dri.so before
4983676  197808   26328 5207812  4f7704 i965_dri.so after

Also, Darwin's libm does not ever set errno, so if we care about those
systems we shouldn't rely on errno anyway.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

r600,compute: force tiling on 2D and 3D texture compute resources

To circumvent a problem occuring when LINEAR_ALIGNED array mode is
selected on a TEXTURE_2D RAT.
This configuration causes MEM_RAT STORE_TYPED to write to incorrect
locations.

clover: handle setKernelArg errors

clover: fix image resource depth and array_size

nir: Use a single bit for the dual-source blend index

The only values allowed are 0 and 1, and the value is checked before
assigning.

This is a copy of 8eeca7a56c that seems to have been made to the glsl
ir type after it was copied for use in nir but before nir landed.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

clover: pass image attributes to the kernel

Read-only and write-only image arguments are recognized and
distinguished.
Attributes of the image arguments are passed to the kernel as implicit
arguments.

clover: move find_kernels to functions

mesa: fix type for array indexing validation

parse_program_resource_name returns -1 when the index is invalid this needs to
be tested before assigning the value to the unsigned array_index.

In link_varyings.cpp (the other place parse_program_resource_name is used) after
the -1 check is done the value is just assigned to an unsigned variable so it
seems long is just used so we can return the -1 rather than actually expecting
index values to be ridiculously large.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa/es3.1: Allow multisampled textures for GLES 3.1

GLES 3.1 must be allowed to create multisampled textures.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa/es3.1: Allow query of GL_TEXTURE_MULTISAMPLE

GLES 3.1 must allow a query for GL_TEXTURE_MULTISAMPLE.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa/es3.1: Allow enable of GL_SAMPLE_MASK

GLES 3.1 must be able to enable GL_SAMPLE_MASK.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa/es3.1: Allow textures with target GL_TEXTURE_2D_MULTISAMPLE

GLES 3.1 should be able to bind a texture with the target
GL_TEXTURE_2D_MULTISAMPLE.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa/es3.1: Allow GL_DEPTH_STENCIL_TEXTURE_MODE

GLES 3.1 must support the parameter GL_DEPTH_STENCIL_TEXTURE_MODE.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa/es3.1: Allow GL_SAMPLE_MASK

GLES 3.1 should be allowed to enable GL_SAMPLE_MASK.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa/es3.1: Allow binding GL_DRAW_INDIRECT_BUFFER with gles 3.1

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

r600g: re-enable single-sample fast clear

Fixed by the CB_SHADER_MASK fix.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>

r600g: fix the CB_SHADER_MASK setup

This fixes the single-sample fast clear hang.

Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>

r600g: fix the single-sample fast clear setup

No effect, but this is what we should be doing.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radeonsi: flush if the memory usage for an IB is too high

Picked from the amdgpu branch.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

opencl: use versioned .so in mesa.icd

We must have versioned library in mesa.icd, because ICD loader would
fail if the mesa-devel package wasn't installed.

Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Reported-by: Fabian Deutsch <fabian.deutsch@gmx.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73512
Signed-off-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>

includes/GL: remove duplicated extension declarations from glx.h

All three of GLX_NV_float_buffer, GLX_EXT_texture_from_pixmap and
GLX_MESA_query_renderer have been in glxext.h for a while now.

As such we can drop this workaround/hack from the header.

v2: Remove the comment about GLX_NV_float_buffer.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v1)

docs: rename/bump 10.7.0 release notes to 11.0.0

Recently a few drivers have grown OpenGL 4+ support so we might as
well go all the way to... 11 ;-)

v2: Don't forget to update the version file (Ilia)

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

winsys/radeon: don't leak the fd when it is 0

Earlier commit added an extra dup(fd) to fix a ZaphodHeads issue.
Although it did not consider the (very unlikely) case where we might end
up with the valid fd == 0.

Fixes: 28dda47ae4d(winsys/radeon: Use dup fd as key in drm-winsys hash
table to fix ZaphodHeads.)

Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Mario Kleiner <mario.kleiner.de@gmail.com>

configure.ac: check for mkostemp()

We can make use of it over mkstemp + fcntl in the egl/wayland code.

Cc: Axel Davy <axel.davy@ens.fr>
Suggested-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl/wayland: use drmGetNodeTypeFromFd helper instead of opencoding it

Cc: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Boyan Ding <boyan.j.ding@gmail.com>

egl/wayland: use designated initializers

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

egl: remove ifdef $(egl_extension) compile guards

All of these are already defined in the headers provided.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl/wayland: libdrm is a hard requirement, treat it as such

Prompt at configure time if it's missing otherwise we'll fail later on
in the build. Remove ambiguous HAVE_LIBDRM guard.

Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl: consolidate ifdef HAVE_LIBDRM blocks

Move the code around rather than having it scattered. No functional
change.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

configure.ac: null,android,gdi are not valid egl-platforms

... and update the documentation to reflect reality.
null and gdi are gone, and surfaceless is a recent addition.

v2: s/platforms/platform/ (spotted by Thomas)

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

Revert "gallium/radeon: re-enable unsafe math for graphics shaders"

This reverts commit 8559f6ce62a9d5b52fa8189ba2352cd48bdabccf.

It causes hangs in DOTA 2 Reborn.

clover: make dispatch matches functions def

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

gallivm: Fix GCC unused-variable warning.

lp_bld_tgsi_soa.c: In function 'lp_emit_immediate_soa':
lp_bld_tgsi_soa.c:3065:18: warning: unused variable 'size' [-Wunused-variable]
       const uint size = imm->Immediate.NrTokens - 1;
                  ^

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

glx: Fix missing bit decl for EXT_texture_integer

Missing from:

    commit b15aba940a3b6fc7c9bebc692968e7e9b72b9f29
    Author: Adam Jackson <ajax@redhat.com>
    Date:   Tue Jul 21 11:43:42 2015 -0400

glx: Fix image size computation for EXT_texture_integer (v2)

Signed-off-by: Adam Jackson <ajax@redhat.com>

glsl: Initialize parse-state in constructor of lower_subroutine.

Static analysis tools don't like partial object initializations.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

glx: Fix image size computation for EXT_texture_integer (v2)

Without this this extension basically can't work in indirect contexts,
TexImage2D will compute the image size as 0 and we'll send no image data
to the server.

v2: Add EXT_texture_integer to the client extension list too (Ian)

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Adam Jackson <ajax@redhat.com>

radeonsi: copy *8_SNORM bits exactly in resource_copy_region

Disabling the FP16 mode didn't help.

If needed, we can use this trick for blits too, but not for scaled blits.

+ 4 piglits

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: early exit in r600_clear if there's nothing to do

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: early exit in si_clear if there's nothing to do

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: fix a regression since the resource_copy_region cleanup

Broken since:
    46b2b3b - radeonsi: don't change pipe_resource in resource_copy_region

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91444

Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: fix broken st/nine from merging tessellation

st/nine uses GENERIC slots greater than 60.