i965/nir: Dot not assign direct uniform locations first for vec4-based shaders

In the vec4 backend we want uniform locations to be assigned consecutively
since that way the offsets produced by nir_lower_io are exactly what we
need to implement nir_intrinsic_load_uniform. Otherwise we would need a
mapping to match the output of nir_lower_io to the actual uniform registers
we need to use.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c
index 8700cb71ad409b1e5a812c138ff80ece69ef840a..d81d82323bb09acca35fba2425c677d7cda66002 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -101,10 +101,16 @@ brw_create_nir(struct brw_context *brw,
    /* Get rid of split copies */
    nir_optimize(nir);
 
-   nir_assign_var_locations_direct_first(nir, &nir->uniforms,
-                                         &nir->num_direct_uniforms,
-                                         &nir->num_uniforms,
-                                         is_scalar);
+   if (is_scalar) {
+      nir_assign_var_locations_direct_first(nir, &nir->uniforms,
+                                            &nir->num_direct_uniforms,
+                                            &nir->num_uniforms,
+                                            is_scalar);
+   } else {
+      nir_assign_var_locations(&nir->uniforms,
+                               &nir->num_uniforms,
+                               is_scalar);
+   }
    nir_assign_var_locations(&nir->inputs, &nir->num_inputs, is_scalar);
    nir_assign_var_locations(&nir->outputs, &nir->num_outputs, is_scalar);