mesa.git
9 years agonir: Add an invalid type
Jason Ekstrand [Thu, 29 Jan 2015 00:27:40 +0000 (16:27 -0800)]
nir: Add an invalid type

This allows us to indicate a concept of an invalid type.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agogallium/docs: fix docs wrt ARL/ARR/FLR
Roland Scheidegger [Thu, 29 Jan 2015 19:39:50 +0000 (20:39 +0100)]
gallium/docs: fix docs wrt ARL/ARR/FLR

since the address reg holds integer values, ARL/ARR do an implicit float-to-int
conversion, so clarify that. Thus it is also incorrect to say that FLR really
does the same as ARL.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
9 years agonir: Add variants of some of the comparison simplifications.
Eric Anholt [Tue, 27 Jan 2015 00:48:48 +0000 (16:48 -0800)]
nir: Add variants of some of the comparison simplifications.

We end up with these from TGSI-to-NIR because the pass generating the
comparisons doesn't know if the arg is actually a bool input or not.  vc4
results:

total instructions in shared programs: 41801 -> 41508 (-0.70%)
instructions in affected programs:     4253 -> 3960 (-6.89%)

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agovc4: Fix point size handling when it's the first output.
Eric Anholt [Thu, 29 Jan 2015 19:33:42 +0000 (11:33 -0800)]
vc4: Fix point size handling when it's the first output.

9 years agonir: Don't try to to-SSA ALU instructions that are already SSA.
Eric Anholt [Mon, 26 Jan 2015 22:37:42 +0000 (14:37 -0800)]
nir: Don't try to to-SSA ALU instructions that are already SSA.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Fix a bit of broken indentation.
Eric Anholt [Tue, 11 Nov 2014 22:08:13 +0000 (14:08 -0800)]
nir: Fix a bit of broken indentation.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Add a couple of helpers for glsl types.
Eric Anholt [Thu, 30 Oct 2014 23:49:32 +0000 (16:49 -0700)]
nir: Add a couple of helpers for glsl types.

This will be used by tgsi_to_nir, which needs to get vec4 types for
declaring shader input/output variables.

v2: Add a missing space.

Reviewed-by: Matt Turner <mattst88@gmail.com> (v2)
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agodocs: fix mesa 10.4.3 release date
Emil Velikov [Thu, 29 Jan 2015 14:02:19 +0000 (14:02 +0000)]
docs: fix mesa 10.4.3 release date

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
9 years agoMesa: Advertise GL_OES_texture_*float* extensions support with i965.
Kalyan Kondapally [Thu, 8 Jan 2015 04:30:27 +0000 (20:30 -0800)]
Mesa: Advertise GL_OES_texture_*float* extensions support with i965.

This patch advertises support for GL_OES_texture_*float* extensions
when using i965 drivers.

Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
9 years agoMesa: Add support for HALF_FLOAT_OES type.
Kalyan Kondapally [Tue, 27 Jan 2015 07:23:00 +0000 (09:23 +0200)]
Mesa: Add support for HALF_FLOAT_OES type.

This patch adds needed support for accepting HALF_FLOAT_OES as valid type
for TexImage*D and TexSubImage*D when Texture FLoat extensions are supported.

Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
9 years agoMesa: Add support for GL_OES_texture_*float* extensions.
Kalyan Kondapally [Thu, 8 Jan 2015 04:30:25 +0000 (20:30 -0800)]
Mesa: Add support for GL_OES_texture_*float* extensions.

This patch series adds support for following GLES2 Texture Float extensions:
1)GL_OES_texture_float,
2)GL_OES_texture_half_float,
3)GL_OES_texture_float_linear,
4)GL_OES_texture_half_float_linear.

This patch adds basic infrastructure and needed boolean flags to advertise
support for these extensions, by default the support is disabled. Next patch
in the series introduces support for HALF_FLOAT_OES token.

v4: take assert away and make valid_filter_for_float conditional (Tapani),
    fix the alphabetical order (Emil)

Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
9 years agonir: Make vec-to-movs handle src/dest aliasing.
Eric Anholt [Thu, 22 Jan 2015 21:08:59 +0000 (13:08 -0800)]
nir: Make vec-to-movs handle src/dest aliasing.

It now emits vector MOVs instead of a series of individual MOVs, which
should be useful to any vector backends.  This pushes the problem of
src/dest aliasing of channels on a scalar chip to the backend, but if
there are any vector operations in your shader then you needed to be
handling this already.

Fixes fs-swap-problem with my scalarizing patches.

v2: Rename to insert_mov(), and add a comment about what it does.
v3: Rewrite the comment.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (v3)
9 years agogallium: Replace u_simple_list.h with util/simple_list.h
Eric Anholt [Fri, 14 Nov 2014 20:40:46 +0000 (12:40 -0800)]
gallium: Replace u_simple_list.h with util/simple_list.h

The code was exactly the same, except util/ has c++ guards and a struct
simple_node declaration.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
9 years agomesa: Port a variant of 68afbe89c72d085dcbbf2b264f0201ab73fe339e to util/
Eric Anholt [Mon, 26 Jan 2015 19:34:18 +0000 (11:34 -0800)]
mesa: Port a variant of 68afbe89c72d085dcbbf2b264f0201ab73fe339e to util/

The idea is that after a remove_from_list(), you might want to be able to
do a remove_from_list() on it again or an is_empty_list().  This is
apparently relied on by r300g.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
9 years agomesa: Move simple_list.h to src/util.
Eric Anholt [Fri, 14 Nov 2014 20:14:40 +0000 (12:14 -0800)]
mesa: Move simple_list.h to src/util.

We have two copies of it in the tree, I'm going to delete one.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
9 years agoradeonsi: Enable VGPR spilling for all shader types v5
Tom Stellard [Wed, 10 Dec 2014 14:13:59 +0000 (09:13 -0500)]
radeonsi: Enable VGPR spilling for all shader types v5

v2:
  - Only emit write SPI_TMPRING_SIZE once per packet.
  - Use context global scratch buffer.

v3:
  - Patch shaders using WRITE_DATA packet instead of map/unmap.
  - Emit ICACHE_FLUSH, CS_PARTIAL_FLUSH, PS_PARTIAL_FLUSH, and
    VS_PARTIAL_FLUSH when patching shaders.

v4:
  - Code cleanups.
  - Remove unnecessary multiplies.

v5:
  - Patch shaders in system memory and re-upload to vram.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agoradeonsi/compute: Allocate the scratch buffer during state creation
Tom Stellard [Tue, 27 Jan 2015 16:35:21 +0000 (16:35 +0000)]
radeonsi/compute: Allocate the scratch buffer during state creation

This moves scratch buffer allocation from si_launch_grid() to
si_create_compute_state().  This helps to reduce the overhead of
launching a kernel and also fixes a bug in the code that would cause
the scratch buffer to be too small if a kernel with smaller scratch size
was launched before a kernel with a larger scratch size.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agoradeonsi: Add radeon_shader_binary member to struct si_shader
Tom Stellard [Fri, 23 Jan 2015 22:54:43 +0000 (22:54 +0000)]
radeonsi: Add radeon_shader_binary member to struct si_shader

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agoradeonsi/compute: Rename si_compute::program to si_compute::shader
Tom Stellard [Fri, 23 Jan 2015 22:54:08 +0000 (22:54 +0000)]
radeonsi/compute: Rename si_compute::program to si_compute::shader

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agoradeonsi: Avoid leaking memory when rebuilding shader states
Marek Olšák [Tue, 27 Jan 2015 14:52:37 +0000 (14:52 +0000)]
radeonsi: Avoid leaking memory when rebuilding shader states

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agonir/opcodes: Use a return type of tfloat for ldexp
Jason Ekstrand [Wed, 28 Jan 2015 20:43:47 +0000 (12:43 -0800)]
nir/opcodes: Use a return type of tfloat for ldexp

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoRevert "util: Move the alternate fpclassify implementation to util"
Jason Ekstrand [Wed, 28 Jan 2015 20:42:47 +0000 (12:42 -0800)]
Revert "util: Move the alternate fpclassify implementation to util"

This reverts commits d6eb572905e39c36168b8f5da240af961f9dde0a and
58e8468d113c7d3d4a59ea4a8d70fd45b78e85e6.

This is no longer necessary as we aren't using it in NIR anymore.  Also, it
broke the build on some strange systems so let's put it back in querymatrix
where it came from.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88852

Acked-by: Matt Turner <mattst88@gmail.com>
9 years agoRevert "nir/opcodes: Use fpclassify() instead of isnormal() for ldexp"
Jason Ekstrand [Wed, 28 Jan 2015 20:41:44 +0000 (12:41 -0800)]
Revert "nir/opcodes: Use fpclassify() instead of isnormal() for ldexp"

This reverts commit d7d340fb2f68c46bd5a0008ecf53c6693e29c916.

We have an isnormal() implementation available, the only problem was that
we had the wrong return type (fixed in a later patch).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88806

Acked-by: Matt Turner <mattst88@gmail.com>
9 years agoutil: Predicate the fpclassify fallback on !defined(__cplusplus)
Jason Ekstrand [Wed, 28 Jan 2015 18:38:01 +0000 (10:38 -0800)]
util: Predicate the fpclassify fallback on !defined(__cplusplus)

The problem is that the fallbacks we have at the moment don't work in C++.
While we could theoretically fix the fallbacks it would also raise the
issue of correctly detecting the fpclassify function.  So, for now, we'll
just disable it until we actually have a C++ user.

Reported-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: EdB <edb+mesa@sigluy.net>
9 years agodrirc: set allow_glsl_extension_directive_midshader for Dead Island.
Sven Arvidsson [Mon, 8 Dec 2014 18:43:09 +0000 (19:43 +0100)]
drirc: set allow_glsl_extension_directive_midshader for Dead Island.

Signed-off-by: Sven Arvidsson <sa@whiz.se>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87076
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
9 years agonir/opcodes: Use fpclassify() instead of isnormal() for ldexp
Jason Ekstrand [Mon, 26 Jan 2015 22:21:15 +0000 (14:21 -0800)]
nir/opcodes: Use fpclassify() instead of isnormal() for ldexp

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88806
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
9 years agoutil: Move the alternate fpclassify implementation to util
Jason Ekstrand [Mon, 26 Jan 2015 22:19:30 +0000 (14:19 -0800)]
util: Move the alternate fpclassify implementation to util

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
9 years agoi965/tex: Don't create read-write textures with non-renderable formats
Jason Ekstrand [Tue, 27 Jan 2015 22:18:57 +0000 (14:18 -0800)]
i965/tex: Don't create read-write textures with non-renderable formats

I haven't actually seen this bug in the wild, but it's possible that
someone could ask to do a S3TC PBO download or something.  This protects us
from accidentally creating a render target with a compressed or otherwise
non-renderable format.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/gen8: Include the buffer offset when emitting renderbuffer relocs
Jason Ekstrand [Tue, 27 Jan 2015 22:06:44 +0000 (14:06 -0800)]
i965/gen8: Include the buffer offset when emitting renderbuffer relocs

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88792
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agomesa: improve error messaging for format CSV parser
Tapani Pälli [Mon, 26 Jan 2015 10:35:23 +0000 (12:35 +0200)]
mesa: improve error messaging for format CSV parser

Patch adds 2 error messages that point user directly to fix
mispelled or impossible swizzle field for a format.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoclover/llvm: Dump the OpenCL C code earlier.
EdB [Wed, 28 Jan 2015 00:20:38 +0000 (02:20 +0200)]
clover/llvm: Dump the OpenCL C code earlier.

[ Francisco Jerez: As discussed on the mailing list, this is intended
  to produce more useful debug output in cases where the compilation
  terminates unexpectedly. ]

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
9 years agoclover/llvm: Move CLOVER_DEBUG stuff into anonymous namespace.
EdB [Sun, 14 Dec 2014 10:31:21 +0000 (11:31 +0100)]
clover/llvm: Move CLOVER_DEBUG stuff into anonymous namespace.

[ Francisco Jerez: As we're at it make debug_options[] local to its
  only user and remove temporary. ]

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
9 years agor600g: add support for primitive id without geom shader (v2)
Dave Airlie [Tue, 27 Jan 2015 03:39:51 +0000 (13:39 +1000)]
r600g: add support for primitive id without geom shader (v2)

GLSL 1.50 specifies a fragment shader may have a primitive id
input without a geometry shader present.

On r600 hw there is a special GS scenario for this, you have
to enable GS_SCENARIO_A and pass the primitive id through
the vertex shader which operates in GS_A mode.

This is a first pass attempt at this, and passes the piglit
tests that test for this.

v1.1: clean up debug print + no need to assign
key value to setup output.
v2: add r600 support

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
9 years agor600g: move selecting the pixel shader earlier.
Dave Airlie [Tue, 27 Jan 2015 03:34:50 +0000 (13:34 +1000)]
r600g: move selecting the pixel shader earlier.

In order to detect that a pixel shader has a prim id
input when we have no geometry shader we need to reorder
the shader selection so the pixel shader is selected
first, then the vertex shader key can take into account
the primitive id input requirement and lack of geom shader.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
9 years agost/clover: Pass target instead of target.begin() to std::string()
Michel Dänzer [Thu, 22 Jan 2015 03:30:24 +0000 (12:30 +0900)]
st/clover: Pass target instead of target.begin() to std::string()

Fixes reading beyond allocated memory:

==1936== Invalid read of size 1
==1936==    at 0x4C2C1B4: strlen (vg_replace_strmem.c:412)
==1936==    by 0x9E00C30: std::basic_string<char, std::char_traits<char>, std::allocator<char> >::basic_string(char const*, std::allocator<char> const&) (in /usr/lib/x86_64-linux-gnu/libstdc++.so.6.0.20)
==1936==    by 0x5B44FAE: clover::compile_program_llvm(clover::compat::string const&, clover::compat::vector<clover::compat::pair<clover::compat::string, clover::compat::string> > const&, pipe_shader_ir, clover::compat::string const&, clover::compat::string const&, clover::compat::string&) (invocation.cpp:698)
==1936==    by 0x5B39A20: clover::program::build(clover::ref_vector<clover::device> const&, char const*, clover::compat::vector<clover::compat::pair<clover::compat::string, clover::compat::string> > const&) (program.cpp:63)
==1936==    by 0x5B20152: clBuildProgram (program.cpp:182)
==1936==    by 0x400F41: main (hello_world.c:109)
==1936==  Address 0x56fee1f is 0 bytes after a block of size 15 alloc'd
==1936==    at 0x4C28C20: malloc (vg_replace_malloc.c:296)
==1936==    by 0x5B398F0: alloc (compat.hpp:59)
==1936==    by 0x5B398F0: vector<std::basic_string<char> > (compat.hpp:98)
==1936==    by 0x5B398F0: string<std::basic_string<char> > (compat.hpp:327)
==1936==    by 0x5B398F0: clover::program::build(clover::ref_vector<clover::device> const&, char const*, clover::compat::vector<clover::compat::pair<clover::compat::string, clover::compat::string> > const&) (program.cpp:63)
==1936==    by 0x5B20152: clBuildProgram (program.cpp:182)
==1936==    by 0x400F41: main (hello_world.c:109)

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
9 years agor600g,radeonsi: Fix calculation of IR target cap string buffer size
Michel Dänzer [Thu, 22 Jan 2015 03:36:13 +0000 (12:36 +0900)]
r600g,radeonsi: Fix calculation of IR target cap string buffer size

Fixes writing beyond the allocated buffer:

==31855== Invalid write of size 1
==31855==    at 0x50AB2A9: vsprintf (iovsprintf.c:43)
==31855==    by 0x508F6F6: sprintf (sprintf.c:32)
==31855==    by 0xB59C7EC: r600_get_compute_param (r600_pipe_common.c:526)
==31855==    by 0x5B2B7DE: get_compute_param<char> (device.cpp:37)
==31855==    by 0x5B2B7DE: clover::device::ir_target() const (device.cpp:201)
==31855==    by 0x5B398E0: clover::program::build(clover::ref_vector<clover::device> const&, char const*, clover::compat::vector<clover::compat::pair<clover::compat::string, clover::compat::string> > const&) (program.cpp:63)
==31855==    by 0x5B20152: clBuildProgram (program.cpp:182)
==31855==    by 0x400F41: main (hello_world.c:109)
==31855==  Address 0x56fed5f is 0 bytes after a block of size 15 alloc'd
==31855==    at 0x4C29180: operator new(unsigned long) (vg_replace_malloc.c:324)
==31855==    by 0x5B2B7C2: allocate (new_allocator.h:104)
==31855==    by 0x5B2B7C2: allocate (alloc_traits.h:357)
==31855==    by 0x5B2B7C2: _M_allocate (stl_vector.h:170)
==31855==    by 0x5B2B7C2: _M_create_storage (stl_vector.h:185)
==31855==    by 0x5B2B7C2: _Vector_base (stl_vector.h:136)
==31855==    by 0x5B2B7C2: vector (stl_vector.h:278)
==31855==    by 0x5B2B7C2: get_compute_param<char> (device.cpp:35)
==31855==    by 0x5B2B7C2: clover::device::ir_target() const (device.cpp:201)
==31855==    by 0x5B398E0: clover::program::build(clover::ref_vector<clover::device> const&, char const*, clover::compat::vector<clover::compat::pair<clover::compat::string, clover::compat::string> > const&) (program.cpp:63)
==31855==    by 0x5B20152: clBuildProgram (program.cpp:182)
==31855==    by 0x400F41: main (hello_world.c:109)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
9 years agonir: fix a bug with constant folding non-per-component instructions
Connor Abbott [Sun, 25 Jan 2015 16:47:53 +0000 (11:47 -0500)]
nir: fix a bug with constant folding non-per-component instructions

Before, we were only copying the first N channels, where N is the size
of the SSA destination, which is fine for per-component instructions,
but non-per-component instructions like fdot3 can have more source
components than destination components. Fix this using the helper
function introduced in the last patch.

v2: use new helper name

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
9 years agonir: add a helper function for getting the number of source components
Connor Abbott [Sun, 25 Jan 2015 16:42:34 +0000 (11:42 -0500)]
nir: add a helper function for getting the number of source components

Unlike with non-SSA ALU instructions, where if they're per-component
you have to look at the writemask to know which source channels are
being used, SSA ALU instructions always have all the possible channels
enabled so we can just look at the number of components in the SSA
definition for per-component instructions to say how many source
components are being used.

v2: use new name nir_ssa_alu_instr_src_components()

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
9 years agoi965: Implemente a tiled fast-path for glReadPixels and glGetTexImage
Sisinty Sasmita Patra [Fri, 12 Dec 2014 21:03:21 +0000 (13:03 -0800)]
i965: Implemente a tiled fast-path for glReadPixels and glGetTexImage

Added intel_readpixels_tiled_mempcpy and intel_gettexsubimage_tiled_mempcpy
functions. These are the fast paths for glReadPixels and glGetTexImage.

On chrome, using the RoboHornet 2D Canvas toDataURL test, this patch cuts
amount of time spent in glReadPixels by more than half and reduces the time
of the entire test by 10%.

v2: Jason Ekstrand <jason.ekstrand@intel.com>
   - Refactor to make the functions look more like the old
     intel_tex_subimage_tiled_memcpy
   - Don't export the readpixels_tiled_memcpy function
   - Fix some pointer arithmatic bugs in partial image downloads (using
     ReadPixels with a non-zero x or y offset)
   - Fix a bug when ReadPixels is performed on an FBO wrapping a texture
     miplevel other than zero.

v3: Jason Ekstrand <jason.ekstrand@intel.com>
   - Better documentation fot the *_tiled_memcpy functions
   - Add target restrictions for renderbuffers wrapping textures

v4: Jason Ekstrand <jason.ekstrand@intel.com>
   - Only check the return value of brw_bo_map for error and not bo->virtual

v5: Jason Ekstrand <jason.ekstrand@intel.com>
   - Don't unnecessarily repeat a comment

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
9 years agoi965/tiled_memcpy: Add tiled-to-linear paths
Sisinty Sasmita Patra [Sat, 3 Jan 2015 19:16:08 +0000 (11:16 -0800)]
i965/tiled_memcpy: Add tiled-to-linear paths

This commit addes tiled copy functions for coping from tiled memory to
linear memory.  These are very similar to the existing linear-to-tiled
paths.

v2: Jason Ekstrand <jason.ekstrand@intel.com>
   - New commit message
   - Various whitespace fixes
   - Added ptrdiff_t casts as done in commit 225a09790

v3: Jason Ekstrand <jason.ekstrand@intel.com>
   - Fixed a comment

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
9 years agoi965: Refactor tiled memcpy functions and move them into their own file
Sisinty Sasmita Patra [Fri, 12 Dec 2014 19:28:05 +0000 (11:28 -0800)]
i965: Refactor tiled memcpy functions and move them into their own file

This commit refactors the tiled_memcpy code in intel_tex_subimage.c and
moves it into its own file intel_tiled_memcpy files.  Also, xtile_copy and
ytile_copy are renamed to linear_to_xtiled and linear_to_ytiled
respectively.  The *_faster functions are similarly renamed.

There was also a bit of logic to select between the the libc provided
memcpy function and our custom memcpy that does an RGBA -> BGRA swizzle.
This was moved into an intel_get_memcpy function so that rgba8_copy can
live (and be inlined) in intel_tiled_memcpy.c.

v2: Jason Ekstrand <jason.ekstrand@intel.com>
   - Better commit message
   - Fix up the copyright on the intel_tiled_memcpy files
   - Various whitespace fixes
   - Moved a bunch of stuff that did not need to be exposed from
     intel_tiled_memcpy.h to intel_tiled_memcpy.c
   - Added proper documentation for intel_get_memcpy
   - Incorperated the ptrdiff_t tweaks from commit 225a09790

v3: Jason Ekstrand <jason.ekstrand@intel.com>
   - Fixed a comment
   - Move the tile size constants into the .c file

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
9 years agoi965/tex_subimage: Use the fast tiled path for rectangle textures
Jason Ekstrand [Sat, 3 Jan 2015 02:22:04 +0000 (18:22 -0800)]
i965/tex_subimage: Use the fast tiled path for rectangle textures

There's no reason why we should be doing this for 2D textures and not
rectangles.  Just a matter of adding another hunk to the condition.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
9 years agomesa/autoconf: attempt to use gnu99 on older gcc compilers
Dave Airlie [Wed, 21 Jan 2015 06:40:26 +0000 (16:40 +1000)]
mesa/autoconf: attempt to use gnu99 on older gcc compilers

anonymous structs/union don't work with c99 but do work with gnu99
on gcc 4.4.

Signed-off-by: Dave Airlie <airlied@redhat.com>
9 years agomesa: simplify detection of fpclassify
Felix Janda [Fri, 23 Jan 2015 16:57:15 +0000 (17:57 +0100)]
mesa: simplify detection of fpclassify

Fixes compilation with musl libc.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
9 years agonir/opcodes: Don't go through doubles when constant-folding iabs
Jason Ekstrand [Mon, 26 Jan 2015 17:40:25 +0000 (09:40 -0800)]
nir/opcodes: Don't go through doubles when constant-folding iabs

Previously, we called the abs() function in math.h.  However, this involves
unnecessarily going through double.  This commit changes it to use integers
directly with a ternary.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agonir/opcodes: Simplify and fix the unpack_half_*_split_* constant expressions
Jason Ekstrand [Mon, 26 Jan 2015 17:36:58 +0000 (09:36 -0800)]
nir/opcodes: Simplify and fix the unpack_half_*_split_* constant expressions

Previously, these functions were explicitly writing to dst.x and dst.y.
However they both return only one component so writing to dst.y is invalid.
Also, since they only return one component, we don't need the explicit
assignment in the expression and can simplify it use an implicit
assignment.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
9 years agonir: Use pointers for nir_src_copy and nir_dest_copy
Jason Ekstrand [Sat, 24 Jan 2015 00:57:40 +0000 (16:57 -0800)]
nir: Use pointers for nir_src_copy and nir_dest_copy

This avoids the overhead of copying structures and better matches the newly
added nir_alu_src_copy and nir_alu_dest_copy.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
9 years agoi965: Handle CMP.nz ... 0 and MOV.nz similarly in cmod propagation.
Kenneth Graunke [Sat, 24 Jan 2015 12:16:54 +0000 (04:16 -0800)]
i965: Handle CMP.nz ... 0 and MOV.nz similarly in cmod propagation.

"MOV.nz null src" and "CMP.nz null src 0" are equivalent instructions.

Previously, we deleted MOV.nz instructions when the instruction
generating the MOV's source also wrote the flag register (as the flag
register already contains the desired value).  However, we wouldn't
delete CMP.nz instructions that served the same purpose.

We also didn't attempt true cmod propagation on MOV.nz instructions,
while we would for the equivalent CMP.nz form.

This patch fixes both limitations, treating both forms equally.
CMP.nz instructions will now be deleted (helping the NIR backend),
and MOV.nz instructions will have their .nz propagated.

No changes in shader-db without NIR.  With NIR,

total instructions in shared programs: 6006153 -> 5969364 (-0.61%)
instructions in affected programs:     2087139 -> 2050350 (-1.76%)
helped:                                10704
HURT:                                  0
GAINED:                                2
LOST:                                  2

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoclover: Fix build with llvm after r226981
Jan Vesely [Sun, 25 Jan 2015 21:11:40 +0000 (16:11 -0500)]
clover: Fix build with llvm after r226981

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88783
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
9 years agoconfigure: Link against all LLVM targets when building clover
Niels Ole Salscheider [Sat, 24 Jan 2015 21:49:44 +0000 (22:49 +0100)]
configure: Link against all LLVM targets when building clover

Since 8e7df519bd8556591794b2de08a833a67e34d526, we initialise all targets in
clover. This fixes bug 85380.

v2: Mention correct bug in commit message

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Cc: "10.4" <mesa-stable@lists.freedesktop.org>
9 years agonir/constant_folding: use the new constant folding infrastructure
Connor Abbott [Fri, 23 Jan 2015 04:32:16 +0000 (23:32 -0500)]
nir/constant_folding: use the new constant folding infrastructure

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: add new constant folding infrastructure
Jason Ekstrand [Fri, 23 Jan 2015 21:38:46 +0000 (13:38 -0800)]
nir: add new constant folding infrastructure

Add a required field to the Opcode class, const_expr, that contains an
expression or statement that computes the result of the opcode given known
constant inputs. Then take those const_expr's and expand them into a function
that takes an opcode and an array of constant inputs and spits out the constant
result. This means that when adding opcodes, there's one less place to update,
and almost all the opcodes are self-documenting since the information on how to
compute the result is right next to the definition.

The helper functions in nir_constant_expressions.c were taken from
ir_constant_expressions.cpp.

v3 Jason Ekstrand <jason.ekstrand@iastate.edu>
 - Use mako to generate one function per opcode instead of doing piles of
   string splicing

v4 Jason Ekstrand <jason.ekstrand@iastate.edu>
 - More comments and better indentation in the mako
 - Add a description of the constant expression language in nir_opcodes.py
 - Added nir_constant_expressions.py to EXTRA_DIST in Makefile.am

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
9 years agonir: use Python to autogenerate opcode information
Connor Abbott [Fri, 23 Jan 2015 04:32:14 +0000 (23:32 -0500)]
nir: use Python to autogenerate opcode information

Before, we used a system where a file, nir_opcodes.h, defined some macros that
were included to generate the enum values and the nir_op_infos structure. This
worked pretty well, but for development the error messages were never very
useful, Python tools couldn't understand the opcode list, and it was difficult
to use nir_opcodes.h to do other things like autogenerate a builder API. Now, we
store opcode information in nir_opcodes.py, and we have nir_opcodes_c.py to
generate the old nir_opcodes.c and nir_opcodes_h.py to generate nir_opcodes.h,
which contains all the enum names and gets included into nir.h like before.  In
addition to solving the above problems, using Python and Mako to generate
everything means that it's much easier to add keep information centralized as we
add new things like constant propagation that require per-opcode information.

v2:
 - make Opcode derive from object (Dylan)
 - don't use assert like it's a function (Dylan)
 - style fixes for fnoise, use xrange (Dylan)
 - use iterkeys() in nir_opcodes_h.py (Dylan)
 - use pydoc-style comments (Jason)
 - don't make fmin/fmax commutative and associative yet (Jason)

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
v3 Jason Ekstrand <jason.ekstrand@intel.com>
 - Alphabetize source file lists
 - Generate nir_opcodes.h in the builddir instead of the source dir
 - Include $(builddir)/src/glsl/nir in the i965 build
 - Rework nir_opcodes.h generation so it generates a complete header file
   instead of one that has to be embedded inside an enum declaration

9 years agodocs: add news item and link release notes for mesa 10.4.3
Emil Velikov [Sat, 24 Jan 2015 13:18:10 +0000 (13:18 +0000)]
docs: add news item and link release notes for mesa 10.4.3

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
9 years agodocs: Add sha256 sums for the 10.4.3 release
Emil Velikov [Sat, 24 Jan 2015 12:54:33 +0000 (12:54 +0000)]
docs: Add sha256 sums for the 10.4.3 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 49a5bce7801651574d3f4841d7532d8b2b86af63)

9 years agoAdd release notes for the 10.4.3 release
Emil Velikov [Sat, 24 Jan 2015 12:49:17 +0000 (12:49 +0000)]
Add release notes for the 10.4.3 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit e92bfa3f9512832b61706b76b5c9f7afa78199b0)

9 years agoi965: Convert CMP.GE -(abs)reg 0 -> CMP.Z reg 0.
Matt Turner [Mon, 5 Jan 2015 21:51:03 +0000 (13:51 -0800)]
i965: Convert CMP.GE -(abs)reg 0 -> CMP.Z reg 0.

total instructions in shared programs: 5952059 -> 5951603 (-0.01%)
instructions in affected programs:     138812 -> 138356 (-0.33%)
GAINED:                                1
LOST:                                  0

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Add support for removing MOV.NZ instructions.
Matt Turner [Wed, 31 Dec 2014 01:19:41 +0000 (17:19 -0800)]
i965/fs: Add support for removing MOV.NZ instructions.

For some reason, we occasionally write the flag register with a MOV.NZ
instruction:

   add(8)          g25<1>F         -g6<0,1,0>F     g15<8,8,1>F
   cmp.l.f0(8)     g26<1>D         g25<8,8,1>F     0F
   mov.nz.f0(8)    null            g26<8,8,1>D

A MOV.NZ instruction on the result of a CMP is like comparing for
equality with true in C. It's useless. Removing it allows us to
generate:

   add.l.f0(8)     null            -g6<0,1,0>F     g15<8,8,1>F

total instructions in shared programs: 5955701 -> 5951657 (-0.07%)
instructions in affected programs:     302910 -> 298866 (-1.34%)
GAINED:                                1
LOST:                                  0

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Allow flipping cond mod for negated arguments.
Matt Turner [Tue, 30 Dec 2014 20:18:57 +0000 (12:18 -0800)]
i965/fs: Allow flipping cond mod for negated arguments.

This allows us to apply the optimization in cases where the CMP's
argument is negated, by flipping the conditional mod. For example, it
allows us to optimize this:

   add(8)       temp   a      b
   cmp.l.f0(8)  null   -temp  0.0

into

   add.g.f0(8)  temp   a      b

total instructions in shared programs: 5958360 -> 5955701 (-0.04%)
instructions in affected programs:     466880 -> 464221 (-0.57%)
GAINED:                                0
LOST:                                  1

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Propagate cmod across flag read if it contains the same value.
Matt Turner [Sat, 3 Jan 2015 20:18:15 +0000 (12:18 -0800)]
i965/fs: Propagate cmod across flag read if it contains the same value.

total instructions in shared programs: 5959463 -> 5958900 (-0.01%)
instructions in affected programs:     70031 -> 69468 (-0.80%)

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Add unit tests for cmod propagation pass.
Matt Turner [Thu, 6 Nov 2014 00:13:59 +0000 (16:13 -0800)]
i965/fs: Add unit tests for cmod propagation pass.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Add pass to propagate conditional modifiers.
Matt Turner [Fri, 22 Aug 2014 17:54:43 +0000 (10:54 -0700)]
i965/fs: Add pass to propagate conditional modifiers.

total instructions in shared programs: 5974160 -> 5959463 (-0.25%)
instructions in affected programs:     1743737 -> 1729040 (-0.84%)
GAINED:                                0
LOST:                                  12

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Eliminate null-dst instructions without side-effects.
Matt Turner [Fri, 22 Aug 2014 18:01:13 +0000 (11:01 -0700)]
i965/fs: Eliminate null-dst instructions without side-effects.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Apply conditional mod specially to split MAD/LRP.
Matt Turner [Tue, 30 Dec 2014 20:56:13 +0000 (12:56 -0800)]
i965/fs: Apply conditional mod specially to split MAD/LRP.

Otherwise we'll apply the conditional mod to only one of SIMD8
instructions and trigger an assertion.

NoDDClr/NoDDChk have the same problem but we never apply those to these
instructions, so I'm leaving them for a later time.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Add a pass to fixup 3-src instructions that have a null dest.
Matt Turner [Tue, 30 Dec 2014 04:33:12 +0000 (20:33 -0800)]
i965/fs: Add a pass to fixup 3-src instructions that have a null dest.

3-src instructions can only have GRF/MRF destinations. It's really
difficult to deal with that restriction in dead code elimination (that
wants to give instructions null destinations to show that their result
isn't used) while allowing 3-src instructions to have conditional mod,
so don't, and just give then a destination before register allocation.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Add is_3src() to backend_instruction.
Matt Turner [Tue, 30 Dec 2014 03:29:21 +0000 (19:29 -0800)]
i965: Add is_3src() to backend_instruction.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Add backend_instruction::can_do_cmod().
Matt Turner [Sun, 24 Aug 2014 21:01:48 +0000 (14:01 -0700)]
i965: Add backend_instruction::can_do_cmod().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/cfg: Add a foreach_block_reverse macro.
Matt Turner [Wed, 31 Dec 2014 03:54:50 +0000 (19:54 -0800)]
i965/cfg: Add a foreach_block_reverse macro.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/cfg: Add a foreach_inst_in_block_reverse_safe macro.
Matt Turner [Wed, 31 Dec 2014 00:14:43 +0000 (16:14 -0800)]
i965/cfg: Add a foreach_inst_in_block_reverse_safe macro.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoglsl: Add a foreach_in_list_reverse_safe macro.
Matt Turner [Wed, 31 Dec 2014 00:14:25 +0000 (16:14 -0800)]
glsl: Add a foreach_in_list_reverse_safe macro.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Don't make instructions with a null dest a barrier to scheduling.
Matt Turner [Wed, 9 Apr 2014 20:38:14 +0000 (13:38 -0700)]
i965: Don't make instructions with a null dest a barrier to scheduling.

Now that we properly track accumulator dependencies, the scheduler is
able to schedule instructions between the mach and mov in the common
the integer multiplication pattern:

   mul  acc0, x, y
   mach null, x, y
   mov  dest, acc0

Since a null destination implies no dependency on the destination, we
can also safely schedule instructions (that don't write the accumulator)
between the mul and mach.

GAINED:                                103
LOST:                                  43

Causes one program to spill (643 -> 1076 instructions).

I committed this patch last year (commit 42a26cb5) but reverted it
(commit 0d3f83f4) after inexplicable artifacts in Kerbal Space Program
(bug 78648). Tapani reapplied this patch and could not reproduce the bug
with current Mesa.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Allow SIMD16 on pre-SNB when try_replace_with_sel is successful
Ian Romanick [Fri, 23 Jan 2015 20:31:05 +0000 (12:31 -0800)]
i965/fs: Allow SIMD16 on pre-SNB when try_replace_with_sel is successful

If try_replace_with_sel is able to replace the flow control with a SEL
instruction, then there is no flow control... failing SIMD16 because
of nonexistent flow control is wrong.

No piglit regressions on any i965 platform in Jenkins.

total instructions in shared programs: 4382707 -> 4382707 (0.00%)
instructions in affected programs:     0 -> 0
helped:                                0
HURT:                                  0
GAINED:                                2089
LOST:                                  0

No other platforms affected in shader-db.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agonir: Expose nir_print_instr() for debug prints
Eric Anholt [Wed, 5 Nov 2014 23:10:37 +0000 (15:10 -0800)]
nir: Expose nir_print_instr() for debug prints

It's nice to have this present in your default cases so you can see what
instruction is triggering an abort.

v2: Just pass a NULL state, now that it won't crash when you do.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: When asked to print with a NULL state, just use bare variable names.
Eric Anholt [Fri, 23 Jan 2015 22:47:50 +0000 (14:47 -0800)]
nir: When asked to print with a NULL state, just use bare variable names.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Add nir_lower_alu_to_scalar.
Eric Anholt [Thu, 13 Nov 2014 20:40:59 +0000 (12:40 -0800)]
nir: Add nir_lower_alu_to_scalar.

This is the equivalent of brw_fs_channel_expressions.cpp, which I wanted
for vc4.

v2: Use the nir_src_for_ssa() helper, and another instance of
    nir_alu_src_copy().
v3: Drop the non-SSA support.  All intended callers will have SSA-only ALU
    ops.
v4: Use insert_before, drop stale bcsel/fcsel comment, drop now-unused
    unsupported() function, drop lower_context struct.
v5: Completely rename the pass to nir_lower_alu_to_scalar(), add an assert
    about weird input_sizes[].

Reviewed-by: Jason Ekstrand <jason.ekstrand@iastate.edu>
9 years agonir: Make some helpers for copying ALU src/dests.
Eric Anholt [Wed, 21 Jan 2015 23:55:23 +0000 (15:55 -0800)]
nir: Make some helpers for copying ALU src/dests.

There aren't many users yet, but I wanted to do this from my scalarizing
pass.

v2: Constify the src arguments.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Add algebraic optimizations for division and reciprocal.
Kenneth Graunke [Thu, 22 Jan 2015 07:52:17 +0000 (23:52 -0800)]
nir: Add algebraic optimizations for division and reciprocal.

These also exist in opt_algebraic.cpp.

total NIR instructions in shared programs: 2011430 -> 2011211 (-0.01%)
NIR instructions in affected programs:     42221 -> 42002 (-0.52%)
helped:                                    198

total i965 instructions in shared programs: 6020553 -> 6020116 (-0.01%)
i965 instructions in affected programs:     84322 -> 83885 (-0.52%)
helped:                                     394
HURT:                                       1 (by 1 instruction)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agonir: Add algebraic optimizations for exponential/logarithmic functions.
Kenneth Graunke [Thu, 22 Jan 2015 07:47:06 +0000 (23:47 -0800)]
nir: Add algebraic optimizations for exponential/logarithmic functions.

Most of these exist in the GLSL IR algebraic pass already.  However,
SSA allows us to find more instances of the patterns.

total NIR instructions in shared programs: 2015593 -> 2011430 (-0.21%)
NIR instructions in affected programs:     124189 -> 120026 (-3.35%)
helped:                                    604

total i965 instructions in shared programs: 6025505 -> 6018717 (-0.11%)
i965 instructions in affected programs:     261295 -> 254507 (-2.60%)
helped:                                     1295
HURT:                                       3

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agonir: Add algebraic optimizations for simplifying comparisons.
Kenneth Graunke [Thu, 22 Jan 2015 07:36:01 +0000 (23:36 -0800)]
nir: Add algebraic optimizations for simplifying comparisons.

The first batch removes bonus fnot/inot operations, possibly allowing
other optimizations to better recognize patterns.

The next batch replaces a fadd and constant 0.0 with an fneg - negation
is usually free on GPUs, while addition is not.

total NIR instructions in shared programs: 2020814 -> 2015593 (-0.26%)
NIR instructions in affected programs:     411143 -> 405922 (-1.27%)
helped:                                    2233
HURT:                                      214

A few shaders are hurt by a few instructions due to moving neg such
that it has a constant operand, which is then folded, resulting in two
distinct load_consts for x and -x.  We can always clean that up later.

total i965 instructions in shared programs: 6035392 -> 6025505 (-0.16%)
i965 instructions in affected programs:     784980 -> 775093 (-1.26%)
helped:                                     4508
HURT:                                       2

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agonir: Add algebraic optimizations for pointless shifts.
Kenneth Graunke [Thu, 22 Jan 2015 07:25:56 +0000 (23:25 -0800)]
nir: Add algebraic optimizations for pointless shifts.

The GLSL IR optimization pass contained these; we may as well include
them too.

v2: Fix a >> 0 and a << 0 optimizations (caught by Matt).

No change in the number of NIR instructions on a shader-db run.

total i965 instructions in shared programs: 6035397 -> 6035392 (-0.00%)
i965 instructions in affected programs:     542 -> 537 (-0.92%)
helped:                                     2 (in glamor)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agonir: Add a bunch of algebraic optimizations on logic/bit operations.
Kenneth Graunke [Mon, 19 Jan 2015 22:57:38 +0000 (14:57 -0800)]
nir: Add a bunch of algebraic optimizations on logic/bit operations.

Matt and I noticed a bunch of "val <- ior a a" operations in a shader,
so we decided to add an algebraic optimization for that.  While there,
I decided to add a bunch more of them.

v2: Delete bogus fand/for optimizations (caught by Jason).

total NIR instructions in shared programs: 2023511 -> 2020814 (-0.13%)
NIR instructions in affected programs:     149634 -> 146937 (-1.80%)
helped:                                    1032

total i965 instructions in shared programs: 6035392 -> 6035397 (0.00%)
i965 instructions in affected programs:     537 -> 542 (0.93%)
HURT:                                       2

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agonir: Implement CSE on intrinsics that can be eliminated and reordered.
Kenneth Graunke [Mon, 19 Jan 2015 22:51:24 +0000 (14:51 -0800)]
nir: Implement CSE on intrinsics that can be eliminated and reordered.

Matt and I noticed that one of the shaders hurt by INTEL_USE_NIR=1 had
load_input and load_uniform intrinsics repeated several times, with the
same parameters, but each one generating a distinct SSA value.  This
made ALU operations on those values appear distinct as well.

Generating distinct SSA values is silly - these are read only variables.
CSE'ing them makes everything use a single SSA value, which then allows
other operations to be CSE'd away as well.

Generalizing a bit, it seems like we should be able to safely CSE any
intrinsics that can be eliminated and reordered.  I didn't implement
support for variables for the time being.

v2: Assert that info->num_variables == 0 (requested by Jason).

total NIR instructions in shared programs: 2435936 -> 2023511 (-16.93%)
NIR instructions in affected programs:     2413496 -> 2001071 (-17.09%)
helped:                                    16872

total i965 instructions in shared programs: 6028987 -> 6008427 (-0.34%)
i965 instructions in affected programs:     640654 -> 620094 (-3.21%)
helped:                                     2071
HURT:                                       585
GAINED:                                     14
LOST:                                       25

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Pull nir_instr_can_cse()'s SSA checks out of the switch.
Kenneth Graunke [Wed, 21 Jan 2015 20:20:59 +0000 (12:20 -0800)]
nir: Pull nir_instr_can_cse()'s SSA checks out of the switch.

This should not be a change in behavior, as all current cases that
potentially answer "yes" require SSA.

The next patch will introduce another case that requires SSA.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/nir: Report NIR instruction counts (in SSA form) via KHR_debug.
Kenneth Graunke [Wed, 21 Jan 2015 09:51:21 +0000 (01:51 -0800)]
i965/nir: Report NIR instruction counts (in SSA form) via KHR_debug.

This allows us to count NIR instructions via shader-db.

Use "run" as normal.  The results file will contain both NIR and
assembly.

Then, to generate a NIR report:
./report.py <(grep    NIR results/foo) <(grep    NIR results/bar)

Or, to generate an i965 report:
./report.py <(grep -v NIR results/foo) <(grep -v NIR results/bar)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/nir: Print NIR on INTEL_DEBUG=fs.
Kenneth Graunke [Tue, 20 Jan 2015 07:11:54 +0000 (23:11 -0800)]
i965/nir: Print NIR on INTEL_DEBUG=fs.

This is useful for debugging and looking for optimization opportunities.

It will need to be expanded when we add support for other scalar stages.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/nir: Do optimizations again just before lowering source mods.
Kenneth Graunke [Tue, 20 Jan 2015 06:11:39 +0000 (22:11 -0800)]
i965/nir: Do optimizations again just before lowering source mods.

We want to run CSE and algebraic optimizations again after lowering IO.
Some of the passes in the optimization loop don't handle saturates and
other modifiers, so run it before lowering to source modifiers.

total instructions in shared programs: 6046190 -> 6045768 (-0.01%)
instructions in affected programs:     22406 -> 21984 (-1.88%)
helped:                                47
HURT:                                  0
GAINED:                                0
LOST:                                  0

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoloader: Remove NEED_OPENGL_COMMON check.
Matt Turner [Thu, 18 Dec 2014 22:10:17 +0000 (14:10 -0800)]
loader: Remove NEED_OPENGL_COMMON check.

HAVE_DRICOMMON is sufficient since OpenGL must be enabled for DRI.

9 years agogitignore: Ignore .tar.xz files.
Matt Turner [Thu, 18 Dec 2014 21:35:47 +0000 (13:35 -0800)]
gitignore: Ignore .tar.xz files.

9 years agomesa: Build with subdir-objects.
Matt Turner [Thu, 18 Dec 2014 19:44:07 +0000 (11:44 -0800)]
mesa: Build with subdir-objects.

9 years agoglsl: Build a libglsl_util library.
Matt Turner [Thu, 18 Dec 2014 21:33:29 +0000 (13:33 -0800)]
glsl: Build a libglsl_util library.

Rather than sourcing files with ../dir/file.c which leads to distclean
wiping out ../dir's .deps directory.

9 years agomapi: Build with subdir-objects.
Matt Turner [Thu, 18 Dec 2014 02:50:25 +0000 (18:50 -0800)]
mapi: Build with subdir-objects.

9 years agomapi: Remove vgapi from SUBDIRS.
Matt Turner [Thu, 18 Dec 2014 04:28:19 +0000 (20:28 -0800)]
mapi: Remove vgapi from SUBDIRS.

OpenVG is disabled with via autotools.

9 years agomesa: Drop inclusion of glapi_gen.mk.
Matt Turner [Thu, 18 Dec 2014 03:46:22 +0000 (19:46 -0800)]
mesa: Drop inclusion of glapi_gen.mk.

Some glapi headers used to be generated from this Makefile.am, but no
longer.

9 years agoglsl: Build with subdir-objects.
Matt Turner [Mon, 8 Dec 2014 00:09:35 +0000 (16:09 -0800)]
glsl: Build with subdir-objects.

Apparently $(top_srcdir) is not expanded in a source list when using
subdir-objects, so remove that. It's not clear to me why we were going
to such lengths to prefix each source file anyway.

9 years agonir: Add headers to distribution.
Matt Turner [Fri, 23 Jan 2015 22:27:39 +0000 (14:27 -0800)]
nir: Add headers to distribution.

9 years agonir: Add nir_{opt_,}algebraic.py to distribution.
Matt Turner [Fri, 23 Jan 2015 22:25:46 +0000 (14:25 -0800)]
nir: Add nir_{opt_,}algebraic.py to distribution.

9 years agomesa: Add format_{un,}pack.py to distribution.
Matt Turner [Fri, 23 Jan 2015 22:25:10 +0000 (14:25 -0800)]
mesa: Add format_{un,}pack.py to distribution.

9 years agomesa: Remove pack_tmp.h from sources.
Matt Turner [Fri, 23 Jan 2015 21:35:25 +0000 (13:35 -0800)]
mesa: Remove pack_tmp.h from sources.

Missed in commit 3a4de321.

9 years agonir: add generated file to .gitignore
Connor Abbott [Fri, 23 Jan 2015 04:32:13 +0000 (23:32 -0500)]
nir: add generated file to .gitignore

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965: Fix min_vs_entries for CHV
Ville Syrjälä [Mon, 19 Jan 2015 14:09:10 +0000 (16:09 +0200)]
i965: Fix min_vs_entries for CHV

According to BSpec the correct number for min_vs_entries is 34 for CHV.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>