misc: Revert version info for develop branch

Change-Id: Ie01f41cb40b025ef31028bff4d59023e380fcf07
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40536
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

Merge "misc: Merge branch v20.1.0.3 hotfix into develop" into develop

fastmodel: fix cntfrq in A76

Change-Id: I7d1167e8b61d6768039c34fe1ee54560f7845dfa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40355
Reviewed-by: Ahbong Chang <cwahbong@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Implementation of s_sleep

This changeset implements the s_sleep instruction in a similar
way to s_waitcnt.

Change-Id: I4811c318ac2c76c485e2bfd9d93baa1205ecf183
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39115
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Make JRCXZ instruction do 64-bit jump

Per the AMD64 Architecture Programming Manual:

The size of the count register (CX, ECX, or RCX) depends on the
address-size attribute of the JrCXZ instruction. Therefore, JRCXZ can
only be executed in 64-bit mode

and

In 64-bit mode, the operand size defaults to 64 bits. The processor
sign-extends the 8-bit displacement value to 64 bits before adding it
to the RIP.

This patch also renames the instruction from JRCX to JRCXZ to match the
language in the programming manual.

Change-Id: Id55147d0602ff41ad6aaef483bef722ff56cae62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40195
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Changed 'long' boot tests to X86 from GCN3_X86

We compile GCN3_X86 for the 'quick' tests, as a substitute for X86. We
compile X86 as part of our nightly tests, along with the running of the
'long' tests. This leads to a needless duplicate compilation of the X86
isa during our nightly tests. Therefore, this commit removes GCN3_X86
for the 'long' tests (only the x86 boot tests are affected).

Change-Id: Ifd8aaf0e7b8178c588ace33b27671d4ba9b353ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40415
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Merge branch v20.1.0.3 hotfix into develop

Change-Id: I12cca586627718bf41fe24f0fcd3f10c4fe48b2d

scons,python: Fix `--without-python` flag

Even with the `--without-python` flag, checks were still done to ensure
the correct version of Python was being used. This commit fixes this so
these checks are not performed when `--without-python` is enabled.

Change-Id: I2242f2971a49ef28cff229ad0337bce0a998413d
Issue-on: https://gem5.atlassian.net/browse/GEM5-880
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39715
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Lukas Steiner <lsteiner@rhrk.uni-kl.de>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updated the RELEASE-NOTES and version number

Updated the RELEASE-NOTES.md and version number for the v20.1.0.3
hotfix release.

Change-Id: I95ab84ea259f5e0529ebaa32be65d9a14370f219
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40435
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute,misc: Remove unused private variable

Clang 9 fails to compile GCN3 due to the unused private variable,
`_nxtFreeIdx`, in `src/gpu-compute/dyn_pool_manager.hh`. This variable
has therefore been removed.

Change-Id: I33f2e9634bbf8d5cea7a42ae2ac9f3ea8298d406
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40397
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute,misc: Fix Clang missing override errors

Clang fails to compile GCN3 due to missing overrides in
`src/gpu-compute/gpu_command_processor.hh`. This commit fixes this
errror.

Change-Id: I6da9fce7c3eb86a5418a931ee4f225cceda488a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40396
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv,misc: Fix clang missing override errors

Clang 9 failed to compile RISC-V due to missing overrides in
`src/arch/riscv/remote_gdb.hh`. This commit adds these missing
overrides.

Change-Id: Id0bfc371ca3e3e1b91e9112a837e1862072bf9d2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40395
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Increase presubmit (Kokoro) timeout to 6 hours

Kokoro is now frequnetly timing out. This will increase the timeout from
5 hours to 6 hours.

Change-Id: I2124567142358ab183d962fcbd73ee9ea4e809a3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40455
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add destRegIdxArr arrays to TME instructions

This is needed as the base StaticInst class is no longer holding the
index array and it is up to the derived class to allocate the
storage depending on the number of registers used

Change-Id: I389e39a7e09d31f370d63a6e61fe6ee3faaac7db
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40375
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Re-remove Authors lines from source files.

These were universally removed a while ago, but a bunch have crept back
in. Remove them.

Change-Id: I3cb5b9f40c9c19aafb5e39a51d1baeae60a591c0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40335
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>

scons: Add an "All" compound debug flag

Add an "All" compound debug flag, which encapsulates all
debug flags.

Since this is the broadest compound flag, allowing users
to include it would imply in extremely generic includes.
Moreover, it is highly unlikely that any correct C++ code
would ever use all debug flags. Therefore, a header file
for this flag is not generated to force users to directly
include only the debug flags they need.

Change-Id: If40f2f708be1495fa2b2380266164d5d44d7cffa
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39077
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

arch-arm,cpu: Use getEMI() in more places.

Use that method to avoid reading the machInst.

Change-Id: I11434206c0b7a1aa3793aa46b5056ad60a64b01c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40100
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm,cpu: Introduce a getEMI virtual method on StaticInst.

This takes the place of direct access to the machInst field as used in
the MinorCPU model which makes the incorrect assumption that it can
arbitrarily treat the ExtMachInst as an integer, and that masking in a
certain way can meaningfully classify what the instruction will do.

Because that assumption is not correct in general, that had been
ifdef-ed out in most ISAs except ARM, and for the other ISAs the value
was simply set to zero.

Change-Id: I8ac05e65475edc3ccc044afdff09490e2c05ba07
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40098
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Templatize the BasicDecodeCache.

While the arch/generic directory is in arch/, it still shouldn't assume
any particular ISA. This change templatizes away the ISA specific types
so it can be used in multiple ISAs at a time.

Change-Id: I1abb4f5081a0a25f743be786ad8e7e3d55cfc67a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40097
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base,tests: Create unit tests for Stats::Stor

Create unit tests for the stats storage types. As a side effect
storage-related classes have been moved to separate files.

HistStor's grow_up, grow_out, and grow_convert have been made
private and renamed to comply with gem5's naming convention
and make grow_convert match its grow_up counterpart (growDown)
which is more suitable for its expected behavior.

The params declarations have been moved to be close to their
storage class' constructor.

HistStor has a explicit condition stating that there must be
at least 2 buckets.

Added documentation!

Fixed grow_convert so that it yields consistent histograms.
Previously buckets could not fully intersect, so doubling their
bucket size would make them steal contents innaproprietly. For
example, the neighbors [-6,-2[, [-2,2[, [2,6[, when doubled,
become [-12,-4[, [-4,4[, [4,12[; however, since the individual
values are not stored, it is impossible to know how to populate
the middle bucket with its neighbor's partial contents.
This fix forces the middle bucket of a storage to have its lower
bound at 0, solving the partial intersection issue.

Change-Id: Idb063e3dbda3cce3a8969e347660143162146eb9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25425
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Move Stats::Info functions to its own source file

Move information needed by Stats::Info and its derived classes
from base/statistics.cc to its own source file.

Create a SConscript in the stats sub-dir to start clustering
stats related files.

Change-Id: I1e5e828c7814748c2582755f664550241caf860e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25424
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base,tests: Add a basic fake class to handle curTick

Add this basic fake class that handles the initialization
and update of the current tick.

Change-Id: Iba8ecc049acdd097caa4d9cf05ac8d78bbaf03cc
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39836
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Move cur tick to its own files

When declared within sim/core.hh, unit tests that use the
current tick would have to unnecessarily include many other
extra files.

Change-Id: Ib4348312afb90765edb4f94c80785df1275b2004
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39835
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

scons: Separate debug flags from debug-format flags

Debug flags are flags that aid with debugging by printing
relevant information when enabled. Debug-formatting flags
define how the debug flags will print the information.

Although a viability, this patch does not support declaring
compound format flags.

As a side effect, now debug flags and debug-formatting flags
are printed in different lists, when using --debug-help.

Change-Id: Ieae68745276218cf4e9c1d37d7bf3bd1f19709ae
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39076
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,python: Add check to ensure files are utf-8 in pre-commit

The `file_from_index` function throws a UnicodeDecodeError if a modified
file targetted for style-checking (i.e. source-code) cannot be decoded
using `.decode("utf-8")`.

This check throws an error informing the user a submitted file must be
utf-8 encoded if this case arises.

Change-Id: I2361017f2e7413ed60f897d2301f2e4c7995dd76
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40015
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,python: Fix Pre-commit hooks to ignore non-source files

Previously if binary blobs were modified the pre-commit hook attempted
to run style-checks on the binary, causing an error when attempting to
decode to utf-8. This commit runs a check on each file to ensure it has
a valid source-code extension prior to running style checks. If a file
does not have a valid extension style checks are not run.

Change-Id: Id1263cac0d6c190ad1a3d67720b3f373e0e42234
Issue-on: https://gem5.atlassian.net/browse/GEM5-903
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39795
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: testlib loading tests from multiple directories

We currently run regressions with the following command line

./main.py run [...] <directory>

Where <directory> is the positional argument pointing to the tests root
directory: Testlib will walk through the directory and load every
testsuite it encounters in its path.

./main.py run [...] <directory1> <directory2> ...

Allowing testlib to load tests from multiple directories will make it
possible to load out of tree regressions (living in an EXTRAS repository
for example)

JIRA: https://gem5.atlassian.net/browse/GEM5-905

Change-Id: I802d8753a18f4dfb00347252f031b5438e9be672
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40136
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: remove boost header dependency

The current tests included don't require boost header to work. Remove
the dependency. This also gets rid of the warning message generated by
the latest boost headers.

Tested by running systemC tests:

src/systemc/tests/verify.py --update-json \
  --filter-file=src/systemc/tests/working.filt -j 56 build/ARM/

Change-Id: I9d3bfe145597335abdf24f2de85ed3c0708aea27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40315
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: don't expose FEAT_VHE by default

If FEAT_VHE is implemented and Linux boots in EL2, it programs itself
to operate in EL2. This causes a later boot stall as explained in
https://gem5.atlassian.net/browse/GEM5-901.
We provide a parameter "have_vhe" to enable FEAT_VHE on demand. This is
disabled by default until fixed. This avoids users stalling on the common
case of booting Linux without a hypervisor.

Change-Id: I3ee7be1ca59afc0cbbda59fb3aad4c897c06405f
Signed-off-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39695
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Update pybind11 to version 2.6.2.

This should help reduce warning spew when building with newer compilers.
The pybind11::module type has been renamed pybind11::module_ to avoid
conflicts with c++20 modules, according to the pybind11 changelog, so
this CL also updates gem5 source to use the new type. There is
supposedly an alias pybind11::module which is for compatibility, but we
still get linker errors without changing to pybind11::module_.

Change-Id: I0acb36215b33e3a713866baec43f5af630c356ee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40255
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: add interface to update system counter freq

This CL set the cntfrq and system counter frequency at once from python
script. This aligns the fastmodel implementation to other part of gem5
CPU.

Change-Id: I78c9a7be801112844c03d2669a94d57015136d16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40278
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: create base class for EVS CPU

Previously we use attribute and event for communication between gem5
SimObject to systemC fastmodel sc_module. Creating a base class allows us
to perform casting once and get all the interface required. Also,
instead of warning on attribute not found, we should make simulator
panic if the sc_module does not provide the interface we need.

Change-Id: I91e1036cb792d556dfc4010e7a0f138b1519b079
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40277
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-power: Delete unused register related constants.

Change-Id: I7b2dc3a9ce29f67d304a22ab15268390fc461e4e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39680
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Fix gem5img when used to manually unmount a disk image.

When unmounting a disk image manually using the
`gem5img umount mount_point` command, the operation can fail if the
process is unable to stat any of the mounts in the mount table. On
some systems this can occur even when running using sudo.

Added an exception check so any mount points that fail to stat will not
cause the whole script to terminate early.

Change-Id: I69cd2494ad0e8c989e19ecd8af8a811905cd6c09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39897
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Improve robustness of sfdisk parsing in util/gem5img.py

The format of the output of sfdisk can change between versions, and
can also change depending on the details of the disk image being
analysed. For example, extra attributes like grain size in the
preamble have been observed.

The current output parsing is quite brittle, expecting a specific
number of lines of preamble. This change switches to a regular
expression based method which searches the output for the line of
interest. The parsing will still be sensitive to changes in the output
of sfdisk, but hopefully less so than the current method.

Change-Id: If03fe999a4986049ae20709895ec1d1b42166023
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39896
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

util: Update util/gem5img.py to work with Python 3.

Tested on Ubuntu 18.04 with Python 3.6.8 and Python 2.7.15+.

Change-Id: Ic8b407ad41dc0d6d37a54a54eeef2b9156d893d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39895
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: remove incorrect cntfrq update

The register cntfrq should be set to system counter frequency.
However, the current fastmodel implementation accidentally set it to
core frequency. This CL removes the wrong implementation, and real
cntfrq setting is performed in the initState.

Change-Id: I6c62822a4fbbcc0c499f79f6003dabb0c133f997
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40276
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Fix packet parser for Python3

Change-Id: Id5124135b0dd4049ce6531d7bdbc562d33f4d299
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40075
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: set Gem5ToTlmBridge blockingRrequest with TLM_UPDATE returning

In Gem5ToTlmBridge::pec, the function expects blockingRequest should be
set no matter the tlm peer returns TLM_UPDATE or TLM_ACCEPTED.
However, current implementation only sets blockingRequest when the tlm
peer returns TLM_ACCEPTED. We should also set blockingRequest when the
tlm peer returns TLM_UPDATE.

Change-Id: I87bba3201cd68d52ded93c9c200f4fa4a40bdf5b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39815
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Fix style in arch/x86/types.hh.

Change-Id: I5e32eea9b843d4f68adf5430516d0636317c8a57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40103
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>

dev-hsa: Add missing include to hsa_driver.hh

Due to using ThreadContext::Suspended in hsa_driver.hh as of
965ad12b9a4ae4035b0f63e7ab083ac87258a071, we now need to include
cpu/thread_context.hh. This change fixes that.

Change-Id: I2c6882f2a29ca1638dd34cda42874b95cafbe548
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40216
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Stop using switching header files in ISA specific files.

We know what ISA we want, we don't need to use the indirection.

Change-Id: I57eb2737bb4d9abb562b857ad2c3238c641199d2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40104
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

arch: Correct style in the ISA base class.

Change-Id: I1732f519bf3eab1dff8b9a9a30fc8e5e132d067d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40105
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>

dev-hsa: enable interruptible hsa signal support

Event creation and management support from emulated drivers is required
to support interruptible signals in HSA and this support was not
available. This changeset adds the event creation and management support
in the emulated driver.  With this patch, each interruptible signal
created by the HSA runtime is associated with a signal event. The HSA
runtime can then put a thread waiting on a signal condition to sleep
asking the driver to monitor the event associated with that signal. If
the signal is modified by the GPU, the dispatcher notifies the driver
about signal value change.  If the modifier is a CPU thread, the thread
will have to make HSA API calls to modify the signal and these API calls
will notify the driver about signal value change. Once the driver is
notified about a change in the signal value, the driver checks to see if
any thread is sleeping on that signal and wake up the sleeping thread
associated with that event. The driver has also implemented the time_out
wakeup that can wake up the thread after a certain time period has
expired. This is also true for barrier packets.

Each signal has an event address in a kernel managed and allocated
event page that can be used as a mailbox pointer to notify an event.
However, this feature used by non-CPU agents to communicate with the
driver is not implemented by this changeset because the non-CPU HSA
agents in our model can directly communicate with driver in our
implementation. Having said that, adding that feature should be trivial
because the event address and event pages are correctly setup by this
changeset and just adding the event page's virtual address to our PIO
doorbell interface in the page tables and registering that pio address
to the driver should be sufficient. Managing mailbox pointer for an
event is based on event ID and using this event ID as an index into
event page, this changeset already provides a unique mailbox pointer for
each event.

Change-Id: Ic62794076ddd47526b1f952fdb4c1bad632bdd2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38335
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Eliminate the generic PseudoInstABI.

Calls to gem5 ops are now handled by locally defined ABIs in each of the
ISAs that support them.

Change-Id: I30aac7b49fa8dc8e18aa7724338d1fd2adacda90
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39319
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Replace Queue.Empty with queue.empty

Queue.Empty is not an exception in python3
(Queue has been renamed to queue)

Change-Id: I82555d96608094fa47990f888fd11663379547bc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40135
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Use MmioVirtIO for disk image in baremetal.py

The baremetal platform is the platform we use for running
user supplied binaries on baremetal hardware.
(simply put, it runs provided binaries without adding
a gem5 bootloader)

Some layers of this software stack might not have a pci driver.
This might be the case for firmware images like edkII
which needs to use a block device to extract the bootloader
and/or the kernel image. Those can use the memory mapped
(in host domain) virtio block device which is already
part of the VExpress_GEM5 platforms

Change-Id: I9c6ba7e1b4566a3999fd9ba20a2bebe191dc3ef8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39995
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix style in decoder.hh.

Change-Id: I45cf1fefc6145393abec2de12e74816c0c8ac0e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40096
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Style fixes in base/refcnt.hh

Change-Id: I8f4b2710bea1fe15baa1b482ff62fbab645a3690
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40095
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: fix unintentionally CSR bit overwritten in different mode

Some CSR register is physically shared between different privilige
level. Current implementation of CSR setting only considers to verify
the bits visable in current privilige level, and directly writes the
masked bits back to register. This leads to other bits invisable
to current mode is overwritten and wrong behavior across the modes.
Thus, CSR updating should always keep the bits value for other modes.
e.g. disabling interrupt in S mode with setting
SSTATUS SIE bit will lead to clear MIE bit as well (the interrupt
is disabled unintentionally).

All CSR register sharing same physical register in different mode
may have similar issue. I only fixed some important ones.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-860

Change-Id: I34d4766a4b483b5add2c3bbefd28b21b9abf37f6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39036
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch,base,mem,sim: Fix style in base/types.hh and remove extra includes.

The base/refcnt.hh header was not used in base/types.hh at all, and
enum/ByteOrder.hh was there just so other files could find it. Instead,
this change moves enum/Byteorder.hh to sim/byteswap.hh where it's fits
with the purpose of the header.

This change also fixes some style problems with the code in
base/types.hh itself.

Change-Id: I471ae5cb2cca9169ba8616fb8411b40108a3ffb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39855
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: implement POPCNT instruction.

Change-Id: Id6ddc1245c81a17720885f9038d55d0811ef7f4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39615
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, mem, cpu, systemc: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: Ib10d01d9398795f46eedeb91a02736f248917b6a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39758
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

tests: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I74b5250722abe1e202f31a9ec1d4cc04039df168
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39757
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Remove Python 2.7 glue code from testlib

Remove the dependency on six in testlib.

Change-Id: I247088d119cf8f9d815632eae16a1cbf87930516
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39759
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Fix compilation error for debug builds.

https://gem5-review.googlesource.com/c/public/gem5/+/39537 removed the
implicit use of the std:: namespace. This change adds a missing
namespace specifier for debug builds.

Change-Id: I1d70602a870a25f68d7fec4b4931ba7cbbb4f4ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39760
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,mem,sim: Use ADD_STAT macro where possible

Change-Id: I3cf0a2a321742445cf7100115eacbc411c70f4fb
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38916
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Fix reset of virtio devices

The VirtualQueue reset was just resetting the queue address but
it was not touching other cached state and its associated
ring buffers (used and avail)

Change-Id: I55cc767d791825899d62c4cd88b84809527f3f22
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39701
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Delete some unused register related constants.

Change-Id: Id5305a863675061b4afb27c71b329180605381b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39677
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-mips: Delete unused register related constants.

Change-Id: If14aa686eda59ff9c148371b4b7f6075b2abd1d8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39679
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Style fixes in cpu/reg_class.hh.

Change-Id: Ie8815c6351609dc9fba9d485e9496b7f7c8ce927
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39676
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Fix style in plain C++ StaticInst base classes.

Change-Id: I826fce4071fe413f16caffbcd519396eec1967a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39675
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Make the default checkBpLen method return true.

This was checking that the breakpoint length was equal to the length of
the ISA specific MachInst type. Instead, force the ISA specific remote
GDB subclass to implement a check if it wants to, specific to its needs.
The base implementation will just approve of any length, which should be
fine with a well behaved GDB client.

Change-Id: Id7325b788f8445049855f8104082b8e4da1fe300
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39661
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Delete the unused RemoteGDB::(set|clear)TempBreakpoint methods.

These are not used by anything, and use the ISA specific
TheISA::MachInst type.

Change-Id: Iae08e672b00834ccc5f11295b4c4529fbe7f8d0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39660
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Style fixes in cpu/exec_context.hh and thread_context.hh.

Change-Id: I2eb82cc6f6ba29c1df74e53b78b57c1a65577837
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39659
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86,cpu: Don't use aliases to hide TheISA::.

We need to gradually eliminate TheISA, and so it's helpful to know where
it's actually being used. This change stops hiding it behind using-s
and, in one case, a placeholder constant.

Change-Id: I391a3129256a9f7bd3b4002d0a46fb06b3068468
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39656
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base,cpu,sim: Stop "using namespace TheISA".

This was mostly not used to begin with, but also when it was used, it
would obscure places where there were types, functions, etc, which were
switched between ISAs at compile time, and which would need to be
cleaned up to allow more than one ISA at a time.

Change-Id: Ieb372feff91b7e946b477fb78e54bcd0c2138966
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39655
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Set the "status" field of the HDLCD device tree node to "ok".

This makes the kernel enable the device.

Change-Id: I2c237b9ba038c5128e2a7e020587ac46ef7b4abd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37936
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I8d6aae84d8192b301d541b8dc81275f4932f9f2f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39756
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I6e2f270557d7343bbad30c8e6d743e363c43715a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39755
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Use the Temperature type in power/thermal models

The thermal models currently work on temperatures in Celsius stored in
plain doubles. Switch to using Temperature instead and internal
processing in Kelvin. There should be no impact on the result since
all thermal processes work on temperature deltas.

Change-Id: I22d0261ae102f30d86051f24a2d88b067b321c91
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39455
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

dev-arm: Instantiate Generic Watchdog in Foundation platform

Change-Id: I75496eeabeabb81804d4055f8257309324d6476a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39700
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Implement Generic Watchdog

Change-Id: I53bcb6ae77c0bcc080f4be0bd2339d4d1f6a4b28
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39699
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: A SystemCounterListener doesn't have to be Serializable

The class is not making use of any Serializable utility.
By removing this dependency we can extend it more easilly

Change-Id: Ia321b8f0deeb92adde008551eb921dcfd365e675
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39698
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add a PL111 to the VExpress_GEM5_Foundation

The device is part of the FVP Foundation platform:

https://static.docs.arm.com/100961/1190/armv8_a_fp_ug_100961_1190_00_en.pdf

Change-Id: I91226cb10a3be50c59e32288b3643c550e8b538d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39697
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add a fake SP810 to the VExpress_GEM5_Foundation

The device is part of the FVP Foundation Platform:

https://static.docs.arm.com/100961/1190/armv8_a_fp_ug_100961_1190_00_en.pdf

Change-Id: I81c11312f29d8e59ac5f8ce2fe165d9474027d82
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39696
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: Enabled HDLcd by default in DTS

This is fine as people using *_hdlcd.dtsi are willing to simulate
an HDLcd

JIRA: https://gem5.atlassian.net/browse/GEM5-866

Change-Id: Ifd5d6ecc81de920dbc29a05b07f30c13dcee3aa4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38797
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm, system-arm: Remove HDLcd from VExpress_GEM5_VX platforms

This is a major change in our platform configuration.
At the moment the VExpress_GEM5_V1 and VExpress_GEM5_V2 platforms
both instantiate an HDLcd device. As the presence of the device
can slow down host performances when the software stack is
aware of its presence, we have historically been providing
an entry in the hdlcd DTB node to "hide" the entry from the
DTB parser:

status = "disable";

This default entry in the hdlcd node will in fact prevent the driver
from bringing up the device. Unfortunately this is useful for
experienced users only which are aware of this knob.

In order to make things more transparent, and to avoid any confusion
(e.g. having the hdlcd present in the config.ini, but not being able to
program it in Linux) we are deprecating this solution; we are removing
the HDLcd from the aforementioned platforms.

Users not interested on simulating a display controller won't
notice the difference.
Users interested on including it, will now have to switch to a new

VExpress_GEM5_Vx_HLCD platform

which will enabled the HDLcd without any further tweaking required

JIRA: https://gem5.atlassian.net/browse/GEM5-866

Change-Id: I4b1920efe764080115a57f52d8a3df2e6e2386a0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38796
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

riscv: Export the system call ABI for use in gem5 ops.

This ABI is effectively used by both the gem5 ops and system calls, in
system calls because it only relies on registers, and in gem5 ops by
inheritance.

Even though these ABIs happen to be the same and were initially defined
to be the same, this change creates a root "reg" ABI which will act as a
root for both so that there isn't an implication that changes to one
should be changes to both.

Change-Id: I8726d8628503be2ad7616a71cc48b66f13e7d955
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39318
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Require a unit in anyToFrequency and anyToLatency

The anytToFrequency and anyToLatency conversion functions are
currently ambiguous when called without a unit. Fix this by always
requiring a unit.

Change-Id: I5ea94e655f7ca82c0efe70b9f9f7f734fbf711c1
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39435
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

sim: Use the Temperature param type

Add support for passing typed temperatures using the new Temperature
param type.

Change-Id: If68d619fd824e171d895a5cbbe4d0325d4c4f4db
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39219
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

base, python: Add a Temperature type and associated param

Add a class to represent a temperature. The class stores temperatures
in Kelvin and provides helper methods to convert to/from Celsius. The
corresponding param type automatically converts from Kelvin, Celsius,
and Fahrenheit to the underlying C++ type.

Change-Id: I5783cc4f4fecbea5aba9821dfc71bfa77c3f75a9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39218
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Don't use TheISA in the ARM implementation.

We know what ISA we're using, so we can use ArmISA directly.

Change-Id: I7d207eea2581bae8be3e870883de88bf2879ef12
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39657
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Added list types of replacement policy.

Replacement policy is one of the key points in CPU performance. For ease
of checking the avliable replacment types for any cpu architects,
"replacment policy list" is added in Options.py and ObjectList.py.
Just like Branch Prediction Policies, adding such list would make it efficient for compare cpu performance
regarding different replacment policies especially for Cache.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-853

Change-Id: I97358617038fdcec79fa7e59baba8926284727b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39195
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: Move display node into a shared DTS file

armv7, armv8, armv8_big_little DTS files are reusing the same
encoder node; moreover those should really be cpu specific files.

For these reasons, and to make it possible to craft a final DTS
without defining a display phandle, we move the shared code into
a display DTS include file

Change-Id: I4f756807292e492a743bb9ab9ec511011125a436
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38795
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Refactor toNum to support a selection of units

Add support for matching one of several different units in toNum. The
units parameter can now either be a tuple or a string describing the
supported unit(s). The function now returns a (magnitude, unit) tuple.

Change-Id: I683819722a93ade91a6def2bfa77209c29b4b39e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39217
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

cpu: Eliminate the empty cpu/exec_context.cc.

Change-Id: I1a675b3c4f09a7119531e2513e3d1f9f8c7f0c0d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39658
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-power: Stop "using namespace std"

Change-Id: Iab8acba7c01a873db660304bb85661e75ffbe854
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39556
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

arch-arm: Add set_reg_idx_arr to SveStructMemSIMicroopDeclare

This should have been part of:

https://gem5-review.googlesource.com/c/public/gem5/+/38381

Change-Id: I1914fdcd0382fc95dcead2eafa09de12a43776ab
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39635
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: remove pipe through flag in TLM extension

Pipe through flag should be equal to whether we have the extension
in TLM payload or not. However, in the current implementation the
two are different and cause issues when we have gem5 - SystemC
connection.

Change-Id: I2c318777d91dca446c1a700d9f7cff356d29ae6d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37375
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Earl Ou <shunhsingou@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Add Python unit tests for m5.util.convert

Python unit tests need to be run from within gem5. This change adds a
script to run unit tests (tests/run_pyunit.py) and a unit test for
m5.util.convert.

The tests can be run as follows:

  ./build/NULL/gem5.opt tests/run_pyunit.py

Change-Id: I80d1aabbe1d87b01b48280972f9418317e648779
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39377
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

sim: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I797163c8690ae0092e00e371d75f5e7cebbcd1f5
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39579
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I3d0bbfa00968486af8d57c36be2c8bee034bae93
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39577
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm, dev-arm: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I9b47194d26d71c8ebedda6c31a5bac54b600d3bf
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39575
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Stop "using namespace std" in unittest/.

These are the historical "unit test"s, which aren't really unit tests,
they're actually complete builds of gem5 with main functions which run a
fairly specific test instead of a simulation. They test a single unit,
but they do it with all the other units in place and potentially
participating in the test.

Change-Id: Ib0ea68f26091a79992396d932627e4ce180f7825
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39565
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Stop "using namespace std" in protoio.cc.

Change-Id: I4f27979910230860c631b63bb500f87b45c24e33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39563
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Stop "using namespace std"

Change-Id: I1b648914d353672076d903ed581aa61cdd7c1d0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39562
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Stop "using namespace std"

Change-Id: If0f373bdaadce81c5ebbc37b03810335c42dd10a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39561
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-sparc: Stop "using namespace std"

Change-Id: I4a1019b5978b08b4999edfe5f65ef7eae06481c2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39560
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-mips: Stop "using namespace std"

Change-Id: I0ad5ad71d8ba2d7c050d3f368341ce98d3f87a90
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39559
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>