mesa: Add support for the GL_KHR_context_flush_control extension

The GL side of this extension just provides an accessor via glGetIntegerv for
the value of GL_CONTEXT_RELEASE_BEHAVIOR so it is trivial to implement. There
is a constant on the context for the value of the enum which is initialised to
GL_CONTEXT_RELEASE_BEHAVIOR_FLUSH. The extension is always enabled because it
doesn't need any driver interaction to retrieve the value.

If the value of the enum is anything but FLUSH then _mesa_make_current will
now refrain from calling _mesa_flush. This should only affect drivers that
explicitly change the enum to a non-default value.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

gles2: Update gl2ext.h to revision 28335

The main incentive to do this is to get the defines for the
GL_KHR_context_flush_control extension.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/fs: Don't set dependency hints on instructions with spilled destinations

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Make scratch write instructions use the correct execution size

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Use correct spill offsets

Different platforms require the offset to be in different units.  However,
the generator fixes all of this up for us and only requires an offset in
bytes.  Previously, we were getting this wrong all over the place.  Some
computed/used it correctly as bytes while others treated the offset as
whole registers or computed it as bytes or bytes*2 in SIMD16 mode.  This
commit cleans all this up and makes us properly treat it as bytes
everywhere.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Use the spill destination for the message header on GEN >= 7

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Don't [un]spill multiple registers at a time in SIMD8 mode

I thought this would be a clever way to make spilling less expensive.
However, it appears that the oword read/write messages we are using for
spilling ignore the execution size and assume SIMD16 whenever working with
more than one register.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Use instruction execution sizes when generating scratch reads/writes

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

egl/drm: do not crash when swapping buffers without any rendering

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

nv50: handle inverted render conditions

This enables ARB_conditional_render_inverted.

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/ir3: consider instruction neighbors in cp

Fanin (merge) nodes require it's srcs to be "adjacent" in consecutive
scalar registers.  Keep track of instruction neighbors in copy-
propagation step and avoid eliminating mov's which would cause an
instruction to need multiple distinct left and/or right neighbors.

This lets us not fall on our face when we encounter things like:

  1: MOV TEMP[2], IN[0].xyzw
  2: TEX OUT[0].xy, TEMP[2], SAMP[0], SHADOW2D
  3: MOV TEMP[2].xy, IN[0].yxzz
  4: TEX OUT[0].zw, TEMP[2], SAMP[0], SHADOW2D
  5: END

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: always mov tex coords

Always insert extra mov's for the tex coord into the fanin.  This
simplifies things a bit, and avoids a scenario where multiple sam
instructions can have mutually exclusive input's to it's fanin, for
example:

  1: TEX OUT[0].xy, IN[0].xyxx, SAMP[0], 2D
  2: TEX OUT[0].zw, IN[0].yxxx, SAMP[0], 2D

The CP pass can always remove the mov's that are not actually needed,
so better to start out with too many mov's in the front end, than not
enough.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: rename a couple debug flags

dscis -> noscis
dbypass -> nobypass

a bit more consistant w/ nobin, etc.  And IMO a bit more sensible names.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: skip virtual outputs in standalone compiler

Kills get added to the outputs list, to ensure they get scheduled.  But
they aren't *really* outputs so skip them in the header comment block.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

glx: Fix make check.

This fixes https://bugs.freedesktop.org/show_bug.cgi?id=85429.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>

mesa: Add ARB_clip_control.xml to automake.

Adding this makes 'make check' catch failures introduced from
within ARB_clip_control.xml earlier.

Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>

freedreno/ir3: standalone compiler updates for ir3test

In order to test compiler changes more easily, spit out the assembled
shader with some header information so that we can know about
inputs/outputs more easily.

See: git://people.freedesktop.org/~robclark/ir3test

In ir3test we have a big collection of tgsi shaders and reference
ir3_compiler outputs.  When making compiler changes, regenerate the
compiler outputs and feed to ir3test to compare the new vs reference
shader.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

ilo: improve blob decoding

The last few dwords were skipped if the total number of dwords was not a
multiple of 4.  Change the formatting for better readability.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>

i965: Skip recalculating URB allocations if the entry size didn't change.

We only get here if the VS/GS compiled programs change, but we can even
skip it if the VS/GS size didn't change.

Affects cairo runtime on glamor by -1.26471% +/- 0.674335% (n=234)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Standardize names and fix typos

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Silence unused parameter warning in brw_dump_ir

Just remove the parameter.  Silences:

brw_program.c: In function 'brw_dump_ir':
brw_program.c:566:33: warning: unused parameter 'brw' [-Wunused-parameter]

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Remove brwIsProgramNative

Originally I just fixed some unused parameter warnings in this
function.  However, Ken pointed out:

    "You could instead remove this driver hook.  If the dd pointer is
    NULL, arbprogram.c will return true.  I think I'd prefer that."

Way, way back in time, I think _mesa_GetProgramivARB had the opposite
behavior.  Given that it works the way it now works, I also prefer
removing the driver hook.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Silence unused parameter warning in _mesa_init_shader_program

Just remove the parameter.  Silences:

../../src/mesa/main/uniform_query.cpp:1062:1: warning: unused parameter 'ctx' [-Wunused-parameter]

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Remove context parameter from dd_function_table::NewShaderProgram

This fixes some unused parameter warnings introduced by the previous
commit.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Make _mesa_init_shader_program static

Since a couple commits ago, there is only one caller, and that caller is
in the same file.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Remove context parameter from _mesa_init_shader_program

Silences:

../../src/mesa/main/shaderobj.c: In function '_mesa_init_shader_program':
../../src/mesa/main/shaderobj.c:239:46: warning: unused parameter 'ctx' [-Wunused-parameter]

For now, this adds a couple other unused parameter warnings, but future
patches will clean those up.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl_to_tgsi: Remove st_new_shader

It was identical to the default implementation in _mesa_new_shader.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: Dave Airlie <airlied@redhat.com>

glsl_to_tgsi: Remove st_new_shader_program

It was identical to the default implementation in
_mesa_new_shader_program.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: Dave Airlie <airlied@redhat.com>

i965: Remove brw_new_shader_program

It was identical to the default implementation in
_mesa_new_shader_program.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Silence unused parameter warning in _mesa_clear_shader_program_data

Just remove the parameter.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

linker: Rely on _mesa_clear_shader_program_data to clear link information

_mesa_link_shader_program already calls _mesa_clear_shader_program_data
before calling link_shaders, so this is already done.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: Add some missing clean-up to _mesa_clear_shader_program_data

All of this is already done in link_shaders.  More clean-ups coming.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Remove prototypes for nonexistent functions

_mesa_UseShaderProgramEXT, _mesa_ActiveProgramEXT, and
_mesa_CreateShaderProgramEXT were all removed when support for
GL_EXT_separate_shader_objects was removed.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

ff_fragment_shader: Silence unused parameter warning in smear

Just remove the parameter.  Silences:

../../src/mesa/main/ff_fragment_shader.cpp:668:1: warning: unused parameter 'p' [-Wunused-parameter]

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

meta: Only use _mesa_ClipControl if the extension is supported

Fixes many piglit failures on IVB since 85edaa8.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85425
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: Mathias Fröhlich <Mathias.Froehlich@gmx.net>

docs: add news item and link release notes

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

docs: Add sha256 sums for the 10.3.2 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 95994706429e08665d1d33d248c8bcd67d40251e)

Add release notes for the 10.3.2 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 3b6a4758fa8958db4b76e6d7efccc93b12b1da06)

i965/fs: Compute q-values for register allocation manually

Previously, we were allowing the register allocation code to do the
computation for us in ra_set_finalize.  However, the runtime for this
computation is O(c^4 * g) where c is the number of classes and g is the
number of GRF registers.  However, these q-values are directly computable
based on the way we lay out our register classes so there is no need for
the aweful runtime algorithm.

We were doing ok until commit 7210583eb where we bumped the number of
register classes from 11 to 16.  While startup times don't normally matter,
this caused piglit to take 4 times as long to run on Bay Trail.  This patch
should make generating the ra_set much faster and melt the piglit run
times.

v2: Fixed a couple of bugs.  I have now verified that the same q-values are
generated both ways.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Don't interfere with too many base registers

On older GENs in SIMD16 mode, we were accidentally building too much
interference into our register classes.  Since everything is divided by 2,
the reigster allocator thinks we have 64 base registers instead of 128.
The actual GRF mapping still needs to be doubled, but as far as the ra_set
is concerned, we only have 64.  We were accidentally adding way too much
interference.

Signed-off-by: Jason Ekstrand <jason.ekstrand@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Properly precolor payload registers on GEN5 in SIMD16

For GEN6 SIMD16 mode, we have to 2-align all the registers, so we only have
the even-numbered ones.  This means that we have to divide the register
number by 2 when we precolor.  This wasn't a problem before because we were
setting up the interference between ra_node registers wrong.  This will be
fixed in the next commit.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Add another use of MAX_VGRF_SIZE

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

util: Use reg_belongs_to_class instead of BITSET_TEST

This shouldn't be a functional change since reg_belongs_to_class is just a
wrapper around BITSET_TEST.  It just makes the code a little easier to
read.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

llvmpipe: Ensure the packed input of the lp_test_format is aligned.

Fixes:
- https://bugs.freedesktop.org/show_bug.cgi?id=85377
- http://llvm.org/bugs/show_bug.cgi?id=21365

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

llvmpipe: Flush stdout on lp_test_* unit tests.

So that the order of test messages and gallivm/llvmpipe debug output is
preserved.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: Enable ARB_clip_control for gallium drivers.

Gallium should be prepared fine for ARB_clip_control.
So enable this and mention it in the release notes.

v2:
Only enable for drivers announcing the freshly introduced
PIPE_CAP_CLIP_HALFZ capability.

v3:
Use extension enable infrastructure to connect PIPE_CAP_CLIP_HALFZ
with ARB_clip_control.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>

gallium: introduce PIPE_CAP_CLIP_HALFZ.

In preparation of ARB_clip_control. Let the driver decide if
it supports pipe_rasterizer_state::clip_halfz being set to true.

v3:
Initially enable on ilo.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de

mesa: Handle clip control in meta operations.

Restore clip control to the default state if MESA_META_VIEWPORT
or MESA_META_DEPTH_TEST is requested.

v3:
Handle clip control state with MESA_META_TRANSFORM.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>

mesa: Implement ARB_clip_control.

Implement the mesa parts of ARB_clip_control.
So far no driver enables this.

v3:
Restrict getting clip control state to the availability
of ARB_clip_control.
Move to transformation state.
Handle clip control state with the GL_TRANSFORM_BIT.
Move _FrontBit update into state.c.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>

mesa: Refactor viewport transform computation.

This is for preparation of ARB_clip_control.

v3:
Add comments.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>

vc4: Reuse uniform_data/contents indices when making uniforms.

This allows vc4_opt_cse.c to CSE-away operations involving the same
uniform values.

total instructions in shared programs: 37341 -> 36906 (-1.16%)
instructions in affected programs:     10233 -> 9798 (-4.25%)
total uniforms in shared programs: 10523 -> 10320 (-1.93%)
uniforms in affected programs:     2467 -> 2264 (-8.23%)

vc4: When asked to discard-map a whole resource, discard it.

This saves a bunch of extra flushes when texsubimaging a whole texture
that's been used for rendering, or subdataing a whole BO.  In particular,
this massively reduces the runtime of piglit texture-packed-formats (when
the probes have been moved out of the inner loop).

vc4: Refactor flushing before mapping a BO.

I'm going to want to make some other decisions here before flushing.

vc4: Allow dead code elimination of unused varyings.

total instructions in shared programs: 39022 -> 37341 (-4.31%)
instructions in affected programs:     26979 -> 25298 (-6.23%)
total uniforms in shared programs: 11242 -> 10523 (-6.40%)
uniforms in affected programs:     5836 -> 5117 (-12.32%)

vc4: Add debug output to match shaderdb info to program dumps.

I'm going to be using VC4_DEBUG=shaderdb,norast to do shaderdb stats, but
when debugging regressions, I want to match shaderdb output to shader
disassembly.

radeon: enable Hyper-Z on r600g and radeonsi by default

This reverts commit 01e637114914453451becc0dc8afe60faff48d84.
Since then many Hyper-Z issues have been fixed or worked around.

Enable Hyper-Z by default so that we get enough feedback for the upcoming
mesa 10.4 release.

If you have issues with Hyper-Z try to disable Hyper-Z using the enviroment
variable R600_DEBUG=nohyperz and please report the issue on the bugtracker.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75011
See also: https://bugs.freedesktop.org/show_bug.cgi?id=75112

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965: Silence unused variable warning.

i965/fs: Silence uninitialized variable warning.

The compiler isn't privy to the knowledge that we're doing at least one
framebuffer write.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

util: Add assume() macro.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glapi: Fix compiler warning and script name

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

Revert "freedreno/a3xx: only emit dirty consts"

This reverts commit 94bb33617d1e8978dc52b8aaa4eb41bfb6703f79.

Which somehow broke gnome-shell.. and needs more investigation.  For
now, revert..

freedreno: fix PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE

fd_bo_cpu_prep() doesn't realize the bo is already referenced in
unflushed cmdstream.  It could be made to do so (but would have to be
implemented twice, ie. both for msm and kgsl).  But we still can't do
the expected thing if the caller isn't using _NOSYNC.  Because of the
way the tiling works, we need to build quite a bit of cmdstream at flush
time, which is not possible to do at the libdrm level.

So rather than trying to make fd_bo_cpu_prep() smarter than it can
possibly be, just *always* discard and reallocate if the
PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE flag is set.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

clover: Require libelf

v2: test for libelf once, check in both radeon and clover

CC: Tom Stellard <tom@stellard.net>
CC: Emil Velikov <emil.l.velikov@gmail.com>
CC: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

clover: use correct typenames for compat::pair's first/second

Seems to be a typo judging from the overall declaration of the
template.

Cc: EdB <edb+mesa@sigluy.net>
Cc: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

auxiliary/os: get the mmap/munmap wrappers working with android

 - Use macro for munmap under Android - the STATIC_ASSERT uses
a off_t which is not used under Android for mmap. As loff_t size
does not vary as does off_t just ignore the assert.

 - Wrap the long lines to improve readability.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

gallium/nouveau: fully build the driver under android

Fix the trivial typo in the variable name.

Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>

mesa/shaderimage.c: fix inconsistent sign warning

Signed-off-by: Alon Levy <alevy@redhat.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

wgl: stw_pixelformat_get_info: correct type for index variable

Signed-off-by: Alon Levy <alevy@redhat.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

u_math.h: fix 64 to 32 bit truncation warning

Signed-off-by: Alon Levy <alevy@redhat.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

gallivm: Fix build with LLVM 3.3.

The setMCJITMemoryManager method doesn't exist in LLVM 3.3.

I thought I had tested the latest version of my earlier change with LLVM
3.3, but it looks I missed it.

Trivial.

gallivm: Properly update for removal of JITMemoryManager in LLVM 3.6.

JITMemoryManager was removed in LLVM 3.6, and replaced by its base class
RTDyldMemoryManager.

This change fixes our JIT memory managers specializations to derive from
RTDyldMemoryManager in LLVM 3.6 instead of JITMemoryManager.

This enables llvmpipe to run with LLVM 3.6.

However, lp_free_generated_code is basically a no-op because there are
not enough hook points in RTDyldMemoryManager to track and free the code
of a module.  In other words, with MCJIT, code once created, stays
forever allocated until process destruction.  This is not speicfic to
LLVM 3.6 -- it will happen whenever MCJIT is used regardless of version.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallivm: Fix white-space.

Replace tabs with spaces.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallivm,llvmpipe,clover: Bump required LLVM version to 3.3.

We'll need to update gallivm for the interface changes in LLVM 3.6, and
the fewer the number of older LLVM versions we support the less hairy that
will be.

As consequence HAVE_AVX define can disappear.  (Note HAVE_AVX meant
whether LLVM version supports AVX or not.  Runtime support for AVX is
always checked and enforced independently.)

Verified llvmpipe builds and runs with with LLVM 3.3, 3.4, and 3.5.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: remove conditional render and rgtc from ES3 requirements

The functionality exposed by those extensions does not appear in ES3

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>

u_blitter: put a comment on util_blitter_cache_all_shaders()

Trivial.

u_blitter: use ctx->bind_fs_state(), not pipe->bind_fs_state()

Consistently use the function pointer we saved earlier.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

u_blitter: create basic fs shaders in util_blitter_cache_all_shaders()

We need to create all fs shaders in this function.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

u_blitter: do error checking assertions for shader caching

If the user calls util_blitter_cache_all_shaders() set a flag and assert
that we never try to create any new fragment shaders after that point.
If the assertions fails, it means we missed generating some shader in
util_blitter_cache_all_shaders().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: Use signed array index in update_max_array_access()

Avoids a crash in case of negative array index is used in a
shader program.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

glsl: Fix crash due to negative array index

Currently Mesa crashes with a shader like this:

[fragmnet shader]
float[5] array;
int idx = -2;
void main()
{
   gl_FragColor = vec4(0.0, 1.0, 0.0, array[idx]);
}

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

radeonsi: implement pipe_rasterizer_state::clip_halfz

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: implement pipe_rasterizer_state::clip_halfz

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r300g: implement pipe_rasterizer_state::clip_halfz

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: Drop references to destroyed blend state

Fixes use-after-free when the currently bound blend state is destroyed.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85267
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84140

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: mesa-stable@lists.freedesktop.org

i965/vec4: Generate better code for ir_triop_csel.

Previously, we generated an extra CMP instruction:

   cmp.ge.f0(8)    g6<1>D          g1<0,4,1>F      0F
   cmp.nz.f0(8)    null            g6<4,4,1>D      0D
   (+f0) sel(8)    g5<1>F          g1.4<0,4,1>F    g2<0,4,1>F

The first operand is always a boolean, and we want to predicate the SEL
on that.  Rather than producing a boolean value and comparing it against
zero, we can just produce a condition code in the flag register.

Now we generate:

   cmp.ge.f0(8)    null            g1<0,4,1>F      0F
   (+f0) sel(8)    g5<1>F          g1.4<0,4,1>F    g2<0,4,1>F

No difference in shader-db.

v2: Remember to delete the old code (thanks Matt).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Simplify visit(ir_expression *)'s result_src/dst setup.

Using dst_reg(this, ir->type) automatically sets the writemask to the
proper size for the type; src_reg(dst_reg) preserves that.  This should
be equivalent, but less code.

Note that src_reg(dst_reg) either uses SWIZZLE_XXXX or SWIZZLE_XYZW, so
the old code did need the manual writemask adjustment, since it
constructed the registers the other way around.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Delete some dead code in visit(ir_expression *).

Nothing uses the vector_elements temporary variable.

Setting this->result.file is dead because we overwrite this->result a
few lines later.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Generate better code for ir_triop_csel.

Previously, we generated an extra CMP instruction:

   cmp.ge.f0(8)   g4<1>D          g2<0,1,0>F      0F
   cmp.nz.f0(8)   null            g4<8,8,1>D      0D
   (+f0) sel(8)   g120<1>F        g2.4<0,1,0>F    g3<0,1,0>F

The first operand is always a boolean, and we want to predicate the SEL
on that.  Rather than producing a boolean value and comparing it against
zero, we can just produce a condition code in the flag register.

Now we generate:

   cmp.ge.f0(8)    null            g2<0,1,0>F      0F
   (+f0) sel(8)    g124<1>F        g2.4<0,1,0>F    g3<0,1,0>F

total instructions in shared programs: 5473459 -> 5473253 (-0.00%)
instructions in affected programs:     6219 -> 6013 (-3.31%)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Delete unused gl_uniform_driver_format enum values.

A while back, Matt made the uniform upload functions simply upload
ctx->Const.UniformBooleanTrue for boolean values instead of 0/1, which
removed the need to convert it later.  We also set UniformBooleanTrue to
1.0f for drivers which want to treat booleans as 0.0/1.0f.

Nothing ever sets these, so they are dead.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

freedreno/a3xx: fix depth/stencil restore format

Also fix z16 restore format which was completely wrong.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a3xx: fix viewport state during clear

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: mark scissor state dirty when enable bit changes

We don't have a scissor enable bit in hw, so when a raster state change
results in scissor enable bit changing, we need to also mark scissor
state as dirty.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: clear vs scissor

The optimization of avoiding restore (mem2gmem) if there was a clear
falls down a bit if you don't have a fullscreen scissor.  We need to
make the decision logic a bit more clever to keep track of *what* was
cleared, so that we can (a) completely skip mem2gmem if entire buffer
was cleared, or (b) skip mem2gmem on a per-tile basis for tiles that
were completely cleared.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

clover: Fix build error with LLVM 3.4.

DataLayoutPass was added in LLVM 3.5 r202168, commit
57edc9d4ff1648568a5dd7e9958649065b260dca "Make DataLayout a plain
object, not a pass.".

This patch fixes this build error with LLVM 3.4.

  CXX      llvm/libclllvm_la-invocation.lo
llvm/invocation.cpp: In function 'void {anonymous}::optimize(llvm::Module*, unsigned int, const std::vector<llvm::Function*>&)':
llvm/invocation.cpp:324:18: error: expected type-specifier
       PM.add(new llvm::DataLayoutPass(mod));
                  ^

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85189
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

r600g,radeonsi: convert TGSI shader type to LLVM shader type

The values are hardcoded in the LLVM backend, but the TGSI definitions are
going to be changed with tessellation, e.g. TGSI_PROCESSOR_COMPUTE will be
increased by 2.

We'll use VS for LS and HS, because there's nothing special about them
from the LLVM backend point of view, even though the hardware side is
different. We do the same for ES.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: add some missing register definitions

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: load ring resource descriptors only once

v2: document the new functions

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: clarify shader constant load functions

I'll need indexed loads without the meta data flag for tessellation later.
Also rename load_const to buffer_load_const to distinguish it from indexed
const loads.

v2: add comments

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: statically declare resource and sampler arrays

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: remove conversion of DX9 FACE input to GL

st/mesa and gallium expect the DX9 format, so this is useless.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>