amd/common: remove unnecessary num_user_sgprs_used

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

amd/common: remove unnecessary user_sgpr_count

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radeonsi: make use of ac_init_exec_full_mask()

Similar to si_init_exec_full_mask().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

svga: use tgsi_util_get_shadow_ref_src_index() in a couple place

No piglit changes.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

tgsi: improve comment on tgsi_util_get_shadow_ref_src_index()

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: fix TGSI_TEXTURE_SHADOW1D coordinate selection

Fixes about 24 Piglit tex-miplevel-selection tests.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: fix shadow comparison failures

In some cases, We do shadow comparison cases in the fragment shader
instead of with texture sampler state.  But when we do so, we must
disable the shadow comparison test in the sampler state.  As it
was, we were doing the comparison twice, which resulted in nonsense.
Also, we had the texcoord and texel value swapped in the comparison
instruction.

Fixes about 38 Piglit tex-miplevel-selection tests.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

util: add trivial comment on u_upload_create()

r600: fix atomic counter index mode getting emitted on pre-cayman

This is a regression since I added cayman atomic support, not sure
it fixes anything, but the shader dumps look better.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: set some dcc parameters depending on if texture will be sampled

This is ported from amdvlk which sets the independent 64b blocks
only for image which will sample dcc.

I'm not sure how to port this to radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/radeonsi: set dcc min uncompressed properly for APUs.

This is ported from amdvlk.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

amd/common/radv/radeonsi: use register defines for dcc block sizes.

These are just taken from amdvlk, we probably knew these already,
but may as well port them now.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

st/glsl_to_nir: add patch support to st_nir_assign_var_locations()

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/glsl_to_nir: call post opt functions after opts have finished

We need to move this to a separate loop because
nir_compact_varyings() can alter the IR of a previous stage.

Fixes: 6648bd68fd27 "st/glsl_to_nir: enable NIR link time opts"
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/st_glsl_to_nir: call nir_lower_64bit_pack

Fixes 56 crashes in the radeonsi nir backend.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

docs/features: show es3.1 compat done on r600.

This was already being reported, just missed the docs.

Reported-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: always compare optype with symbolic name in ATI_fs

Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: document ati_fragment_shader::cur_pass and swizzlerq

Signed-off-by: Miklós Máté <mtmkls@gmail.com>

mesa: move ATI_fs state compile changes after the error checks

Both in setup and arithmetic instructions. Also, remove the useless
new_*_inst() functions, and refactor check_arith_arg(), because it did
two completely different things.

Piglit: spec/ati_fragment_shader/error04-endshader

Signed-off-by: Miklós Máté <mtmkls@gmail.com>

tnl: fix not having texture coords in ATI_fs in swrast

ATI_fs in swrast only had access to texture coordinates if there was a
valid texture bound and texturing was enabled.

Piglit: spec/ati_fragment_shader/render-sources and render-notexture

Signed-off-by: Miklós Máté <mtmkls@gmail.com>

mesa: fix not having secondary color in ATI_fs in swrast

ATI_fs in swrast only had secondary color if GL_COLOR_SUM was enabled.
This patch probably fixes the same issue in r200.

Piglit: spec/ati_fragment_shader/render-sources and render-precedence

Signed-off-by: Miklós Máté <mtmkls@gmail.com>

mesa: fix validate for secondary interpolator

This patch fixes multiple problems:
- the interpolator check was duplicated
- both had arg instead of argRep
- I split it into color and alpha for better readability and error msg
- the DOT4 check only applies to color instruction according to the spec
- made the DOT4 check fatal, and improved the error msg

Piglit: spec/ati_fragment_shader/error08-secondary

v2: fixed formatting, added spec quotations

Signed-off-by: Miklós Máté <mtmkls@gmail.com>

mesa: fix typo in ATI_fs dstMod error checking

Piglit: spec/ati_fragment_shader/error14-invalidmod

Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: fix crash when an ATI_fs pass begins with an alpha inst

This fixes crash when:
- first pass begins with alpha inst
- first pass ends with color inst, second pass begins with alpha inst
Also, use the symbolic name instead of a number.

Piglit: spec/ati_fragment_shader/api-alphafirst

v2: fixed formatting

Signed-off-by: Miklós Máté <mtmkls@gmail.com>

mesa: add fallback texture for SampleMapATI if there is nothing

This fixes crash in the state tracker.

Piglit: spec/ati_fragment_shader/render-notexture

v2: fixed formatting, moved stuff inside the loop,
    moved the fallback later to fix more cases

Signed-off-by: Miklós Máté <mtmkls@gmail.com>

radeonsi: don't use fast color clear for small images even on APUs

Increase the limit and handle non-square images better.

This makes glxgears 20% faster on APUs, and a little more on dGPUs.
We all use and love glxgears.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: set PNT_SPRITE_ENA = point_quad_rasterization

This is based on how nvc0 translates the state.

gallium/util: add util_num_layers helper

radv: Fix DCC compatible formats.

DCC was disabled when the image format is !!supported, which is one ! too many.

Ironically the commit that introduced it was supposed to lead to more DCC use ...

Fixes: 969537d9358 "radv: Add support for more DCC compression with VK_KHR_image_format_list."
Reviewed-by: Dave Airlie <airlied@redhat.com>

Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+"

This reverts commit 9cd60fce9c22737000a8f8dc711141f8a523fe75.
Above commit caused 2000+ piglit tests to assert fail. Disabling
the align1 mode on gen10 for now to avoid failures.

Cc: Matt Turner <mattst88@gmail.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>

docs: update calendar, add news item and link release notes for 17.2.8

Signed-off-by: Andres Gomez <agomez@igalia.com>

docs: add sha256 checksums for 17.2.8

Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 3281775ab9993d700a0a01a2823b6e7c72fce150)

docs: add release notes for 17.2.8

Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 3482790712e92d660706952f9ff282d904415941)

freedreno: set missing internal_format when importing texture

Fixes running piglits without -fbo. Probably lots of other stuff too.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@gmail.com>

amd/common: add ac_export_mrt_z() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

amd/common: pass the family to ac_llvm_context_init()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: reduce the number of small surfaces that need CMASK or DCC

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

gm107/ir: use lane 0 for manual textureGrad handling

This is parallel to the pre-SM50 change which does this. Adjusts the
shuffles / quadops to make the values correct relative to lane 0, and
then splat the results to all lanes for the final move into the target
register.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-By: Karol Herbst <kherbst@redhat.com>

radv/meta: fix blit paths for depth/stencil (v2.1)

This fixes the layout issue for the blit path as well.

This fixes:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint*

v2: use compatible render passes.
v2.1: use enum

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: handle depth/stencil image copy with layouts better. (v3.1)

If we are doing a general->general transfer with HIZ enabled,
we want to hit the tile surface disable bits in radv_emit_fb_ds_state,
however we never get the current layout to know we are in general
and meta hardcoded the transfer layout which is always tile enabled.

This fixes:
dEQP-VK.api.copy_and_blit.core.image_to_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint.optimal_general
dEQP-VK.api.copy_and_blit.core.image_to_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint.general_general

v2: refactor some shared helpers for blit patches
v3: we only need multiple render passes as they should be compatible.
v3.1: use enum (Bas)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: refactor blit2d pipeline creation

This just refactors the gfx9 blit2d pipeline creation
to be less lines of code.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/gfx9: add support for 3d images to blit 2d paths

This add support for a 3D image reading path to the blit 2d paths,
like I did for the clear paths.

Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/gfx9: add 3d sampler image->buffer copy shader. (v3)

On GFX9 we must access 3D textures with 3D samplers AFAICS.

This fixes:
dEQP-VK.api.image_clearing.core.clear_color_image.3d.single_layer

on GFX9 for me.

v1.1: fix tex->sampler_dim to dim
v2: send layer in from outside
v3: don't regress on pre-gfx9

Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: fix surface max layer count (v2)

looking at traces I noticed we'd set slice_max too large sometimes.

This should fix it.

v2: fix missing - 1

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

intel/fs: Initialize fs_visitor::grf_used on construction.

This should shut up some Valgrind errors during pre-regalloc
scheduling.  The errors were harmless since they could only have led
to the estimation of the bank conflict penalty of an instruction
pre-regalloc, which is inaccurate at that point of the program
compilation, but no less accurate than the intended "return 0"
fall-back path.  The scheduling pass is normally re-run after regalloc
with a well-defined grf_used value and accurate bank conflict
information.

Fixes: acf98ff933d "intel/fs: Teach instruction scheduler about GRF bank conflict cycles."
Reported-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

intel/fs/bank_conflicts: Use posix_memalign() instead of overaligned new to obtain vector storage.

The weight_vector_type constructor was inadvertently assuming C++17
semantics of the new operator applied on a type with alignment
requirement greater than the largest fundamental alignment.
Unfortunately on earlier C++ dialects the implementation was allowed
to raise an allocation failure when the alignment requirement of the
allocated type was unsupported, in an implementation-defined fashion.
It's expected that a C++ implementation recent enough to implement
P0035R4 would have honored allocation requests for such over-aligned
types even if the C++17 dialect wasn't active, which is likely the
reason why this problem wasn't caught by our CI system.

A more elegant fix would involve wrapping the __SSE2__ block in a
'__cpp_aligned_new >= 201606' preprocessor conditional and continue
taking advantage of the language feature, but that would yield lower
compile-time performance on old compilers not implementing it
(e.g. GCC versions older than 7.0).

Fixes: af2c320190f3c731 "intel/fs: Implement GRF bank conflict mitigation pass."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104226
Reported-by: Józef Kucia <joseph.kucia@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

Revert "spirv: consider bitsize when handling OpSwitch cases"

This reverts commit 9702fac68e8bd07be8871f7925d7f9fb98da3699, which
hangs vulkancts and crucible on all platforms.

The patch is being reverted because it disables continuous integration
testing.  The patch from bug 104359 does not apply to master.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104359

radv: fix issue with multisample positions and interp_var_at_sample.

This fixes vmfaults seen on vega with:
dEQP-VK.pipeline.multisample_interpolation.sample_interpolate_at_single_sample_.128_128_1.samples_1

These were caused by the don't allocate cmask but it was just accidental.

The actual problem was the shader was trying to get the sample positions from
a buffer, but the buffer was never getting configured to contain them, as the
previous shader never needed them.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 1171b304f3 (radv: overhaul fragment shader sample positions.)
Signed-off-by: Dave Airlie <airlied@redhat.com>

docs: update calendar, add news item and link release notes for 17.3.1

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add sha256 checksums for 17.3.1

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit f66496d291881f1eaca2ee5d326367fb73537541)

docs: add release notes for 17.3.1

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 4f5e85e9e97de4ae6e3d779ff42bf392c4739234)

radv/gfx9: fix primitive topology when adjacency is used

Found by inspection.

Cc: 17.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

glsl: disable vec3 packing/splitting in tfb separate mode

This fixes a varying packing issue when using transform feedback in
GL_SEPARATE_ATTRIBS mode.  By time we get to linking, we already
know that the number of feedback attributes is under the
GL_MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS limit so packing isn't
as critical.  In fact, packing/splitting vec3 attributes can cause
trouble because splitting effectively creates another TFB output
which can exceed device limits.  So, disable vec3 packing when it's
not needed to avoid that issue.

Fixes the Piglit ext_transform_feedback-separate test on VMware
driver.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl: simply packing class comparison

Handle comparing the packing class using the same method as we do
for var->data.is_xfb_only

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl: document varying_matches::assign_locations() params and return value

And change *components to components[] as a reminder that it's an array.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl: remove some continue statements

In some cases, I think loop code is easier to read without continue
statements.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl: use bitwise operators in varying_matches::compute_packing_class()

The mix of bitwise operators with * and + to compute the packing_class
values was a little weird.  Just use bitwise ops instead.

v2: add assertion to make sure interpolation bits fit without collision,
per Timothy.  Basically, rewrite function to be simpler.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl: simplify loop in varying_matches::assign_locations()

The use of break/continue was kind of weird/confusing.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl: minor simplification in assign_varying_locations()

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl: make varying_matches::is_varying_packing_safe() const

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl: trivial comment fixes in lower_packed_varyings.cpp

Reviewed by: Timothy Arceri <tarceri@itsqueeze.com>

docs: update 17.3 and 18.0 cycles for the release calendar

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

spirv: Makefile.nir.am: include vtn_gather_types_c.py script in tarball dist

Fixes: bb1e6ff161c ("spirv: Add a prepass to set types on vtn_values")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

st/dri: allow direct YUYV import

Push this format to the pipe driver unchanged.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

spirv: consider bitsize when handling OpSwitch cases

When walking over all the cases in a OpSwitch, take in account the bitsize
of the literals to avoid getting wrong cases.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

drirc: set allow_glsl_cross_stage_interpolation_mismatch for more games

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Suggested-by: Darius Spitznagel <d.spitznagel@goodbytez.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104288
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

anv: disallow VK_REMAINING_ARRAY_LAYERS in vkCmdClearAttachments()

Vulkan spec doesn't specify that VK_REMAINING_ARRAY_LAYERS is allowed
in the passed VkClearRect struct.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nvc0/ir: change textureGrad to always use lane 0 as the tex origin

Thanks to Karol Herbst for the debugging / tracing work that led to this
change.

Move to using lane 0 as the "work" lane for the texture. It is unclear
why this helps, as that computation should be identical to doing it in
the "correct" lane with the properly adjusted quadops.

In order to be able to use the lane 0 result, we also have to ensure
that lane 0 contains the proper array/indirect/shadow values.

This applies to Fermi and Kepler. Maxwell+ may or may not need fixing,
but that lowering logic is separate.

Fixes KHR-GL45.texture_cube_map_array.sampling

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

broadcom/vc5: Add missing setting of the UIF XOR disable flag in textures.

Most piglit textures happened to work out by RGBW not changing in that
bit, but it did cause failures in RGBA16F fbo-generatemipmap-formats.

broadcom/vc5: Clean up the comment and code around level 0 UIF.

I wrote this early in driver development, and our UIF handling is much
better now.

broadcom/vc5: Simplify the tiling calculations.

The mb_tile_layout table was just the utile_w/h times two, so reuse the
utile code instead.

broadcom/vc5: Return the depth in all components of depth textures.

Apparently gallium's u_blitter wants depth from at least the .z component,
and other swizzling appears to apply on top of that.  Fixes
fbo-generatemipmap-formats failures with depth formats.

broadcom/vc5: Enable decompressing RGTC for desktop GL support.

This matches freedreno's behavior.

broadcom/vc5: Use u_transfer_helper for MSAA mappings.

broadcom/vc5: Start adding support for rendering to Z32F_S8X24_UINT.

There may be some more RCL work to be done (I think I need to split my Z/S
stores when doing separate stencil), but this gets piglit's "texwrap
GL_ARB_depth_buffer_float" working.

v2: Unwrap the z32f_wrapper before calling the helper, rather than having
    the helper have a callback.
v3: Rebase on Rob Clark's u_transfer_helper instead

freedreno: add debug flag to force high priority context

Mainly for testing, FD_MESA_DEBUG=hiprio will force high priority
contexts.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: context priority support

For devices (and kernels) which support different priority ringbuffers,
expose context priority support.

Signed-off-by: Rob Clark <robdclark@gmail.com>

gallium: plumb context priority through to driver

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>

intel/compiler/gen10: Disable push constants.

We still have gpu hangs on Cannonlake when using push constants, so
disable them for now until we have a proper fix for these hangs.

v2: Add warning message when creating context too.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

radv: properly load unused gl_LocalInvocationID/gl_WorkGroupID components

F1 2017 looks good now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: do not add extra SGPR when push constants are not used

This is not because the vertex stage needs some push constants
that other stages need them too. This should reduce the number
of loaded SGPRs in some situations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: change the needs_push_constants logic

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: store pipeline stages that need push constants

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: remove one useless check in ac_nir_shader_info_pass()

pipeline->layout can't be NULL now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: remove one useless check in radv_flush_constants()

pipeline->layout can't be NULL now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: add assertions to make sure pipeline layout objects are valid

The spec requires it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: create pipeline layout objects for all meta operations

They are dummy objects but the spec requires layout to not be
NULL, this just makes sure we are creating valid pipeline layout
objects. This will allow us to remove some useless checks.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: Use a sort for rebuilding the sparse buffer bo list.

It uses slightly more memory (though still bounded by the number
of mapped ranges), but gives less quadratic behavior.

Cuts 4 minutes from the runtime of the CTS *.sparse.* tests.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

freedreno/ir3: handle VTXID_BASE for indirect draws

Need to do some gymnastics to copy the parameter from the indirect
parameters buffer to uniform so shader sees the correct base-vertex-id.

Fixes ./bin/arb_draw_indirect-vertexid on a5xx and probably a4xx too.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: add ctx->mem_to_mem()

For dealing with indirect-draw + gl_VertexID, we'll introduce another
case where we need to use CP_MEM_TO_MEM.  Rather than adding more
if(a5xx)/else make this a ctx vfunc.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: use vertex_id_zero_base

Cmdstream traces from blob make it clear that the blob driver dev's
*think* a5xx has a real (non-zero-based) vtxid.  But reality claims
differently.

Fixes ./bin/gl-3.2-basevertex-vertexid and probably others.

This means draw-indirect is going to need some gymnastics to copy
base-vertex into uniform.  (a4xx probably needs that too.)

Signed-off-by: Rob Clark <robdclark@gmail.com>

r600: clear compressed flags in image state on unbind.

If we aren't binding an image, clear the compressed flags.

This fixes a segfault seen with an apitrace.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104331
Signed-off-by: Dave Airlie <airlied@redhat.com>

swr: Account for index_bias in offsets

When calculating buffer offsets for client buffers account for info.index_bias.

Fixes the follow piglit tests:
arb_draw_elements_base_vertex-drawelements-user_varrays
arb_draw_elements_base_vertex-negative-index-user_varrays

Reviewed-By: Bruce Cherniak <bruce.cherniak@intel.com>

r600: only reported tgsi ir compute support on evergreen+

This fixes a crash on r600/r700.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Advertise sync fd import and export.

Passes dEQP-VK.*.sync_fd.*

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Implement sync file import/export for fences & semaphores.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv/amdgpu: wrap sync fd import/export.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: fix lds store for patch outputs.

This wasn't calculating the correct value, this along with
a nir patch fixes a regression in:
dEQP-VK.tessellation.shader_input_output.barrier

Fixes: 043d14db30a (ac/nir: don't write tcs outputs to LDS that aren't read back.)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

nir/linking: always set the used_across_stages/outputs_read bits

If we don't remap and output this code would trample the outputs
read bits.

This fixes a regression in
dEQP-VK.tessellation.shader_input_output.barrier

Fixes: 1c9c42d16b4c (nir: add varying component packing helpers)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

spirv: Relax the validation conditions of OpSelect

The Talos Principle contains shaders with an OpSelect between two
vectors where the condition is a scalar boolean.  This is technically
against the spec bout nir_builder gracefully handles it by splatting
out the condition to all the channels.  So long as the condition is a
boolean, just emit a warning instead of failing.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104246