mesa.git
4 years agogallivm: fix perspective enable if usage_mask doesn't have 0 bit set
Dave Airlie [Tue, 3 Dec 2019 03:42:03 +0000 (13:42 +1000)]
gallivm: fix perspective enable if usage_mask doesn't have 0 bit set

The current code looks like a typo, and fails if the usage_mask
is for a y/z enabled input.

Fixes piglit ext_transform_feedback-immediate-reuse-index-buffer
with llvmpipe/nir

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
4 years agogallivm: fix transpose for when first channel isn't created
Dave Airlie [Tue, 3 Dec 2019 03:41:56 +0000 (13:41 +1000)]
gallivm: fix transpose for when first channel isn't created

The previous fix worked when the second channel wasn't exposed, but
a couple of piglit tests have inputs with just the y/z chans, no x/w.

Partly Fixes piglit ext_transform_feedback-immediate-reuse-index-buffer
with llvmpipe/nir

Fixes: 5363cda52b84 ("gallivm: add swizzle support where one channel isn't defined.")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
4 years agollvmpipe/nir: handle texcoord requirements
Dave Airlie [Fri, 6 Dec 2019 04:16:52 +0000 (14:16 +1000)]
llvmpipe/nir: handle texcoord requirements

Switch to using texcoord intrinsic support.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
4 years agofreedreno/a6xx: Silence warning for unused perf counters
Kristian H. Kristensen [Wed, 11 Dec 2019 17:33:56 +0000 (09:33 -0800)]
freedreno/a6xx: Silence warning for unused perf counters

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno/a6xx: Convert some tile setup to OUT_REG()
Kristian H. Kristensen [Tue, 10 Dec 2019 03:45:31 +0000 (19:45 -0800)]
freedreno/a6xx: Convert some tile setup to OUT_REG()

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno/a6xx: Convert gmem blits to OUT_REG()
Kristian H. Kristensen [Tue, 10 Dec 2019 03:31:26 +0000 (19:31 -0800)]
freedreno/a6xx: Convert gmem blits to OUT_REG()

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno/a6xx: Convert VSC pipe setup to OUT_REG()
Kristian H. Kristensen [Tue, 10 Dec 2019 03:27:38 +0000 (19:27 -0800)]
freedreno/a6xx: Convert VSC pipe setup to OUT_REG()

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno/a6xx: Convert emit_zs() to OUT_REG()
Kristian H. Kristensen [Tue, 10 Dec 2019 03:25:14 +0000 (19:25 -0800)]
freedreno/a6xx: Convert emit_zs() to OUT_REG()

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno/a6xx: Convert emit_mrt() to OUT_REG()
Kristian H. Kristensen [Tue, 10 Dec 2019 03:24:19 +0000 (19:24 -0800)]
freedreno/a6xx: Convert emit_mrt() to OUT_REG()

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno/a6xx: Include fd6_pack.h in a few files
Kristian H. Kristensen [Tue, 10 Dec 2019 03:22:04 +0000 (19:22 -0800)]
freedreno/a6xx: Include fd6_pack.h in a few files

Including non-functional changes to get the value from the fd_reg_pair
in places.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno/a6xx: Drop stale include
Kristian H. Kristensen [Tue, 10 Dec 2019 03:08:31 +0000 (19:08 -0800)]
freedreno/a6xx: Drop stale include

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno/registers: Add 64 bit address registers
Kristian H. Kristensen [Sat, 9 Nov 2019 08:57:56 +0000 (00:57 -0800)]
freedreno/registers: Add 64 bit address registers

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno: New struct packing macros
Kristian H. Kristensen [Fri, 8 Nov 2019 04:03:21 +0000 (20:03 -0800)]
freedreno: New struct packing macros

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno/registers: Remove duplicate register definitions
Kristian H. Kristensen [Wed, 23 Oct 2019 23:55:43 +0000 (16:55 -0700)]
freedreno/registers: Remove duplicate register definitions

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agodocs: remove mailing list as way of submitting patches
Timothy Arceri [Tue, 10 Dec 2019 22:55:03 +0000 (09:55 +1100)]
docs: remove mailing list as way of submitting patches

All developers now use gitlab, don't confuse newcomers by suggesting
they might use the mailing list. We want everyone to use gitlab so
that patches get run through basic CI before they are merged.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
4 years agoanv: Bump the advertised patch version to 129
Jason Ekstrand [Tue, 10 Dec 2019 20:26:07 +0000 (14:26 -0600)]
anv: Bump the advertised patch version to 129

We've been keeping up with the spec updates.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agoanv: Unconditionally advertise Vulkan 1.1
Jason Ekstrand [Tue, 10 Dec 2019 20:22:25 +0000 (14:22 -0600)]
anv: Unconditionally advertise Vulkan 1.1

Vulkan 1.1 requires VK_KHR_external_fence which requires syncobj support
to be actually usable.  However, it doesn't strictly require that we
support any external handle types.  We should be able to advertise 1.1
even on old kernels that don't have syncobj support.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agoanv: Flush the queue on DeviceWaitIdle
Jason Ekstrand [Wed, 11 Dec 2019 04:55:58 +0000 (22:55 -0600)]
anv: Flush the queue on DeviceWaitIdle

When we have syncobj_wait, we can trust in WAIT_FOR_SUBMIT but when we
don't, we only have BO waits and those aren't quite as nice.  This
commit adds a flag to _anv_queue_submit to wait for the queue to drain
before returning.  This gives us the behavior we need to implement
DeviceWaitIdle.

Fixes: 246261f0add "anv: prepare the driver for delayed submissions"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agonir/tests: MSVC build fix
Karol Herbst [Wed, 11 Dec 2019 16:52:17 +0000 (17:52 +0100)]
nir/tests: MSVC build fix

Fixes: 11f736a6f9c "nir/tests: add serializer tests"
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
4 years agoswr/rasterizer: Add tessellator implementation to the rasterizer
Jan Zielinski [Wed, 4 Dec 2019 12:10:18 +0000 (13:10 +0100)]
swr/rasterizer: Add tessellator implementation to the rasterizer

This is initial commit on the way to implement ARB_tessellation_shader
extension in OpenSWR. It introduces tessellator implementation
taken from Microsoft GitHub (published under MIT license):

https://github.com/microsoft/DirectX-Specs/blob/master/d3d/archive/images/d3d11/tessellator.cpp
https://github.com/microsoft/DirectX-Specs/blob/master/d3d/archive/images/d3d11/tessellator.hpp

It also adds some glue code that connects the tessellator
to the internals of SWR rasterizer.

Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviwed-by: Alok Hota <alok.hota@intel.com>
4 years agogitlab-ci: set RADV_DEBUG=checkir for RADV test jobs
Samuel Pitoiset [Fri, 6 Dec 2019 16:07:35 +0000 (17:07 +0100)]
gitlab-ci: set RADV_DEBUG=checkir for RADV test jobs

This is used to validate if the driver emits correct LLVM IR.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agointel: add mi_builder_test for gen12
Eric Engestrom [Tue, 10 Dec 2019 16:09:36 +0000 (16:09 +0000)]
intel: add mi_builder_test for gen12

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agogitlab-ci: Use lavacli from packages
Rohan Garg [Thu, 5 Dec 2019 15:35:08 +0000 (16:35 +0100)]
gitlab-ci: Use lavacli from packages

lavacli 0.9.8 is now available in Debian Testing.
Ref: https://tracker.debian.org/news/1066828/lavacli-098-1-migrated-to-testing/
Fixes: 555c0de ("gitlab-ci: Move LAVA-related files into top-level ci dir")
Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
4 years agolima/ppir: enable lower_fdph
Erico Nunes [Tue, 10 Dec 2019 18:08:29 +0000 (19:08 +0100)]
lima/ppir: enable lower_fdph

Otherwise we may lower some fdot to fdph which is not implemented in pp.

Fixes #2126

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
4 years agonir/tests: add serializer tests
Karol Herbst [Mon, 2 Dec 2019 21:41:33 +0000 (22:41 +0100)]
nir/tests: add serializer tests

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
4 years agonir/serialize: fix vec8 and vec16
Karol Herbst [Mon, 2 Dec 2019 14:22:49 +0000 (15:22 +0100)]
nir/serialize: fix vec8 and vec16

Nir serializes uses nir_ssa_alu_instr_src_components in a few places to
determine how many components a src has, but that's not what this function
returns. It simply returns how many channels are used, which is still fine
for most of the code.

This was breaking code like this:

vec16 32 ssa_1 = intrinsic load_global
vec1  32 ssa_2 = fmax ssa_1.a, ssa_2.b

v2: make the 16bit encoding work for identify swizzles again

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
4 years agoradv: Fix RGBX Android<->Vulkan format correspondence.
Bas Nieuwenhuizen [Tue, 10 Dec 2019 15:53:56 +0000 (16:53 +0100)]
radv: Fix RGBX Android<->Vulkan format correspondence.

This is correct per the Vulkan spec format equivalence table.

Fixes: f36b52740a0 "radv/android: Add android hardware buffer queries."
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agopanfrost: Add PAN_MESA_DEBUG=sync
Tomeu Vizoso [Mon, 9 Dec 2019 07:39:59 +0000 (08:39 +0100)]
panfrost: Add PAN_MESA_DEBUG=sync

Sometimes it's useful to get information about GPU faults in the
console, so it's synchronized with other messages.

This commit will cause Mesa to wait for completion and check if there
are any faults raised by the GPU.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
4 years agoiris: Create smaller program keys without legacy features
Kenneth Graunke [Mon, 9 Dec 2019 04:25:42 +0000 (20:25 -0800)]
iris: Create smaller program keys without legacy features

A lot of the brw_*_prog_key fields are for emulating features on legacy
hardware that iris doesn't support.  In particular, all of the texture
swizzle fields take up a lot of space.  These dead fields make hashing
the shader keys more expensive than it ought to be.

We introduce iris-specific keys with only the information we need, and
translate them to brw keys when actually compiling new variants.  This
way, key comparisons can use the small keys.  The size reductions are:

   VS:  328 bytes ->  8 bytes
   TCS: 312 bytes -> 24 bytes
   TES: 304 bytes -> 24 bytes
   GS:  284 bytes ->  8 bytes
   FS:  304 bytes -> 16 bytes
   CS:  280 bytes ->  4 bytes

Scores for the Piglit drawoverhead microbenchmark case with a shader
program change improve by roughly 30%.

Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agocompiler/spirv: Fix uses of gnu struct = {} extension
Pierre Moreau [Wed, 27 Nov 2019 19:50:12 +0000 (20:50 +0100)]
compiler/spirv: Fix uses of gnu struct = {} extension

Fixes: a24d6fbae60 ("meson: Add -Werror=gnu-empty-initializer to MSVC compat args")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
4 years agoutil/u_thread: Restrict u_thread_get_time_nano on macOS.
Vinson Lee [Tue, 10 Dec 2019 07:09:58 +0000 (23:09 -0800)]
util/u_thread: Restrict u_thread_get_time_nano on macOS.

macOS does not have pthread_getcpuclockid.

src/util/u_thread.h:156:4: error: implicit declaration of function 'pthread_getcpuclockid' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
   pthread_getcpuclockid(thread, &cid);
   ^

Fixes: 4913215d145e ("util/u_thread: don't restrict u_thread_get_time_nano() to __linux__")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2171
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Acked-by: Eric Engestrom <eric@engestrom.ch>
4 years agotu: Move UBWC layout into fdl6_layout() and use that function.
Eric Anholt [Tue, 26 Nov 2019 20:29:19 +0000 (12:29 -0800)]
tu: Move UBWC layout into fdl6_layout() and use that function.

This gets us shared non-UBWC layout code between gallium and turnip.
Until I fix up the rest of gallium to handle UBWC mipmapping, we do the
single-level UBWC setup in gallium as a fixup after layout.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno: Switch the 16-bit workaround to match what turnip does.
Eric Anholt [Tue, 26 Nov 2019 23:25:29 +0000 (15:25 -0800)]
freedreno: Switch the 16-bit workaround to match what turnip does.

Prevents regressions on argb1555 and rgb565 when making turnip use
freedreno's layout.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno: Move a6xx's setup_slices() to a shareable helper function.
Eric Anholt [Tue, 26 Nov 2019 20:02:34 +0000 (12:02 -0800)]
freedreno: Move a6xx's setup_slices() to a shareable helper function.

We pass in all the parameters for setting up the layout, though freedreno
still sets a few of them up early (since it uses layout helpers in making
some decisions about the layout setup parameters that will be cleaned up
once krh's blitter work lands).

4 years agotu: Move our image layout into a freedreno_layout struct.
Eric Anholt [Tue, 26 Nov 2019 18:56:57 +0000 (10:56 -0800)]
tu: Move our image layout into a freedreno_layout struct.

This lets us start using some of the fdl_* helpers and have more obviously
matching code between gallium and turnip.  We can't yet use the fdl_* UBWC
helpers, since the gallium driver doesn't do UBWC mipmaps (which I'm
working on in another branch).

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno: Move UBWC layout into a slices array like the non-UBWC slices.
Eric Anholt [Mon, 25 Nov 2019 19:23:03 +0000 (11:23 -0800)]
freedreno: Move UBWC layout into a slices array like the non-UBWC slices.

This is a little refactor in preparation for UBWC mipmapping support.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno: Refactor the UBWC flags registers emission.
Eric Anholt [Fri, 22 Nov 2019 00:20:11 +0000 (16:20 -0800)]
freedreno: Refactor the UBWC flags registers emission.

It's the same logic for each of these being emitted, and I was about to
change the rsc->layout.* for UBWC.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agofreedreno: Drop the extra offset field for mipmap slices.
Eric Anholt [Thu, 21 Nov 2019 22:53:58 +0000 (14:53 -0800)]
freedreno: Drop the extra offset field for mipmap slices.

We can just bake the UBWC-goes-first delta into the slices at setup time.
I did have to fix up the resource shadowing swap path to swap the slice
fields, as it was missing and regressed the format reinterpets otherwise.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
4 years agointel/decoder: Make get_state_size take a full 64-bit address and a base
Kenneth Graunke [Wed, 2 Oct 2019 19:09:33 +0000 (15:09 -0400)]
intel/decoder: Make get_state_size take a full 64-bit address and a base

i965 wants to use an offset from a base because everything is in a
single buffer whose address may be relocated, and all base addresses
are set to the start of that buffer.

iris wants to use a full 64-bit address, because state lives in separate
buffers which may be in the shader, surface, and dynamic memory zones,
where addresses grow downward from the top of a 4GB zone,  So it's very
possible for a 32-bit offset to exist relative to multiple bases,
leading to the wrong state size.

4 years agoiris: INTEL performance query implementation
Dongwon Kim [Tue, 15 Oct 2019 19:43:02 +0000 (12:43 -0700)]
iris: INTEL performance query implementation

low-level implementation of INTEL-performance-query APIs in
Intel iris driver. Most of functions and procedures defined here
are adopted from i965 driver (brw_performance_query.c)

v2: - replace genX_init_performance_query with
      iris_init_perfquery_functions which is gen's version agnositic
    - general code clean-up

v3: include gen_perf_gens.h as some of defines were moved to this new
    header file

v4: - checking for kernel 4.13+ won't be needed here as Iris won't be
      loaded anyway without DRM_SYNCOBJ that is enabled after Kernel
      4.13.

    - checking whether gen < 8 or is_cherryview won't be required as
      well because those cases are screened in iris_screen_create.

v5: remove genX(init_performance_query)

v6: - remove oa_metrics_kernel_support as iris works only with kernel
    4.18 and newer.

    - use perf functions defined in separate file, iris_perf.h/c

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agoiris: separating out common perf code
Mark Janes [Fri, 22 Nov 2019 21:46:22 +0000 (13:46 -0800)]
iris: separating out common perf code

The configuration of the gen_perf vtable will be the same for
INTEL_performance_query and AMD_performance_monitor.
Initialize the table in a single routine that can be called from both
implementations.

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agogallium: enable INTEL_PERFORMANCE_QUERY
Dongwon Kim [Tue, 15 Oct 2019 19:43:04 +0000 (12:43 -0700)]
gallium: enable INTEL_PERFORMANCE_QUERY

new state tracker APIs added for INTEL_performance_query
This extension is enabled if all vendor specific functions for it
exist.

v2: add st_cb_perfquery.* to the list of sources in Makefile
v3: minor code clean-up
v4: - add driver hooks for intel-performance-query apis
    - add PIPE level performance counter and type enums that
      match to OpenGL enums
    - do conversion of pipe_perf_counter_type and
      pipe_perf_counter_data_type enums to GL defines in state_tracker

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agomeson/broadcom: libbroadcom_cle also needs zlib
Dylan Baker [Tue, 10 Dec 2019 19:15:37 +0000 (11:15 -0800)]
meson/broadcom: libbroadcom_cle also needs zlib

Fixes: 1ae8018a6af81eec4832a57d9d0346aa3dd98d28
       ("meson: Add support for the vc4 driver.")
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agoanv: Enable Gen11 Color/Z write merging optimization
Kenneth Graunke [Tue, 3 Dec 2019 01:30:06 +0000 (17:30 -0800)]
anv: Enable Gen11 Color/Z write merging optimization

TCCNTLREG contains additional L3 cache write merging optimizations.

The default value on my system appears to be:
- URB Partial Write Merging (bit 0)
- L3 Data Partial Write Merging (bit 2)
- TC Disable (bit 3)

Windows drivers appear to set bit 1 as well to enable "Color/Z Partial
Write Merging".  This should solve an issue we were seeing where MRT
benchmarks were using substantially more bandwidth than they ought.
However, we have not observed it to cause measurable FPS gains.

It is unclear whether we should be setting bit 0 or bit 3, so for now
we leave those at the hardware default value.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agoiris: Enable Gen11 Color/Z write merging optimization
Kenneth Graunke [Sat, 31 Aug 2019 00:19:46 +0000 (17:19 -0700)]
iris: Enable Gen11 Color/Z write merging optimization

TCCNTLREG contains additional L3 cache write merging optimizations.

The default value on my system appears to be:
- URB Partial Write Merging (bit 0)
- L3 Data Partial Write Merging (bit 2)
- TC Disable (bit 3)

Windows drivers appear to set bit 1 as well to enable "Color/Z Partial
Write Merging".  This should solve an issue we were seeing where MRT
benchmarks were using substantially more bandwidth than they ought.
However, we have not observed it to cause measurable FPS gains.

It is unclear whether we should be setting bit 0 or bit 3, so for now
we leave those at the hardware default value.

Improves performance in Manhattan 3.0 by 6% on ICL 8x8 at a fixed
frequency, according to Felix Degrood.  I didn't see any improvements
at out-of-the-box power management settings, however.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agointel/genxml: Add a partial TCCNTLREG definition
Kenneth Graunke [Mon, 2 Dec 2019 07:01:19 +0000 (23:01 -0800)]
intel/genxml: Add a partial TCCNTLREG definition

TCCNTLREG contains additional cache programming settings.  In
particular, there are several write combining controls we'd like to use.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agoutil: Detect use-after-destroy in simple_mtx
Kenneth Graunke [Mon, 21 Oct 2019 21:51:13 +0000 (14:51 -0700)]
util: Detect use-after-destroy in simple_mtx

This makes simple_mtx_destroy set the counter to an invalid canary
value and then makes lock/unlock assert that the value is legal.

That way, calling lock/unlock after destroy will assert fail,
rather than deadlocking or potentially even working.

This has caught real deadlocks in dEQP multithreaded tests (in st/mesa
shader variant zombie list handling), which have since been fixed.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
4 years agofreedreno/a6xx: enable LRZ by default
Rob Clark [Tue, 10 Dec 2019 22:41:46 +0000 (14:41 -0800)]
freedreno/a6xx: enable LRZ by default

Now that dEQP should be happy, lets flip the switch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
4 years agofreedreno/a6xx: fix LRZ logic
Rob Clark [Fri, 6 Dec 2019 19:34:39 +0000 (11:34 -0800)]
freedreno/a6xx: fix LRZ logic

In particular, we need to invalidate the LRZ state when we cannot be
confident in what the Z state would be during rendering:

1) depth test modes not supported by LRZ
2) stencil test, which would require full rasterization and stencil
   test in the binning pass (whereas LRZ normally just needs to
   determine the min and max z value in an 8x8 quad)

Signed-off-by: Rob Clark <robdclark@chromium.org>
4 years agofreedreno/a6xx: fix LRZ layout
Rob Clark [Tue, 10 Dec 2019 22:27:20 +0000 (14:27 -0800)]
freedreno/a6xx: fix LRZ layout

Signed-off-by: Rob Clark <robdclark@chromium.org>
4 years agofreedreno/a5xx+a6xx: split LRZ layout to per-gen
Rob Clark [Tue, 10 Dec 2019 22:24:59 +0000 (14:24 -0800)]
freedreno/a5xx+a6xx: split LRZ layout to per-gen

Seems to be a bit different for a6xx, so let's split this out.

Signed-off-by: Rob Clark <robdclark@chromium.org>
4 years agofreedreno/a6xx: disable LRZ when blending
Rob Clark [Thu, 5 Dec 2019 19:54:33 +0000 (11:54 -0800)]
freedreno/a6xx: disable LRZ when blending

Signed-off-by: Rob Clark <robdclark@chromium.org>
4 years agoradeonsi: don't rely on CLEAR_STATE to set PA_SC_GENERIC_SCISSOR_*
Marek Olšák [Tue, 10 Dec 2019 00:27:26 +0000 (19:27 -0500)]
radeonsi: don't rely on CLEAR_STATE to set PA_SC_GENERIC_SCISSOR_*

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
4 years agoradeonsi/gfx10: simplify the tess_turns_off_ngg condition
Marek Olšák [Tue, 12 Nov 2019 22:10:05 +0000 (17:10 -0500)]
radeonsi/gfx10: simplify the tess_turns_off_ngg condition

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
4 years agoradeonsi/gfx10: disable vertex grouping
Marek Olšák [Mon, 28 Oct 2019 20:37:53 +0000 (16:37 -0400)]
radeonsi/gfx10: disable vertex grouping

based on PAL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
4 years agoradeonsi: enable NIR by default and document GL 4.6 support
Marek Olšák [Sat, 26 Oct 2019 03:32:18 +0000 (23:32 -0400)]
radeonsi: enable NIR by default and document GL 4.6 support

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
4 years agost/dri: assume external consumers of back buffers can write to the buffers
Marek Olšák [Thu, 17 Oct 2019 20:46:06 +0000 (16:46 -0400)]
st/dri: assume external consumers of back buffers can write to the buffers

This was reverted needlessly because if was part of another series.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-By: Tapani Pälli <tapani.palli@intel.com>
4 years agoANV: Stop advertising smoothLines support on gen10+
Jason Ekstrand [Fri, 6 Dec 2019 21:20:35 +0000 (15:20 -0600)]
ANV: Stop advertising smoothLines support on gen10+

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
4 years agomeson/broadcom: libbroadcom_cle needs expat headers
Dylan Baker [Tue, 10 Dec 2019 18:19:04 +0000 (10:19 -0800)]
meson/broadcom: libbroadcom_cle needs expat headers

Fixes: 1ae8018a6af81eec4832a57d9d0346aa3dd98d28
       ("meson: Add support for the vc4 driver.")
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agoanv: fix incorrect VMA alignment for CCS main surfaces
Lionel Landwerlin [Tue, 10 Dec 2019 11:49:49 +0000 (03:49 -0800)]
anv: fix incorrect VMA alignment for CCS main surfaces

Maybe finer way of dealing with this requirement would be to increase
the number of pdevice->memory.types[] to add a category for special
alignment cases.

Meanwhile this fixes the problem of CCS surface alignment and it's
probably not going to cause issues given the size of our address
space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 6af8a4acc4a4 ("anv: Add aux-map translation for gen12+")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agoanv: fix missing gen12 handling
Lionel Landwerlin [Tue, 10 Dec 2019 11:49:16 +0000 (03:49 -0800)]
anv: fix missing gen12 handling

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 181be14d4303 ("anv: Build for gen12")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agodocs: reword a bit and list HTTPS before FTP
Eric Engestrom [Fri, 22 Nov 2019 14:36:02 +0000 (14:36 +0000)]
docs: reword a bit and list HTTPS before FTP

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
4 years agomeson: drop `intel_` prefix on imgui_core
Eric Engestrom [Thu, 21 Nov 2019 23:13:01 +0000 (23:13 +0000)]
meson: drop `intel_` prefix on imgui_core

Again, no real effect, just the name of a temporary build file.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
4 years agomeson: drop duplicate `lib` prefix on libiris_gen*
Eric Engestrom [Thu, 21 Nov 2019 23:11:07 +0000 (23:11 +0000)]
meson: drop duplicate `lib` prefix on libiris_gen*

This has no real effect other than the names of the temporary files in
the build folder.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
4 years agoradv: implement VK_KHR_separate_depth_stencil_layouts
Samuel Pitoiset [Mon, 9 Dec 2019 12:56:24 +0000 (13:56 +0100)]
radv: implement VK_KHR_separate_depth_stencil_layouts

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: initialize HTILE for separate depth/stencil aspects
Samuel Pitoiset [Wed, 6 Nov 2019 14:49:10 +0000 (15:49 +0100)]
radv: initialize HTILE for separate depth/stencil aspects

It either clears the whole HTILE buffer or part of it depending
on the HTILE mask parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: do not init HTILE as compressed state when dst layout allows it
Samuel Pitoiset [Wed, 6 Nov 2019 15:31:56 +0000 (16:31 +0100)]
radv: do not init HTILE as compressed state when dst layout allows it

I don't think this makes much differences and a potential clear
following the initialization will overwrite HTILE anyways.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: synchronize after performing a separate depth/stencil fast clears
Samuel Pitoiset [Tue, 26 Nov 2019 15:55:02 +0000 (16:55 +0100)]
radv: synchronize after performing a separate depth/stencil fast clears

For depth+stencil images, the driver might use an optimized path
if only one aspect is cleared. It either clears the depth or the
stencil part of HTILE. Because the two separate aspects might use
the same HTILE memory we have to synchronize.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agogitlab-ci: Don't exclude any piglit quick_shader tests
Michel Dänzer [Fri, 6 Dec 2019 11:02:13 +0000 (12:02 +0100)]
gitlab-ci: Don't exclude any piglit quick_shader tests

Now that we're running these with process isolation enabled, their
results will hopefully be stable.

Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agogallivm: add TGSI bit arithmetic opcodes support
Krzysztof Raszkowski [Thu, 5 Dec 2019 17:01:08 +0000 (18:01 +0100)]
gallivm: add TGSI bit arithmetic opcodes support

Add TGSI_OPCODE_BFI, TGSI_OPCODE_POPC, TGSI_OPCODE_LSB,
TGSI_OPCODE_IMSB, TGSI_OPCODE_UMSB, TGSI_OPCODE_IBFE,
TGSI_OPCODE_UBFE, TGSI_OPCODE_BREV support.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
4 years agoradv: fix possibly wrong PA_SC_AA_CONFIG value for conservative rast
Samuel Pitoiset [Fri, 6 Dec 2019 11:19:11 +0000 (12:19 +0100)]
radv: fix possibly wrong PA_SC_AA_CONFIG value for conservative rast

PA_SC_AA_CONFIG might be updated when conversative rasterization is
enabled. Because the driver only re-emits the multisample state if
the number of samples is different, that register value might not
be updated correctly.

Found by inspection, doesn't fix anything known.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: move emission of two PA_SC_* registers to the pipeline CS
Samuel Pitoiset [Fri, 6 Dec 2019 11:12:38 +0000 (12:12 +0100)]
radv: move emission of two PA_SC_* registers to the pipeline CS

They don't have to be updated dynamically.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agost/dri: use st->flush callback to flush the backbuffer
Pierre-Eric Pelloux-Prayer [Wed, 27 Nov 2019 10:25:40 +0000 (11:25 +0100)]
st/dri: use st->flush callback to flush the backbuffer

Previously the flush was done before the call to st->flush but
could lead to problems as FLUSH_VERTICES could push some work
that would change the backbuffer (or modify it).

With this commit, all the backbuffer flushing code is executed
right before the call to st_flush.

Closes: https://gitlab.freedesktop.org/drm/amd/issues/842
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=205049

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agost/mesa: add a notify_before_flush callback param to flush
Pierre-Eric Pelloux-Prayer [Wed, 27 Nov 2019 10:22:11 +0000 (11:22 +0100)]
st/mesa: add a notify_before_flush callback param to flush

The new callback is called right before the flush is done to allow
users of st->flush to do some work after all the previous work has
been flushed.

This will be used by dri_flush in the next commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agoradeonsi: dcc dirty flag
Pierre-Eric Pelloux-Prayer [Fri, 22 Nov 2019 14:42:46 +0000 (15:42 +0100)]
radeonsi: dcc dirty flag

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agoradeonsi: fix multi plane buffers creation
Pierre-Eric Pelloux-Prayer [Mon, 9 Dec 2019 08:48:37 +0000 (09:48 +0100)]
radeonsi: fix multi plane buffers creation

When using 3 planes, the sequence produces this chain:
  plane0 -> plane2
This commit fixes this to produce:
  plane0 -> plane1 -> plane2

Fixes: 86e60bc2659 ("radeonsi: remove si_vid_join_surfaces and use combined planar allocations")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2193
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agoradeonsi: use gfx9.surf_offset to compute texture offset
Pierre-Eric Pelloux-Prayer [Fri, 6 Dec 2019 20:35:38 +0000 (21:35 +0100)]
radeonsi: use gfx9.surf_offset to compute texture offset

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2177
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agoradeonsi: use compute shader for clear 12-byte buffer
Sonny Jiang [Fri, 29 Nov 2019 23:04:54 +0000 (18:04 -0500)]
radeonsi: use compute shader for clear 12-byte buffer

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agost/mesa: release the draw shader properly to fix driver crashes (iris)
Marek Olšák [Tue, 10 Dec 2019 03:35:57 +0000 (22:35 -0500)]
st/mesa: release the draw shader properly to fix driver crashes (iris)

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agodraw, st/mesa: generate TGSI for ffvp/ARB_vp if draw lacks LLVM
Marek Olšák [Wed, 4 Dec 2019 22:27:13 +0000 (17:27 -0500)]
draw, st/mesa: generate TGSI for ffvp/ARB_vp if draw lacks LLVM

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
4 years agost/mesa: don't generate VS TGSI if NIR is enabled
Marek Olšák [Thu, 28 Nov 2019 03:47:56 +0000 (22:47 -0500)]
st/mesa: don't generate VS TGSI if NIR is enabled

it's no longer needed

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agost/mesa: remove struct st_vp_variant in favor of st_common_variant
Marek Olšák [Thu, 28 Nov 2019 03:37:35 +0000 (22:37 -0500)]
st/mesa: remove struct st_vp_variant in favor of st_common_variant

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agost/mesa: remove st_vp_variant::num_inputs
Marek Olšák [Thu, 28 Nov 2019 03:30:22 +0000 (22:30 -0500)]
st/mesa: remove st_vp_variant::num_inputs

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agost/mesa: use a separate VS variant for the draw module
Marek Olšák [Thu, 28 Nov 2019 03:25:00 +0000 (22:25 -0500)]
st/mesa: use a separate VS variant for the draw module

instead of keeping the IR indefinitely in st_vp_variant.

This trivially fixes Selection/Feedback/RasterPos for NIR.

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agost/mesa: support shader images for Selection/Feedback/RasterPos
Marek Olšák [Wed, 27 Nov 2019 23:01:15 +0000 (18:01 -0500)]
st/mesa: support shader images for Selection/Feedback/RasterPos

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agost/mesa: support SSBOs for Selection/Feedback/RasterPos
Marek Olšák [Wed, 27 Nov 2019 22:26:51 +0000 (17:26 -0500)]
st/mesa: support SSBOs for Selection/Feedback/RasterPos

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agost/mesa: support samplers for Selection/Feedback/RasterPos
Marek Olšák [Wed, 27 Nov 2019 20:10:33 +0000 (15:10 -0500)]
st/mesa: support samplers for Selection/Feedback/RasterPos

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agost/mesa: save currently bound vertex samplers and sampler views in st_context
Marek Olšák [Wed, 27 Nov 2019 20:10:27 +0000 (15:10 -0500)]
st/mesa: save currently bound vertex samplers and sampler views in st_context

for st_draw_feedback.c

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agost/mesa: support UBOs for Selection/Feedback/RasterPos
Marek Olšák [Wed, 27 Nov 2019 01:55:13 +0000 (20:55 -0500)]
st/mesa: support UBOs for Selection/Feedback/RasterPos

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agogallivm: implement LOAD with CONSTBUF but don't enable it for llvmpipe
Marek Olšák [Wed, 27 Nov 2019 22:10:45 +0000 (17:10 -0500)]
gallivm: implement LOAD with CONSTBUF but don't enable it for llvmpipe

This is already used in st_draw_feedback.c, because it uses shaders
generated for drivers.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
4 years agollvmpipe: implement TEX_LZ and TXF_LZ opcodes
Marek Olšák [Wed, 27 Nov 2019 20:04:14 +0000 (15:04 -0500)]
llvmpipe: implement TEX_LZ and TXF_LZ opcodes

gallivm receives these opcodes anyway because st_draw_feedback.c uses
shaders that were assembled for drivers, not llvmpipe.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
4 years agodrirc: set allow_higher_compat_version for Faster Than Light
Gurchetan Singh [Thu, 5 Dec 2019 02:03:19 +0000 (18:03 -0800)]
drirc: set allow_higher_compat_version for Faster Than Light

With 781a78 ("mesa: enable ARB_direct_state_access in compat for
GL3.1+), it's possible to have DSA with GL3.1+.

FTL creates a GL3.1 compat context, but fails the
_mesa_has_geometry_shaders(..) check in frame_buffer_texture.

Bump the compat version to pass the check.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agoutil/atomic: Fix p_atomic_add for unlocked and msvc paths
Roland Scheidegger [Mon, 9 Dec 2019 17:49:13 +0000 (18:49 +0100)]
util/atomic: Fix p_atomic_add for unlocked and msvc paths

Braces mismatch (flagged by CI, untested).

Fixes: 385d13f26d2 "util/atomic: Add a _return variant of p_atomic_add"
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agofreedreno: Track the set of UBOs to be uploaded in UBO analysis.
Eric Anholt [Mon, 9 Dec 2019 19:55:21 +0000 (11:55 -0800)]
freedreno: Track the set of UBOs to be uploaded in UBO analysis.

We were iterating over the entire 32-entry array each time, when we
can just use a bitset to know that we're only uploading from the first
entry normally.

Knocks ir3_emit_user_consts down from ~.5% of CPU to .1% on WebGL
fishtank.

Reviewed-by: Rob Clark <robdclark@chromium.org>
4 years agofreedreno: Stop forcing ALLOW_MAPPED_BUFFERS_DURING_EXEC off.
Eric Anholt [Mon, 9 Dec 2019 19:19:14 +0000 (11:19 -0800)]
freedreno: Stop forcing ALLOW_MAPPED_BUFFERS_DURING_EXEC off.

The default is to not throw GL errors when drawing with mapped
buffers, but we were forcing it on for unclear reasons.  Internally we
keep all our buffers mapped anyway, so it should be a no-op other than
reducing CPU overhead (.23% in a perf report for WebGL fishtank)

Reviewed-by: Rob Clark <robdclark@chromium.org>
4 years agofreedreno/fdperf: use drmOpen()
Rob Clark [Mon, 9 Dec 2019 21:08:33 +0000 (13:08 -0800)]
freedreno/fdperf: use drmOpen()

Signed-off-by: Rob Clark <robdclark@chromium.org>
4 years agogallium/util: Support POLYGON in u_stream_outputs_for_vertices
Alyssa Rosenzweig [Fri, 6 Dec 2019 21:45:57 +0000 (16:45 -0500)]
gallium/util: Support POLYGON in u_stream_outputs_for_vertices

u_decomposed_prims_for_vertices cannot support POLYGON, but POLYGON is
trivial to support as a special case directly (since we have the number
of vertices directly).

Fixes aborts in Panfrost in apps using GL_POLYGON.

Fixes: e881aa8c12c ("gallium/util: Add u_stream_outputs_for_vertices helper")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Revewied-by: Eric Anholt <eric@anholt.net>
4 years agointel: Add pci-ids for Jasper Lake
Anuj Phogat [Wed, 4 Dec 2019 23:21:20 +0000 (15:21 -0800)]
intel: Add pci-ids for Jasper Lake

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agointel: Add device info for 1x4x6 Jasper Lake
Anuj Phogat [Wed, 4 Dec 2019 23:19:18 +0000 (15:19 -0800)]
intel: Add device info for 1x4x6 Jasper Lake

Also removing the FIXME comments after matching the numbers with
updated documentation.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agolima: expose tiled format modifier in query_dmabuf_modifiers()
Vasily Khoruzhick [Sun, 8 Dec 2019 20:06:43 +0000 (12:06 -0800)]
lima: expose tiled format modifier in query_dmabuf_modifiers()

Fixes: 8c12f4e5f24f ("lima: enable tiling")
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>