Alyssa Rosenzweig [Tue, 13 Aug 2019 16:11:48 +0000 (09:11 -0700)]
pan/midgard: Wire writemask into UBO reads
Helps the disassembly be clearer and maybe regalloc be smarter.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 13 Aug 2019 15:51:40 +0000 (08:51 -0700)]
pan/midgard: Identify UBO/SSBO op symmetry
It's the same thing, just shifted.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 12 Aug 2019 23:14:03 +0000 (16:14 -0700)]
panfrost: Extend blending to MRT
Our hardware supports independent (per-RT) blending, but we need to
route those settings through from Gallium.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 12 Aug 2019 19:36:46 +0000 (12:36 -0700)]
pan/midgard: Emit store_output branch just-in-time
We'll need multiple branches for MRT, so we can't defer. Also, we need
to track dependencies to ensure r0 is set to the correct value for each
store_output.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 12 Aug 2019 22:29:03 +0000 (15:29 -0700)]
pan/midgard: Add dont_eliminate flag
We need to treat fragment writes specially.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 9 Aug 2019 22:12:30 +0000 (15:12 -0700)]
pan/mfbd: Stuff in RT count
Fixes DATA_INVALID_FAULTs with multiple render targets.
We do always allocate space for 4 cbufs just to keep things sane. This
may not be strictly necessary.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 12 Aug 2019 18:07:00 +0000 (11:07 -0700)]
pan/decode: Dump FBD tagged pointer
Turns out the rt count is stuffed in here..
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 9 Aug 2019 23:04:24 +0000 (16:04 -0700)]
pan/decode: Decode invalid access type upon fault
We don't have a good way to confirm this, but it parallels the kernel
definitons for MMU faults nicely.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 9 Aug 2019 21:56:30 +0000 (14:56 -0700)]
pan/decode: Fix duplicate heap_end property
This was supposed to read heap_start. It's the same value but still,
better get this right.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 23:01:38 +0000 (16:01 -0700)]
panfrost: Note "MFBD preload disable" bit
It's a chicken bit, as far as I can tell. Buck buck.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 19:48:04 +0000 (12:48 -0700)]
pan/bifrost: Link in compiler
We enable the standalone compiler, build the new files, and let it
blast.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 19:46:35 +0000 (12:46 -0700)]
pan/bifrost: Check in remainder of the Bifrost compiler
What it says on the tin.
Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 19:36:30 +0000 (12:36 -0700)]
pan/bifrost: Add bifrost_print.c/h
IR printers.
Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 19:28:01 +0000 (12:28 -0700)]
pan/bifrost: Style format the disassembler
$ astyle *.c *.h --style=linux -s8
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 19:21:23 +0000 (12:21 -0700)]
pan/bifrost: Stub out standalone compiler
We don't actually have a standalone compiler in-tree yet, but let's get
prepared for when we do.
Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 19:19:01 +0000 (12:19 -0700)]
pan/bifrost: Sync disassembler with Ryan's tree
The disassembler was updated to move common code with the compiler into
a shared header. Additional, some new ops and control registers relating
to rounding were added.
Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 21:46:21 +0000 (14:46 -0700)]
panfrost: Remove standalone pandecode tool
Now that panwrap has gained the ability to trace directly without
dumping to the filesystem, there's no need to lug around this tool.
I can assure you nobody will miss it.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 21:42:07 +0000 (14:42 -0700)]
pan/midgard: Fix disassembly termination condition
Fixes: 863bdd1f8dc ("pan/midgard: Break, not return, in disassembler")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 21:41:49 +0000 (14:41 -0700)]
panfrost: Ensure we upload at least 1 blend RT
Otherwise we'll get memory junk.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 21:21:02 +0000 (14:21 -0700)]
panfrost: Zero tripipe on initialize
I don't think the hardware cares, but this adds a lot of noise to traces
that we would rather not need to look at.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 21:11:54 +0000 (14:11 -0700)]
pan/midgard: Improve disassembler robustness
Some memory corruption / etc issues let to an accidental "fuzzing" of
the disassembler ;) This uncovered some issues leading to a disassembler
hang, so let's fix that.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 20:52:03 +0000 (13:52 -0700)]
pan/decode: Split public.h out
We want a defined ABI for tracing; this set of functions should be as
small as strictly necessary to minimize panwrap shenanigans.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 20:21:21 +0000 (13:21 -0700)]
pan/decode: Prefer uint64_t to mali_ptr
This removes an unwanted dependency on panfrost-job.h
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 13 Aug 2019 22:59:41 +0000 (15:59 -0700)]
pan/midgard: Allocate spill_slot once
Multiple spill moves share a single spill slot. Issue found in Krita.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 13 Aug 2019 22:58:49 +0000 (15:58 -0700)]
pan/midgard: Use hint on midgard_instruction for spill_move
This allows us to have multiple spill moves, whereas otherwise for N
spill moves, the first N-1 would be clobbered. Issue found in Krita.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 13 Aug 2019 20:08:52 +0000 (13:08 -0700)]
panfrost: Remove panfrost_add_dependency asserts
It doesn't... make a ton of sense to need to assert and this routine is
hotter than you might expect. Doesn't matter for release builds, of
course.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Marek Olšák [Wed, 2 Jan 2019 20:50:13 +0000 (15:50 -0500)]
radeonsi: add support for Renoir
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Engestrom [Fri, 19 Jul 2019 23:42:13 +0000 (00:42 +0100)]
meson: add nir tests to the compiler/nir test suite
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Engestrom [Thu, 8 Aug 2019 10:13:43 +0000 (11:13 +0100)]
EGL: sync headers with Khronos
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Christian Gmeiner [Wed, 14 Aug 2019 07:37:35 +0000 (09:37 +0200)]
relnotes: Add new ext on etnaviv for 19.2.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Christian Gmeiner [Wed, 14 Aug 2019 13:23:15 +0000 (15:23 +0200)]
etnaviv: fix weird indentation
Fixes: 797a2e4fd03 ("etnaviv: update logic to determine uniform limits")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Ian Romanick [Tue, 6 Aug 2019 20:11:56 +0000 (13:11 -0700)]
nir/algebraic: Reassociate shift-by-constant of shift-by-constant
v2: After some review discussion with Alyssa, the replacements now
correct account for cases where (b+c) >= bitsize.
v3: Use a temporary to simplify the Python code quite a bit. Suggested
by Jason.
Haswell and all Gen8+ platforms had similar results. (Ice Lake shown)
total instructions in shared programs:
16251155 ->
16249576 (<.01%)
instructions in affected programs: 232627 -> 231048 (-0.68%)
helped: 547
HURT: 1
helped stats (abs) min: 1 max: 15 x̄: 2.89 x̃: 3
helped stats (rel) min: 0.04% max: 7.84% x̄: 1.14% x̃: 1.06%
HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.12% max: 0.12% x̄: 0.12% x̃: 0.12%
95% mean confidence interval for instructions value: -3.12 -2.65
95% mean confidence interval for instructions %-change: -1.20% -1.06%
Instructions are helped.
total cycles in shared programs:
365924392 ->
365372103 (-0.15%)
cycles in affected programs:
59207053 ->
58654764 (-0.93%)
helped: 497
HURT: 34
helped stats (abs) min: 1 max: 29300 x̄: 1118.16 x̃: 16
helped stats (rel) min: <.01% max: 10.59% x̄: 1.82% x̃: 1.82%
HURT stats (abs) min: 2 max: 424 x̄: 101.03 x̃: 63
HURT stats (rel) min: 0.07% max: 46.17% x̄: 4.72% x̃: 2.06%
95% mean confidence interval for cycles value: -1426.41 -653.77
95% mean confidence interval for cycles %-change: -1.66% -1.15%
Cycles are helped.
total spills in shared programs: 8870 -> 8871 (0.01%)
spills in affected programs: 104 -> 105 (0.96%)
helped: 0
HURT: 1
Ivy Bridge and all pre-Gen7 platforms had similar results. (Ivy Bridge shown)
total instructions in shared programs:
11956236 ->
11955635 (<.01%)
instructions in affected programs: 94110 -> 93509 (-0.64%)
helped: 106
HURT: 0
helped stats (abs) min: 1 max: 14 x̄: 5.67 x̃: 4
helped stats (rel) min: 0.12% max: 4.71% x̄: 1.96% x̃: 0.76%
95% mean confidence interval for instructions value: -6.62 -4.72
95% mean confidence interval for instructions %-change: -2.27% -1.64%
Instructions are helped.
total cycles in shared programs:
179296340 ->
178788044 (-0.28%)
cycles in affected programs:
51009603 ->
50501307 (-1.00%)
helped: 82
HURT: 7
helped stats (abs) min: 5 max: 27820 x̄: 6199.00 x̃: 16
helped stats (rel) min: 0.30% max: 8.16% x̄: 2.58% x̃: 3.11%
HURT stats (abs) min: 2 max: 8 x̄: 3.14 x̃: 2
HURT stats (rel) min: 0.02% max: 1.40% x̄: 0.34% x̃: 0.10%
95% mean confidence interval for cycles value: -7649.38 -3773.00
95% mean confidence interval for cycles %-change: -2.71% -1.99%
Cycles are helped.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> [v2]
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ian Romanick [Wed, 10 Jul 2019 23:28:38 +0000 (16:28 -0700)]
nir/algebraic: Reassociate add-and-shift to be shift-and-add
A common thing in many shaders:
uniform vs { vec4 bones[...]; };
...
x = some_calculation(bones[i + 0]);
y = some_calculation(bones[i + 1]);
z = some_calculation(bones[i + 2]);
This turns into stuff like
vec1 32 ssa_12 = iadd ssa_11, ssa_0
vec1 32 ssa_13 = ishl ssa_12, ssa_3
vec1 32 ssa_14 = intrinsic load_ssbo (ssa_7, ssa_13) (16, 4, 0)
vec1 32 ssa_15 = iadd ssa_11, ssa_1
vec1 32 ssa_16 = ishl ssa_15, ssa_3
vec1 32 ssa_17 = intrinsic load_ssbo (ssa_7, ssa_16) (16, 4, 0)
vec1 32 ssa_18 = iadd ssa_11, ssa_2
vec1 32 ssa_19 = ishl ssa_18, ssa_3
vec1 32 ssa_20 = intrinsic load_ssbo (ssa_7, ssa_19) (16, 4, 0)
By reassociating the shift and the add, we can reduce this to
vec1 32 ssa_12 = ishl ssa_11, ssa_3
vec1 32 ssa_13 = iadd ssa_12, ssa_0
vec1 32 ssa_14 = intrinsic load_ssbo (ssa_7, ssa_13) (16, 4, 0)
vec1 32 ssa_16 = iadd ssa_12, ssa_1
vec1 32 ssa_17 = intrinsic load_ssbo (ssa_7, ssa_16) (16, 4, 0)
vec1 32 ssa_19 = iadd ssa_12, ssa_2
vec1 32 ssa_20 = intrinsic load_ssbo (ssa_7, ssa_19) (16, 4, 0)
v2: Add some commentary from Rhys Perry's nearly identical patch.
All Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs:
16277758 ->
16250704 (-0.17%)
instructions in affected programs:
1440284 ->
1413230 (-1.88%)
helped: 4920
HURT: 6
helped stats (abs) min: 1 max: 69 x̄: 5.50 x̃: 4
helped stats (rel) min: 0.10% max: 18.33% x̄: 2.21% x̃: 1.79%
HURT stats (abs) min: 1 max: 12 x̄: 4.50 x̃: 3
HURT stats (rel) min: 0.18% max: 3.23% x̄: 1.91% x̃: 2.55%
95% mean confidence interval for instructions value: -5.67 -5.31
95% mean confidence interval for instructions %-change: -2.26% -2.16%
Instructions are helped.
total cycles in shared programs:
367118526 ->
365895358 (-0.33%)
cycles in affected programs:
93504145 ->
92280977 (-1.31%)
helped: 2754
HURT: 1269
helped stats (abs) min: 1 max: 47039 x̄: 460.66 x̃: 16
helped stats (rel) min: <.01% max: 34.93% x̄: 3.77% x̃: 1.12%
HURT stats (abs) min: 1 max: 1500 x̄: 35.85 x̃: 9
HURT stats (rel) min: 0.01% max: 17.35% x̄: 2.18% x̃: 0.75%
95% mean confidence interval for cycles value: -387.31 -220.78
95% mean confidence interval for cycles %-change: -2.11% -1.68%
Cycles are helped.
LOST: 1
GAINED: 1
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Andrii Simiklit [Wed, 7 Aug 2019 10:56:38 +0000 (13:56 +0300)]
nir/find_array_copies: Reject copies with mismatched lengths
copy_deref for wildcard dereferences requires the same
arrays lengths otherwise it leads to a crash in optimizations
like 'nir_opt_copy_prop_vars' because these optimizations expect
'copy_deref' just for arrays with the same lengths.
v2: check was moved to 'try_match_deref' to fix aoa cases
(Jason Ekstrand <jason@jlekstrand.net>)
v3: -fixed comment
-the condition merged with other one
(Jason Ekstrand <jason@jlekstrand.net>)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111286
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 16:19:54 +0000 (09:19 -0700)]
pan/midgard: Prefix blobber-db output for grepping
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 14 Aug 2019 16:11:55 +0000 (09:11 -0700)]
pan/midgard: Implement blobber-db
We wire through some shader-db-style stats on the current shader in the
disassemble so we can get a quick estimate of shader complexity from a
trace.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Suggested-by: Rob Clark <robdclark@chromium.org>
Alyssa Rosenzweig [Wed, 14 Aug 2019 16:11:17 +0000 (09:11 -0700)]
pan/midgard: Break, not return, in disassembler
We'll want to dump some stats after the shader, and I refuse to use one
teensy little goto.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Ian Romanick [Mon, 12 Aug 2019 22:47:35 +0000 (15:47 -0700)]
nir/range-analysis: Fail gracefully on non-SSA sources
Tested-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Christian Gmeiner [Mon, 12 Aug 2019 16:40:17 +0000 (18:40 +0200)]
etnaviv: split destroy_shader
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Christian Gmeiner [Mon, 12 Aug 2019 13:18:20 +0000 (15:18 +0200)]
etnaviv: split link_shader
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Christian Gmeiner [Wed, 14 Aug 2019 08:06:17 +0000 (10:06 +0200)]
etnaviv: split dump_shader
Also this adds the missing impl for etna_dump_shader_nir(..).
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Christian Gmeiner [Wed, 14 Aug 2019 08:00:27 +0000 (10:00 +0200)]
etnaviv: mv etnaviv_compiler.c etnaviv_compiler_tgsi.c
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Christian Gmeiner [Wed, 14 Aug 2019 09:56:02 +0000 (11:56 +0200)]
etnaviv: correct PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE handling
Have a correct answer to GL_MAX_FRAGMENT_UNIFORM_VECTORS and
GL_MAX_VERTEX_UNIFORM_VECTORS.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach l.stach@pengutronix.de
Christian Gmeiner [Wed, 14 Aug 2019 09:39:13 +0000 (11:39 +0200)]
etnaviv: update logic to determine uniform limits
Taken 1:1 from the header file.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach l.stach@pengutronix.de
Christian Gmeiner [Wed, 14 Aug 2019 09:32:50 +0000 (11:32 +0200)]
etnaviv: put uniform limit determination into own function
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach l.stach@pengutronix.de
Marek Vasut [Mon, 3 Jun 2019 22:22:49 +0000 (00:22 +0200)]
etnaviv: Use reentrant screen lock around flush
The flush callback may be called on the same pipe context, and thus
the same stream, from two different threads of execution. However,
etna_cmd_stream_flush{,2}() must not be called on the same stream
from two different threads of execution as that would mess up the
etna_bo refcounting and likely have other ugly side effects.
Fix this by using a reentrant screen lock around the flush callback.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Marek Vasut [Sat, 8 Jun 2019 22:18:29 +0000 (00:18 +0200)]
etnaviv: Add valgrind support
Add Valgrind support for etnaviv to track BO leaks.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Marek Vasut [Mon, 3 Jun 2019 17:49:14 +0000 (19:49 +0200)]
etnaviv: Use hash table to track BO indexes
Use hash table instead of ad-hoc arrays.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Marek Vasut [Sat, 1 Jun 2019 23:07:28 +0000 (01:07 +0200)]
etnaviv: Fix double-free in etna_bo_cache_free()
The following situation can happen in a multithreaded OpenGL application.
A BO is submitted from etna_cmd_stream #1 with flags set for read.
A BO is submitted from etna_cmd_stream #2 with flags set for write.
This triggers a flush on stream #1 and clears the BO's current_stream
pointer. If at this point, stream #2 attempts to queue BO again, which
does happen, the BO will be added to the submit list twice. The Linux
kernel driver correctly detects this and warns about it with "BO at
index %u already on submit list" kernel message.
However, when cleaning the BO cache in etna_bo_cache_free(), the BO
which was submitted twice will also be free()d twice, this triggering
a glibc double free detector.
The fix is easy, even if the BO does not have current_stream set,
iterate over current streams' list of BOs before adding the BO to it
and verify that the BO is not yet there.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Roman Stratiienko [Tue, 6 Aug 2019 10:29:06 +0000 (13:29 +0300)]
kmsro: Add missing definitions to Android.mk
Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
Reviewed-by: Rob Herring robh@kernel.org
Gert Wollny [Tue, 13 Aug 2019 16:08:34 +0000 (18:08 +0200)]
softpipe: Add support for ARB_derivative_control
Enables and passes piglits:
spec/ARB_drivative_control/
dfdx-coarse
dfdx-dfdy
dfdx-fine
dfdy-coarse
dfdy-fine
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Vasily Khoruzhick [Fri, 2 Aug 2019 04:27:17 +0000 (21:27 -0700)]
lima/ppir: print srcs and dests in ppir_node_print_prog()
Now we have an accessors for ppir src, so it's possible to easily
print all srcs and dests while dumping ppir representation.
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Vasily Khoruzhick [Fri, 2 Aug 2019 05:04:34 +0000 (22:04 -0700)]
lima/ppir: use src accessors in ppir regalloc
Get rid of most switch/case by using src accessors
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Vasily Khoruzhick [Wed, 24 Jul 2019 22:29:34 +0000 (15:29 -0700)]
lima/ppir: add ppir_node to ppir_src
We'll need it if we want to walk through node sources
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Vasily Khoruzhick [Wed, 24 Jul 2019 22:25:33 +0000 (15:25 -0700)]
lima/ppir: introduce accessors for ppir_node sources
Sometimes we need to walk through ppir_node sources, common
accessor for all node types will simplify code a lot.
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Jordan Justen [Tue, 25 Jun 2019 02:24:37 +0000 (19:24 -0700)]
iris: Expose aux buffer as 2nd plane w/modifiers
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Tue, 9 Jul 2019 07:47:15 +0000 (00:47 -0700)]
iris: Export and import surfaces with modifiers that have aux data
The DRI interface for modifiers with aux data treats the aux data as a
separate plane of the main surface.
When the dri layer requests the plane associated with the aux data, we
save the required information into the dri aux plane image.
Later when the image is used, the dri plane image will be available in
the pipe_resource structure's `next` field. Therefore in iris, we
reconstruct the aux setup from this separate dri plane image when the
image is used.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Tue, 26 Mar 2019 07:25:31 +0000 (00:25 -0700)]
iris: Do proper format checks for Y+CCS modifier support
We need to ensure that the DRI image format supports CCS.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jordan Justen [Sun, 23 Jun 2019 08:16:48 +0000 (01:16 -0700)]
iris: Create single bo for surfaces with modifiers and aux data
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sun, 23 Jun 2019 07:53:23 +0000 (00:53 -0700)]
iris: Split iris_resource_alloc_aux to enable aux modifiers
Reworks:
* If the aux-state is not ISL_AUX_STATE_AUX_INVALID, then use memset
even when memset_value is zero. The hiz buffer initial aux-state
will be set to invalid, and therefore we can skip the memset. But,
for CCS it will be set to ISL_AUX_STATE_PASS_THROUGH, and therefore
the aux data must be cleared to 0 with the memset. Previously we
would use BO_ALLOC_ZEROED with the CCS aux data, so this memset
wasn't required. Now, the CCS aux data may be part of the main
surface. We prefer to not use BO_ALLOC_ZEROED excessively, so the
memset is needed for the CCS case. (Nanley)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Tue, 13 Aug 2019 08:37:11 +0000 (01:37 -0700)]
iris: Add aux offset into hiz_address
This is not currently required because the hiz buffer is in a separate
buffer, and therefore the offset is 0. If we combine the aux buffer
with the main surface buffer, then the hiz offset may become non-zero.
Suggested-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Marek Olšák [Tue, 13 Aug 2019 22:14:17 +0000 (18:14 -0400)]
tgsi_to_nir: add assertions for max varying slots
Nine uses GENERIC slots > 31.
Trivial.
Marek Olšák [Tue, 13 Aug 2019 19:26:51 +0000 (15:26 -0400)]
tgsi_to_nir: expand vec3 system values to vec4
for nir_intrinsic_load_work_group_id
Reviewed-by: Eric Anholt <eric@anholt.net>
Marek Olšák [Tue, 13 Aug 2019 19:25:40 +0000 (15:25 -0400)]
tgsi_to_nir: fix incorrect number of image src1 components
Reviewed-by: Eric Anholt <eric@anholt.net>
Mauro Rossi [Tue, 13 Aug 2019 15:38:29 +0000 (17:38 +0200)]
i965/gen11: fix genX_bits.h include path
Instead of "genX_bits.h" use "genxml/genX_bits.h"
as already done in other similar cases
Besides being more correct, it also fixes building error in Android.
Fixes: f0d2923 ("i965/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Alyssa Rosenzweig [Tue, 13 Aug 2019 14:19:27 +0000 (07:19 -0700)]
panfrost: Workaround bug in partial update implementation
We can't intersect with empty regions.
Fixes: 65ae86b8542 ("panfrost: Add support for KHR_partial_update()")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Eric Anholt [Fri, 28 Jun 2019 23:35:32 +0000 (16:35 -0700)]
gitlab-ci: Run the GLES2 CTS on llvmpipe.
This is the start of doing CTS tests on merges to Mesa master. We use
the surfaceless platform so that we don't need to bother bringing up
weston or X11. The surface size is kept low to reduce runtime, but
this comes at the cost of many rendering tests skipping due to
too-small render targets (as we see the impact of Mesa on the shared
runner pool, we can reevaluate this and what set of CTS tests we want
to run).
We split the job up across 4 runners (each at 4 llvmpipe threads), so
that the job can load-balance across our shared runners and finish
sooner (since dEQP is very single-thread-performance bound).
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Anholt [Thu, 1 Aug 2019 19:14:15 +0000 (12:14 -0700)]
gitlab-ci: Switch the meson-main build type to debugoptimized.
Now that we're running the drivers we build, building with
optimization is important for keeping our runtime down. Shaves about
4 minutes of runtime off of GLES2 CTS of llvmpipe at 64x64.
v2: Only switch meson-main until we enable CTS for other builds
on request by Michel.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Anholt [Thu, 25 Jul 2019 18:02:34 +0000 (11:02 -0700)]
gitlab-ci: Set the prefix to ./install instead of the DESTDIR.
If we don't set DESTDIR, then the DEFAULT_DRIVER_DIR built into the
libraries is correct and we don't need to use LIBGL_DRIVERS_PATH and
friends for CI usage. Incidentally, this moves our installed paths
from /builds/anholt/mesa/install/usr/local/lib (for example) to
/builds/anholt/mesa/install/lib for simplicity.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Anholt [Mon, 22 Jul 2019 19:03:47 +0000 (12:03 -0700)]
gitlab-ci: Build the CTS in the debian build image.
This will let us reuse the image for test runs.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Anholt [Mon, 29 Jul 2019 23:25:56 +0000 (16:25 -0700)]
surfaceless: Fix swrast-path segfault when loader doesn't know driver name.
If we're hitting the swrast fallback path here, it's probably because
we stumbled across a KMS-only device (such as the ASpeed that some of
our CI runners have) that will then return a NULL driver_name. Don't
crash in that case.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Anholt [Tue, 23 Jul 2019 20:18:21 +0000 (13:18 -0700)]
surfaceless: Fix swrast path.
We get a getDrawableInfo() call in the MakeCurrent path, which
platform_device was handling correctly by returning the pbuffer's
width/height but platform_surfaceless segfaulted for. Reuse
platform_device's implementation.
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Eric Anholt [Wed, 7 Aug 2019 21:05:51 +0000 (14:05 -0700)]
gitlab-ci: Move around which builds cover which swrast.
I want to enable CI of llvmpipe out of the meson-main build. So, kick
classic swrast/osmesa to meson-i386, then promote llvmpipe to
meson-main (along with nine, now that classic osmesa isn't keeping it
out of there).
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Anholt [Thu, 18 Jul 2019 21:45:57 +0000 (14:45 -0700)]
meson: Don't require DRI classic swrast for OSMesa.
OSMesa doesn't care about this build option, it links against
src/mesa/swrast regardless.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Alyssa Rosenzweig [Fri, 9 Aug 2019 19:32:49 +0000 (12:32 -0700)]
panfrost: Implement transform feedback
Midgard has no hardware support for transform feedback, so we simulate
it in software. Lucky us.
What Midgard does do is write out vertex shader outputs to main memory
unconditonally. Fragment shaders read varyings back from main memory;
there's no on-chip storage for varyings. Whether this was a reasonable
design is a question I will not be engaging in this commit message.
What that does mean is that, in some sense, Midgard *always* does
transform feedback uncondtionally, and there's no way to turn off
transform feedback. Normally, we would allocate some scratch memory
every frame to store the varyings in an arbitrary format (interleaved
for simplicity), and then feed that scratch to the fragment shader and
discard when the rendering completes.
The only difference now is that sometimes, for some buffers, we use a BO
provided to us by Gallium and a format provided by Gallium, instead of
allocating the memory and choosing the format ourselves. This has some
limitations -- in particular, it only works at vec4 granularity, so a
corresponding GLSL linkage patch is needed to correctly implement
transform feedback for non-vec4 types. Nevertheless, given the hardware
already works in this admittedly-bizarre fashion, transform feedback is
"free". Or, at least, it's no more expensive than any other rendering.
Specifically not implemented is dynamically-sized transform feedback
(i.e. with geometry/tesselation shaders).
Spoiler alert: Midgard has no support for geometry *or* tessellation
shaders, despite advertising support. They get compiled to *massive*
compute shaders. How's that for checkbox compliance?
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Alyssa Rosenzweig [Thu, 8 Aug 2019 15:16:09 +0000 (08:16 -0700)]
panfrost: Increment offsets[] per draw
We have to maintain the internal offset ourselves. Per v3d.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Alyssa Rosenzweig [Wed, 7 Aug 2019 17:33:15 +0000 (10:33 -0700)]
panfrost: Fixup stream out information per variant
We could probably get away with doing this once per pipe_shader_state
but let's not jump down that rabbit hole quite yet.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Alyssa Rosenzweig [Wed, 7 Aug 2019 17:26:12 +0000 (10:26 -0700)]
panfrost: Route outputs_written through the compiler
It's there in shader_info, but we need to access it from pan_context.c
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Alyssa Rosenzweig [Wed, 7 Aug 2019 17:11:28 +0000 (10:11 -0700)]
panfrost: Import stream out utility from iris
We'll need this in a moment. Ken's implementation, lightly edited for
Panfrost.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Alyssa Rosenzweig [Thu, 8 Aug 2019 14:46:54 +0000 (07:46 -0700)]
panfrost: Flush when using transform feedback
This is a huge hack to workaround incomplete BO flushing logic, but it's
enough for the dEQP transform feedback tests, and doing the resource
management to get this right is out-of-scope for this patch series.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Alyssa Rosenzweig [Wed, 7 Aug 2019 19:00:14 +0000 (12:00 -0700)]
panfrost: Set PIPE_CAP_TGSI_TEXCOORD
It doesn't really make sense, since we don't have special texture
coordinate varyings, but it'll make some code simpler for XFB and it
doesn't hurt us, even if I lose a bit of my soul setting it.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Alyssa Rosenzweig [Thu, 8 Aug 2019 14:10:24 +0000 (07:10 -0700)]
panfrost: Wire up statistics for primitives
GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN should now be handled.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Alyssa Rosenzweig [Thu, 8 Aug 2019 14:01:12 +0000 (07:01 -0700)]
panfrost: Implement callbacks for PRIMITIVES queries
We're just going to compute them in the driver but let's get the
structures setup to handle them. Implementation from v3d.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Rob Clark [Wed, 7 Aug 2019 18:40:31 +0000 (11:40 -0700)]
freedreno/a6xx: move SSBO/image consts to IBO stateobj
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Wed, 7 Aug 2019 18:34:03 +0000 (11:34 -0700)]
freedreno/a6xx: move VS driverparams to it's own stateobj
If driver-params are required, we really should emit it on every draw
for correctness. And if not required, we should emit a DISABLE so that
un-applied state updates from previous draws don't corrupt the const
state.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Fri, 2 Aug 2019 21:07:47 +0000 (14:07 -0700)]
freedreno/ir3+a6xx: same VBO state for draw/binning
Worth ~+20% on gl_driver2
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Fri, 2 Aug 2019 16:57:08 +0000 (09:57 -0700)]
freedreno/a6xx: add fd_emit_take_group()
Which takes ownership of the stateobj. Useful for streaming state-
objs, to avoid an extra ref/unref
Worth ~5% at gl_driver2
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Thu, 1 Aug 2019 21:22:46 +0000 (14:22 -0700)]
freedreno/ir3: track # of driver params
To avoid emitting unneeded const state.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Thu, 1 Aug 2019 15:35:14 +0000 (08:35 -0700)]
freedreno/a6xx: move immediates to program stateobj
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Thu, 1 Aug 2019 15:31:25 +0000 (08:31 -0700)]
freedreno/a6xx: stop using ir3_emit_{vs,fs}_consts()
Should be no functional change. Next step is to re-arrange various
const state into different stateobjs.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Thu, 1 Aug 2019 15:13:02 +0000 (08:13 -0700)]
freedreno/ir3: push ctx further up call chain
Move more of the code to deal just w/ screen, without requiring ctx.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Thu, 1 Aug 2019 02:00:59 +0000 (19:00 -0700)]
freedreno/ir3: move ring_wfi() further up call chain
Hoist them out of code-paths that will eventually be called directly for
various a6xx+ const related stateobjs.
This ends up duplicating one constlen check in ir3_emit_vs_consts(), to
avoid what could otherwise be an unnecessary WFI on older gens.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Thu, 1 Aug 2019 01:26:57 +0000 (18:26 -0700)]
freedreno/all: move more emit helpers to screen
framebuffer_barrier() still depends on the ctx, but the rest can move to
screen.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Thu, 1 Aug 2019 01:20:52 +0000 (18:20 -0700)]
freedreno/a3xx-a6xx+ir3: move emit_const* to screen
These don't need to be in context, and we'll need them in screen in a
later patch. Plus it's a good cleanup.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Thu, 1 Aug 2019 01:13:38 +0000 (18:13 -0700)]
freedreno/a6xx: add fd6_emit_init_screen()
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Thu, 1 Aug 2019 01:12:00 +0000 (18:12 -0700)]
freedreno/a5xx: add fd5_emit_init_screen()
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Thu, 1 Aug 2019 01:09:26 +0000 (18:09 -0700)]
freedreno/a3xx: add fd3_emit_init_screen()
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Thu, 1 Aug 2019 01:01:07 +0000 (18:01 -0700)]
freedreno/a2xx: add fd2_emit_init_screen()
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Thu, 1 Aug 2019 00:58:56 +0000 (17:58 -0700)]
freedreno/a4xx: add fd4_emit_init_screen()
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Thu, 1 Aug 2019 00:43:32 +0000 (17:43 -0700)]
freedreno/a2xx: call fd2_emit_ib() directly from fd2
Signed-off-by: Rob Clark <robdclark@chromium.org>