mesa: optimise interleaved sso validation

Now that we have a linked_stages bitfield we can use this
to check if the program is used at a later stage.

This change is also required to be able to use gl_program
rather than gl_shader_program in the CurrentProgram array.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa/glsl: add bitmask to track stages a program was linked against

This will be used to enable us to store the current gl_program
rather than gl_shader_program in the gl_pipline_object allowing
us to simplify handing of validation.

Also we should not be depending on _LinkedShader for this information
as it may contain shaders from a failed linking attempt rather than
the current program still in use.

We could also use this mask to iterate over the stages during linking
with _mesa_bit_scan() rather then the current method of NULL checking
each stage.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

swr: [rasterizer jit] use signed integer representation for logic op

Instead of (incorrectly) biasing the snorm value to make it look like a
unorm, just use signed integer math.

This fixes arb_color_buffer_float-render GL_RGBA8_SNORM

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: add missing rgbx8_srgb variant

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: reorder renderable formats, add grouping comments

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: use util_copy_framebuffer_state helper

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: enable cubemap arrays

Everything is in place for these.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: rearrange caps into limits/supported/unsupported groups

I find this a lot more readable and compact - much easier to scan
through the list and see what's on and what's off.

No functional change intended.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: only store up to the LOD size

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer common] add SwrTrace() and macros

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

radeonsi: don't fetch 8 dwords for samplerBuffer and imageBuffer

The compiler doesn't shrink s_load_dwordx8, so we always wasted 4 SGPRs.
Also, the extraction of the descriptor created some really ugly asm code
with lots of VALU bitwise ops and v_readfirstlane.

Totals from *affected* shaders:
SGPRS: 13880 -> 13253 (-4.52 %)
VGPRS: 15200 -> 15088 (-0.74 %)
Code Size: 499864 -> 459816 (-8.01 %) bytes
Max Waves: 1554 -> 1564 (0.64 %)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: disable XNACK to free 2 SGPRs on APUs

My LLVM commit disables it for dGPUs, but not APUs.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: count and report temp arrays in scratch separately

v2: only do this if debug output of shader dumping is enabled

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)

radeonsi: don't try to eliminate trivial VS outputs for PS and CS

PS and CS don't have any param exports, so it's a no-op.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: disable RB+ blend optimizations for dual source blending

This fixes dual source blending on Stoney. The fix was copied from Vulkan.
The problem was discovered during internal testing.

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: set CB_BLEND1_CONTROL.ENABLE for dual source blending

copied from Vulkan

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: always set all blend registers

better safe than sorry

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: set the smallest possible CB_TARGET_MASK

better safe than sorry; set_framebuffer_state always makes this dirty

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't print bodies of header-only packets

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: print unknown registers with correct formatting

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ddebug: fix hang detection with deferred flushes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radv: set spi_baryc_cntl.pos_float_location to 0

This fixes:
dEQP-VK.pipeline.multisample_interpolation.offset_interpolate_at_sample_position.*

This should probably be 2 when sample shading is enabled, but I'm
not sure.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: force persample shading when required.

We need to force persample shading when
a) shader uses sample_id
b) shader uses sample_position
c) shader uses sample qualifier.

Also since ps_iter_samples can now change independently of the
rasterizer samples we need to move setting the regs more often.

This fixes:
dEQP-VK.pipeline.multisample_interpolation.centroid_interpolate_at_consistency.*
dEQP-VK.pipeline.multisample_interpolation.centroid_qualifier_inside_primitive.137_191_1.*
dEQP-VK.pipeline.multisample_interpolation.sample_interpolate_at_distinct_values.*
dEQP-VK.pipeline.multisample_interpolation.sample_qualifier_distinct_values.128_128_1.*

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

nir: print var binding in dumps.

This only useful for spir-v shaders, but I keep finding myself
having to add it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

docs: fix small typo

Fixes: ba28f2136febca32fe56 ("docs: add note about r-b/other tags when resending")
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

i965/sched: Schedule trivial blocks.

In commit 45cd76e342d1e8e schedule_instructions(bblock_t *) began
setting bblock_t::cycle_count, but that function was not called on
trivial blocks.

Remove the code to skip trivial blocks so that cycle_count is set.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/sched: Make 'time' a local variable.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/cfg: Initialize bblock_t::cycle_count.

schedule_instructions(bblock_t *) isn't called on blocks with a single
instruction, and since it is the only thing that set cycle_count,
cycle_count would be uninitialized.

A non-empty block with bblock_t::cycle_count == 0 is arguably a bug.
That'll be fixed in the next commit.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/cfg: Initialize cfg_t::cycle_count.

This reverts commit b4001af1744a02f472bd1204458662088307981b.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

ac/nir: Fix accessing an unitialized value.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Initialize the shader_stats_dump flag.

Meta was using it before it was set. I suspect we typically don't
want to dump meta shaders, so just set it to false in the beginning.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

vc4: Add a note for the future about texture latency calculation.

Debugging a shader-db reported cycle count regression from the tex
coalescing, I eventually figured out that the texture latencies were
totally bogus.  Really fixing it will probably involve mirroring
vc4_qir_schedule.c's texture fifo management here.

vc4: Add support for coalescing ALU ops into tex_[srtb] MOVs.

This isn't as complete as I would like (can't merge interpolation because
of the implicit r5 dependency, doesn't work with control flow), but this
was cheap and easy.

Improves 3DMMES Taiji performance by 1.15353% +/- 0.299896% (n=29, 16)

total instructions in shared programs: 99810 -> 99059 (-0.75%)
instructions in affected programs:     10705 -> 9954 (-7.02%)

vc4: Restructure VPM write optimization into two passes.

For texturing, there won't be a fixed limit on how many writes there are,
so we need to compute uses up front.

vc4: Make qir_for_each_inst_inorder() safe against removal.

The dead code elimination wants it to be safe, and I actually got
segfaults due to it being unsafe with the new coalescing pass.

vc4: Split optimizing VPM writes from VPM reads.

The VPM write logic will be basically the same as the texture coordinate
write logic we need, and it's not really related to the VPM read logic
other than the reuse of the use_count array.

vc4: Restructure texture insts as ALU ops with tex_[strb] as the dst.

For now we're still just generating MOVs, but this will let us fold into
other ops in the future.  No difference on shader-db.

vc4: Refactor qir_get_op_nsrc(enum qop) to qir_get_nsrc(struct qinst *).

Every caller was dereffing the qinst, and this will let us make the number
of sources vary depending on the destination of the qinst so that we can
have general ALU ops that store to tex_[strb] and get an implicit uniform.

vc4: Replace the qinst src[] with a fixed-size array.

This may have made a tiny bit of sense when we had one 4-arg inst per
shader, but if we only ever put 2 things in, having a pointer to 2 things
almost every instruction is pointless indirection.

vc4: Remove qir_inst4().

This was used originally for unorm4x8 packs, but we now represent those as
a series of packed movs.

anv: bump the texture gather offset limits

This matches what NVIDIA and AMD hardware expose, as well as what Intel
hardware supports.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/gen7: expose larger gather offsets

This matches the capabilities of the hardware.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: support constant gather offsets larger than 4 bits

Offsets that don't fit into 4 bits need to force gather_po to be
selected. Adjust the logic so that this happens.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/fs: Refactor handling of constant tg4 offsets

Previously, we had an OFFSET_VALUE source for logical texture instructions
that was intended to mean exactly what it says, "offset".  In reality, we
only fully used it for tg4 offsets.  We used offset_value.file == IMM to
mean, "you have a constant offset, go look in instr->offset" and didn't
actually use the contents of the register at all in that case except for
in nir_emit_texture where we used it as a temporary before we copy it into
instr->offset.

This commit renames OFFSET_VALUE to TG4_OFFSET and restricts its usage to
indirect tg4 offsets only.  The nir_emit_texture code is refactored so that
we explicitly build a header_bits value which is placed in instr->offset
and the constant offset values (both for tg4 and regular texture
operations) are used to construct header_bits and don't go through the
offset source at all.  Finally, we stop passing offset_value in to
lower_sampler_logical_send_gen5 because we can't do indirect offsets until
gen7 anyway.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radv: Use different intrinsic for ubo loads.

Not sure about the deprecation path, but this intrinsic
can be lowered to SMEM loads. This results in a significant
Talos performance improvement.

v2: Fix for LLVM attribute changes.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

mesa: fix active subroutine uniforms properly

07fe2d565b introduced a big hack in order to return
NumSubroutineUniforms when querying ACTIVE_RESOURCES for
<shader>_SUBROUTINE_UNIFORM interfaces. However this is the
wrong fix we are meant to be returning the number of active
resources i.e. the count of subroutine uniforms in the
resource list which is what the code was previously doing,
anything else will cause trouble when trying to retrieve
the resource properties based on the ACTIVE_RESOURCES count.

The real problem is that NumSubroutineUniforms was counting
array elements as separate uniforms but the innermost array
is always considered a single uniform so we fix that count
instead which was counted incorrectly in 7fa0250f9.

Idealy we could probably completely remove
NumSubroutineUniforms and just compute its value when needed
from the resource list but this works for now.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: 13.0 <mesa-stable@lists.freedesktop.org>

anv/cmd_buffer: Remove the 1-D case from the HiZ QPitch calculation

The 1-D special case doesn't actually apply to depth or HiZ.  I discovered
this while converting BLORP over to genxml and ISL.  The reason is that the
1-D special case only applies to the new Sky Lake 1-D layout which is only
used for LINEAR 1-D images.  For tiled 1-D images, such as depth buffers,
the old gen4 2-D layout is used and the QPitch should be in rows.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>

anv/cmd_buffer: Set the correct surface type for depth/stencil

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

anv: enable drawIndirectFirstInstance

This was already piped through in the CmdDraw(Indexed)Indirect handling.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: expose depthBiasClamp, it is already set

The gen7/8_cmd_buffer logic already sets the clamp, and it's piped
through via the dynamic state.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv: bump maxFramebufferLayers to 2048

This matches maxImageArrayLayers, as well as the same setting in the GL
frontend.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv: enable storage image extended formats

These are all regularly available in desktop GL, so the backend fully
supports them.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: expose imageCubeArray functionality

This appears to be fully supported already.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radv: set maxFragmentDualSrcAttachments to 1

Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

anv: set maxFragmentDualSrcAttachments to 1

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

swr: [rasterizer memory] only clear up to the LOD size

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer memory] hook up stencil clears for ClearTile

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer memory] add support for clearing Z32F_X32 and Z16

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

intel/aubinator: Pull useful information from the AUB header

This commit does two things.  One is to pull useful and/or interesting
information from the AUB file header and display it as a header above your
decoded batches.  Second, it is now capable of pulling the PCI ID from the
AUB file comment left by intel_aubdump.  This removes the need to use the
--gen flag all the time.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/aubinator: Wait to setup decoders until we parse the aub header

This requires that a few more state bits become global.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/aubinator: Rework handling of the --gen flag

This makes it just store the pci_id instead of a struct pointer

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/aubinator: Trust the packet size in the header for SUBOPCODE_HEADER

We were reading from the "comment size" dword and incrementing by that
amount.  This never caused a problem because that field was always zero.
However, experimenting with actual aub file comments indicates, the
simulator seems to include the comment size in the packet size provided in
the header.  We should do the same.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/aubinator: Add a get_offset helper

The helper automatically handles masking for us so we don't have to worry
about whether or not something is in the bottom bits.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

intel/aubinator: Fix the kernel start pointer for 3DSTATE_HS

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

intel/aubinator: Add a get_address helper

This new helper is automatically handles 32 vs. 48-bit GTT issues.  It also
handles 48-bit canonical addresses on Broadwell and above.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

intel/aubinator: Properly handle batch buffer chaining

The original aubinator that Kristian wrote had a bug in the handling of
MI_BATCH_BUFFER_START that propagated into the version in upstream mesa.
In particular, it ignored the "2nd level" bit which tells you whether this
MI_BATCH_BUFFER_START is a subroutine call (2nd level) or a goto.  Since
the Vulkan driver uses batch chaining, this can lead to a very confusing
interpretation of the batches.  In some cases, depending on how things are
laid out in the virtual GTT, you can even end up with infinite loops in
batch processing.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

swr: don't clear all dirty bits when changing so targets

Among other things, blits would clear existing SO targets which would
cause a bunch of updates from u_blitter to be missed.

Fixes fbo-scissor-blit fbo, probably among many others.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] fix typo in scissor tile-alignment logic

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

anv: Fix cache UUID generation.

I asked Emil to switch from 0 (success) vs. -1 (fail) to use a boolean
in my review comments.  The "not" went missing.  Easy mistake, but the
result is that nothing runs at all :)

Fix whitespace while we're here too.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

vulkan/wsi: Fix resource leak in success path of wsi_queue_init()

It fixes leakage of pthread_condattr resource on wsi_queue_init()

Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

anv: Update the teardown in reverse order of the anv_CreateDevice

This updates releasing of resource in reverse order of the anv_CreateDevice
to anv_DestroyDevice.
And it fixes resource leak in pthread_mutex, pthread_cond, anv_gem_context.

Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: drop the return type for anv_queue_init()

anv_queue_init() always returns VK_SUCCESS, so caller does not need
to check return value of anv_queue_init().

Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: Add missing error-checking to anv_block_pool_init (v2)

When the memfd_create() and u_vector_init() fail on anv_block_pool_init(),
this patch makes to return VK_ERROR_INITIALIZATION_FAILED.
All of initialization success on anv_block_pool_init(), it makes to return
VK_SUCCESS.

CID 1394319

v2: Fixes from Emil's review:
  a) Add the return type for propagating the return value to caller.
  b) Changed anv_block_pool_init() to return VK_ERROR_INITIALIZATION_FAILED
     on failure of initialization.

Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

st/omx/dec/h264: consider POC as signed instead of unsigned

picture order count can be a negative value

Reviewed-by: Christian König <christian.koenig@amd.com>

radv: don't return VK_SUCCESS if radv_device_get_cache_uuid() fails

If radv_device_get_cache_uuid() fails result will be VK_SUCCESS as set
by the radv_init_wsi() call above.

Fixes: d943839 (radv: Use library mtime for cache UUID.)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: don't leak the fd if radv_physical_device_init() succeeds

radv_amdgpu_winsys_create() does not take ownership of the fd, thus we
end up leaking it as we return with VK_SUCCESS.

Cc: Dave Airlie <airlied@redhat.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

anv: don't leak memory if anv_init_wsi() fails

brw_compiler_create() rzalloc-ates memory which we forgot to free.

Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: don't double-close the same fd

Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: remove no longer used TIMESTAMP_CMD

Good bye, you shall not be missed.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

anv: automake: don't generate anv_timestamp.h

No longer used as of last commit.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

anv: Use library mtime for cache UUID.

Inspired by a similar commit for radv.

Rather than recomputing the timestamp on each make invocation, just
fetch it at runtime.

Thus we no longer get the constant rebuild of anv_device.c and the
follow-up libvulkan_intel.so link, when nothing has changed.

I.e. using make && make install is a little bit faster.

v2: Use bool return type (Ken).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv: Store UUID in physical device.

Port of an equivalent commit for radv.

v2: Move the call just after MMAP_VERSION (Ken).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

isl: Make isl_finishme only warn once per call-site

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

radv: Make radv_finishme only warn once per call-site

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

anv: use do { } while (0) in the anv_finishme macro

Use the generic construct instead of the currect GCC specific one.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

docs: add git tips how to do commit fixups and squash them

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add note about r-b/other tags when resending

[Emil Velikov: split from the typos fixes]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: fix small typos in the submit patches page

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

docs/releasing: use correct page title

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs/releasing: correctly document touch-testing

I've used an ancient version of the script which did not cover:
 - version expansion (cd mesa-* does not work)
 - --enable-glx-tls
 - EGL and es2* testing
 - Vulkan and DOTA2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs/release: drop references to patchwork

The changes to release.sh have landed, so all we need is a recent
checkout of xorg-utils.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add news item and link release notes for 13.0.2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add sha256 checksums for 13.0.2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 2722144beddac0aa7065b478502c7c3a1f2a5451)

docs: add release notes for 13.0.2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit c9e993ba1301ac0380b86a3934f5c97ff0827594)

radv: fix 3D clears with baseMiplevel

This fixes:
dEQP-VK.api.image_clearing.clear_color_image.3d*

These were hitting an assert as the code wasn't taking the
baseMipLevel into account when minify the image depth.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>

radv: brown-paper bag for a forgotten else.

This fixes the fix:
radv/ac/llvm: fix regression with shadow samplers fix

Signed-off-by: Dave Airlie <airlied@redhat.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>

radv/ac/llvm: fix regression with shadow samplers fix

This fixes b56b54cbf1d8e70c87a434da5350d11533e5fed8:
radv/ac/llvm: shadow samplers only return one value

It makes sure we only do that for shadow sampling, as
opposed to sizing requests.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>

radv/ac/llvm: shadow samplers only return one value.

The intrinsic engine asserts in llvm due to this.

Reported-by: Christoph Haag <haagch+mesadev@frickel.club>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/si: fix optimal micro tile selection

The same fix was posted for radeonsi, so port it here.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: honour the number of properties available

Cap up-to the number of properties available while copying the data.
Otherwise we might crash and/or leak data.

Cc: Dave Airlie <airlied@redhat.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>