gbm: Axe buffer import format conversion table

Wayland buffers coming from wl_drm use the WL_DRM_FORMAT_* enums, which
are identical to GBM_FORMAT_*. Similarly, FD imports do not need to
convert between GBM and DRI FourCC, since they are (almost) completely
compatible.

This widens the formats accepted by gbm_bo_import() when importing
wl_buffers; previously, only XRGB8888, ARGB8888, RGB565 and YUYV were
supported.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

i965/gen4: Set tile offsets to zero after depth rebase

Current logic calls intel_renderbuffer_set_draw_offset() which in
turn tries to calculate x and y offset against layer/level settings
that are against the original miptree actually having sufficient
levels/layers. This returns correctly x=0 y=0 regardless of the given
layer/level only because one calls intel_miptree_get_image_offset()
which goes and consults miptree offset table which in turn luckily
contains entries for max-mipmap levels, all initialised to zero even
in case of non-mipmapped.

This patch stops consulting the table and simply sets the draw
offsets to zero that are compatible with the single slice miptree
backing the renderbuffer.
This prepares for ISL based miptrees that calculate offsets
on-demand and do not tolerate levels beyond what the miptree has.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Refactor check for separate stencil

v2 (Jason): s/needs_stencil/needs_separate_stencil/

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp/gen4: Drop cube map flag for single face copy

This will falsely trigger an assert on number of layers once
isl is used for 3D layouts of Gen4 cube maps.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/wm: Use level offsets directly

dropping dependency to slice table.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Use offset helper in intel_readpixels_tiled_memcpy()

providing support for isl based.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/miptree: Pass flags instead of explicit tiling to surface creator

allowing one to use isl tiling filter.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/miptree: Add pitch override for imported buffer objects

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/miptree: Stop setting total_width/height for existing bo

Now that image surface vertical slice calculator doesn't depend
on total_height, total dimensions are only needed when new buffer
objects are created. Therefore one can safely ignore them when
miptrees are created for already exisiting buffer objects.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/wm: Use isl for filling tex image parameters

This helps to drop dependency to miptree::total_height which is
used in brw_miptree_get_vertical_slice_pitch().

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Take 3D surfaces into account in image params

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/miptree: Check for miptree_create() failures

Rest of the function assumes it always succeeds.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/miptree: Do not rely on msaa type to decide if aux is needed

Once the driver moves to ISL both compressed and uncompressed have
the same type. One needs to tell them apart by other means. This
can be done by checking the existence of mcs_buf.

There is a short period of time within intel_miptree_create()
where mcs_buf doesn't exist yet (between calls to
intel_miptree_create_layout() and intel_miptree_alloc_mcs()).
First compute_msaa_layout() makes the decision if compression is
to be used and sets the msaa_layout type. Then based on the type
one sets aux_usage and finally decides if mcs_buf is needed.

This patch duplicates the logic in compute_msaa_layout() and uses
that to make the decision on aux_usage and mcs_buf allocation.
Most of the original logic in compute_msaa_layout() will be gone
in later patch leaving only one version.

Elsewhere only brw_populate_sampler_prog_key_data() needs to know
if compression is used based on the msaa_type. This is now
replaced with consideration for number of samples and existence
of mcs_buf. All other occurrences consider CMS || UMS which can
be represented using single the type of ISL_MSAA_LAYOUT_ARRAY
without any tweaks.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Make irb::mt_layer logical instead of physical

same as irb::layer_count. In case of copies and blits msaa
surfacas already fall to blorp which natively works with logical
slices.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/tex: Use offset helper instead of accessing table directly

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Mark read-only args as const in intel_miptree_supports_hiz()

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/miptree: Use > 1 instead of > 0 to check for multisampling

Checking against zero currently works as single sampling is
represented with zero. Once one moves to isl single sampling
really has sample number of one.

This keeps later patches simpler.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/miptree: Set refcount before failing via _release()

Otherwise one wraps uint to UINT_MAX via -1.

Fixes: 3cf470f2b6c ("i965: Add isl based miptree creator")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

build: Add $(top_srcdir)/src/compiler/spirv to AM_CPPFLAGS

Generated C files try to include spirv_info.h.  For in-tree builds,
the header is in the same directory, so it just works.  For out-of-tree
builds, we need to look for it in srcdir rather than builddir.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101831
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

radeonsi: add back the USE_MININUM_PRIORITY flag to the low-prio compiler queue

Accidentally removed in 9f320e0a387a1009c5218daf130b3b754a3c2800.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

compiler/spirv: Add a .gitignore and ignore spirv_info.c

anv: Advertise support for VK_KHR_variable_pointers

We don't support the general version yet because that requires us to
lower shared variables up-front in SPIR-V -> NIR.  This shouldn't be a
whole lot of work but it's not something we support today.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv: Advertise support for VK_KHR_storage_buffer_storage_class

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir/spirv: Add support for SPV_KHR_variable_pointers

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir/spirv: Add a helper for pushing SSA values

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir/spirv: Implement OpPtrAccessChain for buffers

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

spirv/nir: Add some useful asserts for type decorations

Now that vtn_type has piles of unions, we should assert sanity before
setting fields that may stomp others.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

spirv: Add support for the StorageBuffer storage class

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

spirv: Generate spirv_info.c

The old table based spirv_*_to_string functions would return NULL for
any values "inside" the table that didn't have entries.  The tables also
needed to be updated by hand each time a new spirv.h was imported.
Generate the file instead.

v2: Make this script work more like src/mesa/main/format_fallback.py.
Suggested by Jason.  Remove SCons supports.  Suggested by Jason and
Emil.  Put all the build work in Makefile.nir.am in lieu of adding a new
Makefile.spirv.am.  Suggested by Emil.  Add support for Android builds
based on code provided by Emil.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

spirv: Import the lastest 1.0.2 JSON from Khronos

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>

spirv: Import the latest 1.2 header from Khronos

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

mesa: whitespace fixes in get.c

Remove trailing whitespace.
Replace tabs with spaces.
Trivial.

mesa: fix GL_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION_EXT query

This query is not allowed in GL core profile 3.3 and later (since
GL_QUADS and GL_QUAD_STRIP are disallowed).  The query was (mistakenly)
supported in GL 3.2.  This fixes the glGet error test accordingly.

Reviewed-by: Neha Bhende<bhenden@vmware.com>

vulkan/util: fix typo in comment

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

mapi: add missing no_error tag to glBlitNamedFramebuffer()

Fixes: 6fedb31785 ("mesa: add KHR_no_error support for glBlitNamedFramebuffer()")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radv: Set the RADEON_SURF_OPTIMIZE_FOR_SPACE flag for images

This looks like a regression from df301237940 ("radv: use
ac_compute_surface"). Before that, the opt4Space addrlib flag was set
to true unless the image has FMASK (ac_compute_surface will similarly
only set that flag for images without FMASK).

This saves multiple gigabytes of VRAM on one of our games, and brings
its VRAM utilisation on RADV in line with AMDGPU-PRO and NVIDIA.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: don't shadow meta_va.

Coverity warned about dead code below, as meta_va was being shadowed.

Signed-off-by: Dave Airlie <airlied@redhat.com>

i965: Delete brw_sf_state.c again

"...and stay dead!"

Rafael deleted this file in c2b5a26dc25b9c62954a75465e25294c7fd3851a
(i965: Convert SF_STATE to genxml.) but Marek accidentally brought it
back in commit e7a091936fb6fd578c6ced9baa38b306b638a11b (mesa: replace
ctx->Polygon._FrontBit with a helper function) when resolving conflicts.

It's not actually even compiled, but it's still here trolling people
into thinking it still exists and needs patching.

ac/nir: rewrite shared variable handling (v2)

Translate the NIR variables directly to LLVM instead of lowering to a
TGSI-style giant array of vec4's and then back to a variable. This
should fix indirect dereferences, make shared variables more tightly
packed, and make LLVM's alias analysis more precise. This should fix an
upcoming Feral title, which has a compute shader that was failing to
compile because the extra padding made us run out of LDS space.

v2: Combine the previous two patches into one, only use this for shared
variables for now until LLVM becomes smarter.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Alex Smith <asmith@feralinteractive.com>

i965: Check if the modifier is supported in select_best_modifier

Otherwise, if a client gave us a list of modifiers that contained a
modifier we understand but which is not supported on the hardware, we
might return that one and then fail to create the image.

Reviewed-by: Daniel Stone <daniels@collabora.com>

i965: Rework the modifier info map

This commit splits the mapping in half.  The modifier_infos table now
only contains the modifier and the since_gen field.  The tiling bits
have been moved into a table in tiling_to_modifier as that's the only
place it was ever used.  The modifier_is_supported function now takes a
devinfo and does the since_gen check.

Reviewed-by: Daniel Stone <daniels@collabora.com>

i965/surface_state: Remove the mcs_buf->offset == 0 restriction

This assert was removed in b0cc55f29831638069407a4c1a5c809b26902ab6 but
got added back in 1a43d774b613d0b00e26b28cc752d944ce8049aa, probably by
accident.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add a row_pitch parameter to surf_get_ccs_surf

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/miptree: Use BO_ALLOC_ZEROED for CCS_E buffers

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/screen: Allocate ZEROED BOs for images

Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/bufmgr: Add a BO_ALLOC_ZEROED flag

Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/miptree: Replace is_lossless_compressed with mt->aux_usage checks

Now that we have an actual aux_usage field, we no longer need the
complex logic of is_lossless_compressed in order to figure out if a
miptree is CCS_E compressed.  As a side-effect, there is not longer any
need to overload MSAA_LAYOUT_CMS for CCS_E and we can stop doing so.

Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/miptree: Allocate HiZ up-front

HiZ, like MCS and CCS_E, can compress more than just clear colors so we
want it turned on whenever the miptree is being used as a depth
attachment.  It's theoretically possible for someone to create a depth
texture, upload data with glTexSubImage2D, and texture from it without
ever binding it as a depth target.  If this happens, we would end up
wasting a bit of space by allocating a HiZ surface we never use.
However, this is rather unlikely out side of test cases, so we're better
off just allocating it up-front.

Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/miptree: Add an intel_tiling_supports_hiz helper

We need this split for the same reason that we need the split for CCS:
intel_miptree_supports_hiz is called *before* we choose the actual
tiling.  Adding a tiling_supports_hiz helper lets choose_aux_usage
more accurately decide whether or not to enable hiz.  In particular,
this prevents us from enabling HiZ on linear depth buffers.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/miptree: Gather initial aux allocation into a single function

Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

st/mesa: init winsys buffers list only if context creation succeeds

Fixes piglit test crash when context creation fails.

v2: As suggested by Brian, move the init to st_create_context_priv()

Reviewed-by: Brian Paul <brianp@vmware.com>

winsys/svga/drm: Enable import/export fence FD

Enable the capability if the DRM supports it.

Hook up mechanism to send and receive fence FD from the DRM.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

winsys/svga/drm: Connect winsys-side fence_* functions

Connect fence_get_fd, fence_create_fd, and fence_server_sync.

Implement the required functions in vmw_fence module.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

drivers/svga: Connect driver-side fence_* functions

Connect fence_get_fd, fence_create_fd, and fence_server_sync.
Return PIPE_CAP_NATIVE_FENCE_FD capability based on what the
winsys reports

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

winsys/svga/drm: Create winsys interface for Fence FD

The new interfaces will be used to enable
EGL_ANDROID_native_fence_sync.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

winsys/svga/drm: Prepare to support fence fd

Make the fields and flags available.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

drivers/svga, winsys/svga/drm: Thread through timeout for fence_finish

The timeout parameter is required to implement
EGL_ANDROID_native_fence_sync.

v2
* Replaced default timeout from 0 to PIPE_TIMEOUT_INFINITE
* Add more documentation to the new timeout parameter

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: whitespace clean-up in svga_winsys.h

Trivial.

svga: add some const qualifiers

Trivial.

svga: add comment about 'extra' constant locations

Trivial.

anv/image: Add INPUT_ATTACHMENT to the list of required usages

From the Vulkan 1.0.53 spec VU for vkCreateImageView:

    "image must have been created with a usage value containing at least
    one of VK_IMAGE_USAGE_SAMPLED_BIT, VK_IMAGE_USAGE_STORAGE_BIT,
    VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
    VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT, or
    VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT"

We were missing VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT from out list.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org

anv: Stop leaking the no_aux sampler surface state

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org

anv/cmd_buffer: Properly handle render passes with 0 attachments

We were early returning and never created the NULL surface state.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: James Legg <jlegg@feralinteractive.com>
Cc: mesa-stable@lists.freedesktop.org

radeonsi/gfx9: add VM fault dmesg parser support

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: automatically resize shader compiler thread queues when they are full

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: prevent a deadlock in util_queue_add_job with too many GL contexts

If the queue is full, util_queue_add_job will wait while bo_fence_lock is
held.

It pb_slab wants to reuse a buffer, it will lock the pb_slab mutex and
try to check BO fence busyness, but it has to wait for bo_fence_lock to get
released. Both bo_fence_lock and pb_slab mutex are locked now.

When the CS thread unreferences and releases a suballocated buffer,
it will try to lock the pb_slab mutex and has to wait. The CS thread
can't finish its job in order to free a queue slot and unblock
util_queue_add_job ==> deadlock.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

util/u_queue: add an option to resize the queue when it's full

Consider the following situation:
  mtx_lock(mutex);
  do_something();
  util_queue_add_job(...);
  mtx_unlock(mutex);

If the queue is full, util_queue_add_job will wait for a free slot.
If the job which is currently being executed tries to lock the mutex,
it will be stuck forever, because util_queue_add_job is stuck.

The deadlock can be trivially resolved by increasing the queue size
(reallocating the queue) in util_queue_add_job if the queue is full.
Then util_queue_add_job becomes wait-free.

radeonsi will use it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: expose ARB_timer_query unconditionally

clock_crystal_freq is always non-zero now.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/gpu_info: if clock crystal frequency is 0, print an error and set 1

During bring-up, this is often 0. Prevent automatic disablement of
ARB_timer_query and demotion of the OpenGL version to 3.2 by setting
a non-zero frequency. Print an error message instead.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't read back non-existent register SRBM_STATUS2

It looks like there is no way to monitor SDMA busyness on GFX9.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: prevent a crash with DBG_CHECK_VM and u_threaded_context

by setting PIPE_CONTEXT_DEBUG in the caller

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface/gfx9: flags.texture currently refers to TC-compatible HTILE

This should lead to better MSAA performance on GFX9.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: simplify computation of tessellation offchip buffers

This is overly cautious, but better safe than sorry.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add workarounds to avoid VGPR indexing completely

For inputs and outputs, indirect indexing is lowered by the GLSL compiler.
For temporaries, use alloca and disable the "promote-alloca" pass.

In the future, we could switch all codepaths to alloca permanently and
just rely on the "promote-alloca" pass.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: emit param exports after position exports

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move building parameter exports into a separate function

Both loops now look simple.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't use info.num_inputs when it's unused

For clarity. It's only used by color interpolation.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add si_build_fs_interp helper

This is much simpler.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: merge si_llvm_get_amdgpu_target into ac_get_llvm_target

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallivm: inline gallivm_init_llvm_targets

there is only one user.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't call gallivm_init_llvm_targets

It's for initializing the native (x86) target.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: reallocate suballocated buffers when exported

This should fix exports of suballocated buffers.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: flush the context after in-place texture realloc before export

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/va: Fix scaling list ordering for H.265

Mesa here requires the scaling lists in diagonal scan order, but
VAAPI passes them in raster scan order.  Therefore, rearrange the
elements when copying.

v2: Move scan tables to vl_zscan.c.
    Fix type in size assertion.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Mark Thompson <sw@jkqxz.net>
Reviewed-by: Christian König <christian.koenig@amd.com>

radv: advertise v6 of the wayland surface extension

Jason updated the Khronos spec to explicitly state that Wayland surfaces
must support VK_PRESENT_MODE_MAILBOX_KHR.

ANV did so since day one (back in 2015)

Cc: mesa-stable@lists.freedesktop.org
Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: Dave Airlie <airlied@redhat.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: advertise v6 of the wayland surface extension

Jason updated the Khronos spec to explicitly state that Wayland surfaces
must support VK_PRESENT_MODE_MAILBOX_KHR.

ANV did so since day one (back in 2015)

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: use strtol to convert the integer deviceID override

One can override the deviceID, by setting the INTEL_DEVID_OVERRIDE
variable. A few symbolic names or a numerical value for the actual
device ID is accepted.

At the same time we're using strtod (string to double) to convert the
string to a decimal numeral. A seeming thinko, made by the original
commit that introduces the code in libdrm_intel and got here with the
import.

Fixes: 514db96c117a ("i965: Import libdrm_intel.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gallium/u_blitter: don't use TXF for scaled blits

There seems to be a rounding difference with F2I vs nearest filtering.
The precise problem in the rounding is unknown.

This fixes an incorrect output with OpenMAX encoding.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

anv: ensure device name contains terminating character

v2: Use sizeof() (Chris)

CID: 1415113
Reported-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

i965: miptree: silence coverity warning

This probably can't happen, but we're better off with initialized
variables.

CID: 1415114
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

mesa: flag _NEW_TEXTURE_OBJECT for GL_TEXTURE_LOD_BIAS_EXT

Only the compatibility profile can set it.
It was done incorrectly when we split _NEW_TEXTURE.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

meta: Actually initialize ImmutableLevels to 1.

Otherwise, ImmutableLevels is 0, which is an illegal value.  Later,
_mesa_meta_setup_sampler will use _mesa_texture_parameteriv to set

   texObj->MaxLevel = CLAMP(params[0], texObj->BaseLevel,
                            texObj->ImmutableLevels - 1);

which turns into a completely bogus CLAMP(value, 0, -1)...where the
upper bound is smaller than the lower bound.  This ends up being -1
today due to the way CLAMP is implemented, which is a bogus MaxLevel.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

dri: Make classic drivers allow __DRI_CTX_FLAG_NO_ERROR.

Grigori recently added EGL_KHR_create_context_no_error support,
which causes EGL to pass a new __DRI_CTX_FLAG_NO_ERROR flag to
drivers when requesting an appropriate context mode.

driContextSetFlags() will already handle it properly for us, but the
classic drivers all have code to explicitly balk at unknown flags.  We
need to let it through or they'll fail to create a no_error context.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>

ddebug: fix parsing of the pipelined mode

Trivial.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radv: predicate cmask eliminate when using DCC.

When using DCC some clear values don't require a cmask eliminate
step. This patch adds support for black and black with alpha 1,
there are other values, but I don't have access to a comprehensive list.

This works by setting the cmask eliminate predicate when doing the
fast clear, and later when doing the cmask elimination making sure
the draws are predicated.

This increases the fps on Sascha Willems deferred.

Tonga: 580fps->670fps on a Tonga PRO card.
Polaris 730->850fps

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/clear: add r32g32b32a32 fast clear support (v2)

We can only fast clear 128-bit images if the r/g/b channels
are the same, and we are using DCC.

For DCC we'll bail out on translate if this isn't true,
and we catch cmask clears explicitly.

v2: remove 64-bit block (Bas), add uint32 as well.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

amd/addrlib: fix typo in api name.

This fixes the misspelling of ALIGNMENTS in addrlib.

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: set cb base tile swizzles for MRT speedups (v4)

This patch uses addrlib to workout the tile swizzles according
to the surface index. It seems to produce the same values as
amdgpu-pro for the deferred test.

v2: don't apply swizzle to CMASK. the eg docs don't mention
it, and we clearly don't align cmask for that.
v3: disable surf index for dedicated images, as these will
most likely be shared, and I don't think the metadata has
space for this info in it yet.
v4: update for shareable images, rename combined_swizzle
to tile_swizzle

This gets the deferred demo from 730->950fps on my rx480.
(dcc cmask elim predication patches get it further)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: allow clear merging for depth/stencil with no care stencil

Some of the Sascha Willems demos pick a D32/S8 format for the depth
buffer, then do a LOAD_OP_CLEAR/LOAD_OP_DONT_CARE on it, which means
we don't get to merge the undefined->depth and clear htile transitions.

This add the stencil aspect to the pending clears if there is a depth
clear pending and the stencil aspect is don't care.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Remove NV dedicated alloc extension.

To not confuse apps in thinking it might be faster.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>