i965: Remove duplicate #includes.

Added in commits 36fd65381 and 337dad8ce even though the existing
include was in view.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Remove unneeded forward declarations.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Mark count_trailing_one_bits() static.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Remove useless gen6_blorp.h/gen7_blorp.h headers.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

util: Include assert.h in macros.h.

util: Include <stdbool.h> in debug.h.

i965: Prevent implicit upcasts to brw_reg.

Now that backend_reg inherits from brw_reg, we have to be careful to
avoid the object slicing problem.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: Use scope operator to ensure brw_reg is interpreted as a type.

In the next patch, I make backend_reg's inheritance from brw_reg
private, which confuses clang when it sees the type "struct brw_reg" in
the derived class constructors, thinking it is referring to the
privately inherited brw_reg:

brw_fs.cpp:366:23: error: 'brw_reg' is a private member of 'brw_reg'
fs_reg::fs_reg(struct brw_reg reg) :
                      ^
brw_shader.h:39:22: note: constrained by private inheritance here
struct backend_reg : private brw_reg
                     ^~~~~~~~~~~~~~~
brw_reg.h:232:8: note: member is declared here
struct brw_reg {
       ^

Avoid this by marking brw_reg with the scope resolution operator.

i965: Use implicit backend_reg copy-constructor.

In order to do this, we have to change the signature of the
backend_reg(brw_reg) constructor to take a reference to a brw_reg in
order to avoid unresolvable ambiguity about which constructor is
actually being called in the other modifications in this patch.

As far as I understand it, the rule in C++ is that if multiple
constructors are available for parent classes, the one closest to you in
the class heirarchy is closen, but if one of them didn't take a
reference, that screws things up.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: Add and use backend_reg::equals().

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

softpipe/llvmpipe: don't advertize support for ASTC

33339775565154040e0c4ea2e196217dccc08cdf added support for ASTC textures to
gallium. They don't have any helpers hooked up for software decoding, however,
so cannot support them in drivers relying on util code for decoding.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

llvmpipe: don't test for unsupported formats in lp_test_format

Removing the fake format helpers (1c7d0a6aa4f5cb38af7e281e1e5437cd1a20f781)
caused this to fail. These formats were never supported, but previously
they would have asserted in the generated jit functions (which, due to lack
of test cases for these formats, were never called) whereas we now assert when
trying to build the jit function. So, skip them completely.

This fixes https://bugs.freedesktop.org/show_bug.cgi?id=93092

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

docs: add missed i965 feature to relnotes

Trivial.  GL_ARB_fragment_layer_viewport support was added in 8c902a58
by Ken.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>

util: move brw_env_var_as_boolean() to util

Kind of a handy function.  And I'll want it available outside of i965
for common nir-pass helpers.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Nicolai Hähnle <nhaehnle@gmail.com>

st/va: fix indentation

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

st/va: move MPEG4 functions into separate file

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

st/va: move VC-1 functions into separate file

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

st/va: move H264 functions into separate file

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

st/va: move MPEG12 functions into separate file

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

st/va: move post processing function into own file

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

st/va: fix post process dirty area handling

The dirty area in this call isn't related to the screen at all.

v2: set clear dirty area to false as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

glsl: implement recent spec update to SSO validation

Enables 200+ dEQP SSO tests to proceed past validation,
and fixes a ES31-CTS.sepshaderobjs.PipelineApi subtest.

V2: split out change that reverts a previous patch into its own commit,
move variable declaration to top of function, and fix some formatting
all suggested by Ian.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>

Revert "mesa: return initial value for VALIDATE_STATUS if pipe not bound"

This reverts commit ba02f7a3b6a0e4314753a8e5080db61241563f9c.

The commit checked whether the pipeline was currently bound instead
of checking whether it had ever been bound.  The previous setting
of Validated during object creation makes this unnecessary.  The
real problem was that Validated was not properly set to false
elsewhere in the code.  This is fixed by a later patch.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>

radeon/llvm: Use llvm.AMDIL.exp intrinsic again for now

llvm.exp2.f32 doesn't work in some cases yet.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92709

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeon/uvd: uv pitch separation for stoney

v2: set the behaviour default for future ASICs.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Cc: mesa-stable@lists.freedesktop.org

texgetimage: consolidate 1D array handling code.

This should fix the getteximage-depth test that currently asserts.

I was hitting problem with virgl as well in this area.

This moves the 1D array handling code to a single place.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

i965: Use NIR for lowering texture swizzle

Now that nir_lower_tex can do texture swizzle lowering, we can use that
instead of repeating more-or-less the same code in both backends.  This
both allows us to share code and means that things like the tg4
work-arounds are somewhat simpler because they don't have to take the
swizzle into account.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir/lower_tex: Add support for lowering texture swizzle

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: Add a tex_instr_is_query helper

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: Add a ssa_def_rewrite_uses_after helper

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: Use instr/if_rewrite in nir_ssa_def_rewrite_uses

nir_ssa_def_rewrite_uses is one of the older helpers in NIR and predated
both of those.  Now it can be substantially simplified.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir/validate: Validated dests after sources

Previously, if someone accidentally made an instruction that refers to its
own SSA destination, the validator wouldn't catch it.  The reason for this
is that it validated the destination too early and, by the time it got to
the source, the destination SSA value was already added to the set of seen
SSA values so it would assume that it came from some previous instruction.
By moving destination validation to be after source validation, the SSA
value is not in the list of seen values and the validator will catch
self-referential instructions.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

i965: Use nir_lower_tex for texture coordinate lowering

Previously, we had a rescale_texcoords helper in the FS backend for
handling rescaling of texture coordinates.  Now that we can do variants in
NIR, we can use nir_lower_tex to do the rescaling for us.  This allows us
to delete the i965-specific code and gives us proper TEXTURE_RECTANGLE and
GL_CLAMP handling in vertex and geometry shaders.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Stomp the texture return type to UINT32 for resinfo messages

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir/lower_tex: Set the dest_type for txs instructions

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir/lower_tex: Report progress

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Move postprocess_nir to codegen time

This allows us to insert NIR passes between initial NIR compilation and
optimization (link time) and actual backend code-gen.  In particular, it
will allow us to do shader variants in NIR and share some of that shader
variant code between backends.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965/nir: Split shader optimization and lowering into three stages

At the moment, brw_create_nir just calls the three stages in sequence so
there's not much difference.  Soon, however, we will want to start doing
variants in NIR at which point the postprocessing step will have to move
from shader create time to codegen time.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Use ull immediates in brw_inst_bits

This fixes a regression introduced in b1a83b5d1 that caused basically all
shaders to fail to compile on 32-bit platforms.

Reported-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

docs: add missed freedreno features to relnotes

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>

docs: update relnotes with new freedreno/a4xx support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

svga: Add ASTC formats to format table.

Fixes build.  Otherwise untested.

Trivial.

freedreno/ir3: add support for a few gs5 ops

Tested on a4xx. This is part of the builtins added by ARB_gpu_shader5
and GLSL ES 3.10.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

ttn: fix UMSB conversion

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: add ARB_texture_query_lod support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

ttn: add LODQ support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: re-emit program on dirty framebuffer

The program emit depends on certain fb details. Make sure those get
updated when the fb changes.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: use a factor of 32767 for snorm8 blending

It appears that the hardware wants the integer to be scaled the same way
that the hardware representation is. snorm16 uses one of the float
factors, so this is only relevant for snorm8.

This fixes a number of subcases of
  bin/fbo-blending-formats GL_EXT_texture_snorm

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

freedreno/a4xx: only compute texture offset once for the view

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: add ARB_texture_view support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: add formats for ARB_texture_buffer_object_rgb32 support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: add ARB_texture_rgb10_a2ui support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: add astc formats

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: add astc support

This doesn't account for the ldr/hdr distinction... that will probably
have to be exposed via a separate cap. When relevant hardware appears,
this can be worked out.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: add ASTC formats

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium/util: remove the fake format helpers for bptc and etc2

This was a silly hack that kept growing and growing. Instead, just write
NULLs for those functions. No need to have helpers that just assert(0)
when you call them.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

freedreno/a4xx: support 16384 texels in buffer texture

Looks like the width field's bitmask was off-by-one.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: add ARB_texture_buffer_range support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: add polygon mode support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

configure.ac: default to disabled dri3 when --disable-dri is set

Not too long ago, the dri3 code was living in src/glx, which in itself
was guarded by HAVE_DRI_GLX. As the name suggests we didn't dive into
the folder when dri was disabled, thus we missed that dri3 does not
consider/honour --enable-dri.

Cc: mesa-stable@lists.freedesktop.org
Fixes: 6bd9ba7d074 "loader: Add dri3 helper"
Cc: Pali Rohár <pali.rohar@gmail.com>
Reported-by: Pali Rohár <pali.rohar@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

loader: unconditionally add AM_CPPFLAGS to libloader_la_CPPFLAGS

It seems that due to the conditional autotools is getting confused and
forgetting to add AM_CPPFLAGS when building libloader (when
HAVE_DRICOMMON is not set).

Cc: mesa-stable@lists.freedesktop.org
Fixes: 5a79e0a8e37 "automake: loader: rework the CPPFLAGS"
Reported-by: Pali Rohár <pali.rohar@gmail.com>
Tested-by: Pali Rohár <pali.rohar@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

pipe-loader: link against libloader regardless of libdrm presence

Whether or not the loader has libdrm support is up-to it. Anyone using
the loader should just include it whenever they depend on it.

Cc: mesa-stable@lists.freedesktop.org
Fixes: 0f39f9cb7ad "pipe-loader: add a dummy 'static' pipe-loader"
Reported-by: Jon TURNEY <jon.turney@dronecode.org.uk>
Tested-by: Jon TURNEY <jon.turney@dronecode.org.uk>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

i965: Handle lum, intensity and missing components in the fast clear

It looks like the sampler hardware doesn't take into account the
surface format when sampling a cleared color after a fast clear has
been done. So for example if you clear a GL_RED surface to 1,1,1,1
then the sampling instructions will return 1,1,1,1 instead of 1,0,0,1.
This patch makes it override the color that is programmed in the
surface state in order to swizzle for luminance and intensity as well
as overriding the missing components.

Fixes the ext_framebuffer_multisample-fast-clear Piglit test.

v2: Handle luminance and intensity formats
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

nir: s/nir_type_unsigned/nir_type_uint

v2: do the same in tgsi_to_nir (Samuel)

v3: added missing cases after rebase (Iago)

v4: Add a blank space after '#' in one of the comments (Matt)

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nir/builder: only read meaningful channels in nir_swizzle()

This way the caller doesn't have to initialize all 4 channels when they
aren't using them.

v2: Fix signed/unsigned comparison warning (Iago)

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: add stride restrictions for copy propagation

There are various restrictions on what the hstride can be that depend on
the Gen, and now that we're using hstride == 2 for packing/unpacking
doubles, we're going to run into these restrictions a lot more often.
Pull them out into a separate function, and move the one restriction we
checked previously into it.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: don't propagate cmod when the exec sizes differ

This can happen when the source of the compare was split by the SIMD
lowering pass. Potentially, we could allow the case where the exec size
of scan_inst is larger, and scan_inst has the right quarter selected,
but doing that seems a little more risky.

v2: Merge the bail condition into the the previous if/break block (Matt)

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: respect force_sechalf/force_writemask_all in CSE

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: fix 64-bit immediates in brw_inst(_set)_bits

If we tried to get/set something that was exactly 64 bits, we would
try to do (1 << 64) - 1 to calculate the mask which doesn't give us all
1's like we want.

v2 (Iago)
 - Replace ~0 by ~0ull
 - Removed unnecessary parenthesis

v3 (Kristian)
 - Avoid the conditional

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: print non-1 strides when dumping instructions

v2:
  - Simplify code (Iago)

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nv50/ir: fix (un)spilling of 3-wide results

There is no 96-bit load/store operations, so we have to split it up
into a 32-bit parts, with a split/merge around it.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90348
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>

glsl: fix max binding validation for uniform blocks

Regression as of 64710db66461e

We can't use the type returned by get_interface_type() as
the interface type has arrays removed.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

nv50,nvc0: properly handle buffer storage invalidation on dsa buffer

In case that the buffer has no bind at all, assume it can be a regular
buffer. This can happen on buffers created through the ARB_dsa
interfaces.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>

nouveau: use the buffer usage to determine placement when no binding

With ARB_direct_state_access, buffers can be created without any binding
hints at all. We still need to allocate these buffers to VRAM or GART,
as we don't have logic down the line to place them into GPU-mappable
space. Ideally we'd be able to shift these things around based on usage.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92438
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>

vc4: Take precedence over ilo when in simulator mode.

They're exclusive at build time, but the ilo entry is always present, so
we'd try to use it and fail out.

v2: Add comment in the code, from Emil.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

vc4: Just put USE_VC4_SIMULATOR in DEFINES.

In the pipe-loader reworks, it was missed in one of the new directories it
was used.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

mesa/teximage: Fix S3TC regression due to ASTC interaction

A prior, literal reading of the ASTC spec led to the prohibition
of some compressed formats being used against the targets:
TEXTURE_CUBE_MAP_ARRAY and TEXTURE_3D. Since the spec does not specify
interactions with other extensions for specific compressed textures,
remove such interactions.

Fixes the following Piglit tests on Gen9:
piglit.spec.arb_direct_state_access.getcompressedtextureimage
piglit.spec.arb_get_texture_sub_image.arb_get_texture_sub_image-getcompressed
piglit.spec.arb_texture_cube_map_array.fbo-generatemipmap-cubemap array s3tc_dxt1
piglit.spec.ext_texture_compression_s3tc.getteximage-targets cube_array s3tc

v2. Don't interact with other specific compressed formats (Ian).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91927
Suggested-by: Neil Roberts <neil@linux.intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa/extensions: Enable overriding permanently enabled extensions

Provide the ability to prevent any permanently enabled extension
from appearing in the string returned by glGetString[i]().

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Brian Paul <brianp@vmware.com>

virgl: pipe_virgl_create_screen is not static

Cc: mesa-stable@lists.freedesktop.org
Fixes: 17d3a5f8579 "target-helpers: add a non-inline drm_helper.h"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93063
Signed-off-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

i965: Fix num_uniforms count for scalar GS.

I noticed that brw_vs.c does this.

I believe the point is that nir->num_uniforms is either counted in
scalar components (in scalar mode), or vec4 slots (in vector mode).
But we want param_count to be in scalar components regardless, so
we have to scale up in vector mode.

We don't have to scale up in scalar mode, though.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

vc4: Use nir_channel() to simplify all of our nir_swizzle() cases.

vc4: Fix point size lookup.

I think I may have regressed this in the NIR conversion.  TGSI-to-NIR is
putting the PSIZ in the .x channel, not .w, so we were grabbing some
garbage for point size, which ended up meaning just not drawing points.

Fixes glean pointAtten and pointsprite.

pipe-loader: Fix PATH_MAX define on MSVC.

scons: Conditionally use DRM module on pipe-loader.

Fixes non Linux builds.

Trivial.

freedreno/a4xx: disable blending and alphatest for integer rt0

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

freedreno/a4xx: fix independent blend

This fixes the ext_draw_buffers2 and arb_draw_buffers_blend tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

freedreno/a4xx: enable ARB_base_instance support

We already pass in start_instance in fd4_draw. Expose the extension.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: set fetchsize in mem2gmem texture restore

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: add 11_11_10_float vertex type support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: fix 3d texture setup

Same fix as on a3xx - set the second (tiny) layer size bitfield to the
smallest level's size so that the hw knows not to minify beyond that.

This fixes texelFetch sampler3D piglits.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

freedreno/a4xx: only align slices in non-layer_first textures

When layer is the container, slices are tightly packed inside of each
layer. We don't need any additional alignment. On a3xx, each slice
contains all the layers, so having alignment makes sense.

This fixes a whole slew of array-related piglits, including texelFetch
and tex-miplevel-selection varieties.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

docs: add 11.2.0-devel release notes template, bump version

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

util: use RTLD_LOCAL with util_dl_open()

Otherwise we risk things blowing up due to conflicting symbols.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Rob Clark <robclark@freedesktop.org>

targets/nine: remove unused static functions

Dead code since commit 8f50614910c40366d94964fe2c5da5772aff2f96

Cc: Axel Davy <axel.davy@ens.fr>
Cc: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Rob Clark <robclark@freedesktop.org>

targets/nine: add note about messy header inclusion order

Cc: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Rob Clark <robclark@freedesktop.org>

targets/nine: add note about fd owndership

v2:
 - move autotools hunk into correct patch
 - correct the note based on Axel's feedback

Cc: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Rob Clark <robclark@freedesktop.org>

auxiliary/vl: Don't close the drm fd on failure

Ported from an identically named commit in st/xa

commit 35cf3831d71770211f29da6608313dc1f6213d7b
Author: Thomas Hellstrom <thellstrom@vmware.com>
Date:   Thu Jul 3 02:07:36 2014 -0700

    st/xa: Don't close the drm fd on failure v2

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Rob Clark <robclark@freedesktop.org>

st/dri: NULL check the pscreen earlier

We delay the null check only to jump through hoops to work around that.
Check early to make our lives easier.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Rob Clark <robclark@freedesktop.org>

st/dri: Don't close the drm fd on failure

Ported from an identically named commit in st/xa

commit 35cf3831d71770211f29da6608313dc1f6213d7b
Author: Thomas Hellstrom <thellstrom@vmware.com>
Date:   Thu Jul 3 02:07:36 2014 -0700

    st/xa: Don't close the drm fd on failure v2

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Rob Clark <robclark@freedesktop.org>

target-helpers: remove inline_drm_helper.h

As of earlier all the targets use the non inline version. Don't forget
to remove the function prototypes/declarations.

v2: rebase on top of virgl support.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Rob Clark <robclark@freedesktop.org>