openpower-isa.git
20 months agoadd maxs. combined with cmp capability
Luke Kenneth Casson Leighton [Mon, 24 Oct 2022 09:54:53 +0000 (10:54 +0100)]
add maxs. combined with cmp capability
https://bugs.libre-soc.org/show_bug.cgi?id=915

20 months agouse svshape2 instead of svindex for the 4th shape
Luke Kenneth Casson Leighton [Sun, 23 Oct 2022 09:52:15 +0000 (10:52 +0100)]
use svshape2 instead of svindex for the 4th shape
(cycling through modulo4 shifts) as there is no
change of order, svindex wastes a regfile lookup
chacha20

21 months agoadd extra pysvp64dis tests for divmod2du and maddedu
Luke Kenneth Casson Leighton [Sat, 22 Oct 2022 16:37:04 +0000 (17:37 +0100)]
add extra pysvp64dis tests for divmod2du and maddedu

21 months agoargh, extremely annoying: 4-operand dsld/dsrd is not possible to
Luke Kenneth Casson Leighton [Sat, 22 Oct 2022 16:32:41 +0000 (17:32 +0100)]
argh, extremely annoying: 4-operand dsld/dsrd is not possible to
have EXTRA3, therefore it fails as a bigint operation. reverting

21 months agoremove redundant case_dsrd3
Luke Kenneth Casson Leighton [Sat, 22 Oct 2022 16:16:26 +0000 (17:16 +0100)]
remove redundant case_dsrd3

21 months agobigint shuffle
Luke Kenneth Casson Leighton [Sat, 22 Oct 2022 16:15:17 +0000 (17:15 +0100)]
bigint shuffle
* divmod2du moves to XO=58 (from XO=52)
* dsld/dsrd become Rc=1 and move to XO=52-55 in VA2-Form
* dsld/dsrd pseudocode no longer is overwrite with "sm" mode
* Z23 "sm" removed from fields.txt

21 months agofix get_masked_reg and add test
Jacob Lifshay [Sat, 22 Oct 2022 00:46:58 +0000 (17:46 -0700)]
fix get_masked_reg and add test

21 months agoformat code removing unused imports
Jacob Lifshay [Fri, 21 Oct 2022 23:37:14 +0000 (16:37 -0700)]
format code removing unused imports

21 months agocode-comments
Luke Kenneth Casson Leighton [Fri, 21 Oct 2022 12:29:07 +0000 (13:29 +0100)]
code-comments

21 months agoadd 2nd outer loop, CTR 2 rounds, in chacha20 test
Luke Kenneth Casson Leighton [Fri, 21 Oct 2022 12:00:41 +0000 (13:00 +0100)]
add 2nd outer loop, CTR 2 rounds, in chacha20 test

21 months agomove chacha20 to separate test, set/get masked regs to ISACaller
Luke Kenneth Casson Leighton [Fri, 21 Oct 2022 11:47:41 +0000 (12:47 +0100)]
move chacha20 to separate test, set/get masked regs to ISACaller

21 months agomove HASK, ROTL32, ROTL64, MASK32, into helper class
Luke Kenneth Casson Leighton [Fri, 21 Oct 2022 11:29:33 +0000 (12:29 +0100)]
move HASK, ROTL32, ROTL64, MASK32, into helper class

21 months agouse XLEN/2 for ROTL32 in fixedshift.mdwn
Luke Kenneth Casson Leighton [Fri, 21 Oct 2022 11:28:43 +0000 (12:28 +0100)]
use XLEN/2 for ROTL32 in fixedshift.mdwn

21 months agocomments
Luke Kenneth Casson Leighton [Thu, 20 Oct 2022 17:49:32 +0000 (18:49 +0100)]
comments

21 months agoadd first chacha20 round test
Luke Kenneth Casson Leighton [Thu, 20 Oct 2022 16:27:59 +0000 (17:27 +0100)]
add first chacha20 round test

21 months agosv_binutils_fptrans: fix registers generation
Dmitry Selyutin [Wed, 19 Oct 2022 20:23:29 +0000 (23:23 +0300)]
sv_binutils_fptrans: fix registers generation

21 months agoav.mdwn: fix missing bmask operand
Dmitry Selyutin [Wed, 19 Oct 2022 18:23:15 +0000 (21:23 +0300)]
av.mdwn: fix missing bmask operand

21 months agoTODO, sort out remap indices order
Luke Kenneth Casson Leighton [Wed, 19 Oct 2022 10:49:51 +0000 (11:49 +0100)]
TODO, sort out remap indices order

21 months agoadd test for scalar sv.maddedu
Jacob Lifshay [Tue, 18 Oct 2022 05:49:42 +0000 (22:49 -0700)]
add test for scalar sv.maddedu

21 months agoadd missing files to .gitignore
Jacob Lifshay [Tue, 18 Oct 2022 05:49:28 +0000 (22:49 -0700)]
add missing files to .gitignore

21 months agoav.mdwn: fix Rc-augmented cprop instruction
Dmitry Selyutin [Mon, 17 Oct 2022 18:52:59 +0000 (21:52 +0300)]
av.mdwn: fix Rc-augmented cprop instruction

21 months agodebug print correction
Luke Kenneth Casson Leighton [Sun, 16 Oct 2022 11:24:50 +0000 (12:24 +0100)]
debug print correction

21 months agosigh, have to use yield from on get_out_map()
Luke Kenneth Casson Leighton [Sun, 16 Oct 2022 11:22:34 +0000 (12:22 +0100)]
sigh, have to use yield from on get_out_map()

21 months agorewrite get_idx_out2 in ISACaller to split out
Luke Kenneth Casson Leighton [Sun, 16 Oct 2022 11:08:56 +0000 (12:08 +0100)]
rewrite get_idx_out2 in ISACaller to split out
RS/out2 relationship

21 months agorewrite get_idx_out in ISACaller to split out
Luke Kenneth Casson Leighton [Sun, 16 Oct 2022 11:01:10 +0000 (12:01 +0100)]
rewrite get_idx_out in ISACaller to split out
RT/out relationship

21 months agoadd unit test showing two svindex calls, found bugs,
Luke Kenneth Casson Leighton [Sun, 16 Oct 2022 10:30:06 +0000 (11:30 +0100)]
add unit test showing two svindex calls, found bugs,
needs resolving in ISACaller.  REMAP application to RA/B/C/T/S is
not properly routing

21 months agocode-shuffle, rework get_idx_in() to separate out the in1/2/3 map
Luke Kenneth Casson Leighton [Sun, 16 Oct 2022 10:27:24 +0000 (11:27 +0100)]
code-shuffle, rework get_idx_in() to separate out the in1/2/3 map

21 months agowhoops missed an update MEM(EA...) in pifixedstore
Luke Kenneth Casson Leighton [Fri, 14 Oct 2022 20:37:08 +0000 (21:37 +0100)]
whoops missed an update MEM(EA...) in pifixedstore

21 months agosv_binutils_fptrans: fix opcodes mode
Dmitry Selyutin [Fri, 14 Oct 2022 19:17:35 +0000 (22:17 +0300)]
sv_binutils_fptrans: fix opcodes mode

21 months agopower_insn: really skip sv. entries for PPC database
Dmitry Selyutin [Fri, 14 Oct 2022 19:14:32 +0000 (22:14 +0300)]
power_insn: really skip sv. entries for PPC database

21 months agosv_binutils_fptrans: generate all permutations
Dmitry Selyutin [Fri, 14 Oct 2022 19:07:07 +0000 (22:07 +0300)]
sv_binutils_fptrans: generate all permutations

21 months agopysvp64asm: fix coding style
Dmitry Selyutin [Thu, 13 Oct 2022 13:59:27 +0000 (16:59 +0300)]
pysvp64asm: fix coding style

21 months agopower_insn: skip sv. instructions in PPC database
Dmitry Selyutin [Fri, 7 Oct 2022 12:16:05 +0000 (15:16 +0300)]
power_insn: skip sv. instructions in PPC database

21 months agopower_insn: fix AA match
Dmitry Selyutin [Fri, 7 Oct 2022 12:15:09 +0000 (15:15 +0300)]
power_insn: fix AA match

21 months agopower_insn: do not allow default records
Dmitry Selyutin [Fri, 7 Oct 2022 12:14:19 +0000 (15:14 +0300)]
power_insn: do not allow default records

21 months agoadd max-with-getting-index-of vertical-first loop example
Luke Kenneth Casson Leighton [Fri, 14 Oct 2022 13:14:53 +0000 (14:14 +0100)]
add max-with-getting-index-of vertical-first loop example

21 months agosmall update in the max detection code
Konstantinos Margaritis [Fri, 14 Oct 2022 10:34:05 +0000 (10:34 +0000)]
small update in the max detection code

21 months agoSVP64RMModeDecode detects Post-Inc LDST-imm mode
Luke Kenneth Casson Leighton [Fri, 14 Oct 2022 09:16:33 +0000 (10:16 +0100)]
SVP64RMModeDecode detects Post-Inc LDST-imm mode

21 months agocorrect comments
Luke Kenneth Casson Leighton [Thu, 13 Oct 2022 06:45:46 +0000 (07:45 +0100)]
correct comments

21 months agoadd in zeroing on test strncpy
Luke Kenneth Casson Leighton [Wed, 12 Oct 2022 21:47:48 +0000 (22:47 +0100)]
add in zeroing on test strncpy

21 months agoremove unneeded svstate from test
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 20:14:34 +0000 (21:14 +0100)]
remove unneeded svstate from test

21 months agoadd strncpy example - 6 instructions
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 16:09:54 +0000 (17:09 +0100)]
add strncpy example - 6 instructions

21 months agoadd sv.stwu/pi example in test_sv_load_store_postinc
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 14:17:45 +0000 (15:17 +0100)]
add sv.stwu/pi example in test_sv_load_store_postinc

21 months agoadd ld/st-immediate "post-inc" mode support. unit test for LD
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 13:11:04 +0000 (14:11 +0100)]
add ld/st-immediate "post-inc" mode support. unit test for LD

21 months agoadd /pi to sv/trans/svp64.py and power_insns.py
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 12:31:58 +0000 (13:31 +0100)]
add /pi to sv/trans/svp64.py and power_insns.py

21 months agoadd new LD-Immediate Post constants
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 12:30:56 +0000 (13:30 +0100)]
add new LD-Immediate Post constants

21 months agofirst working version
Konstantinos Margaritis [Fri, 14 Oct 2022 00:16:59 +0000 (00:16 +0000)]
first working version

21 months agoincrease buffer size, fix svp64 address for r5
Konstantinos Margaritis [Fri, 14 Oct 2022 00:16:37 +0000 (00:16 +0000)]
increase buffer size, fix svp64 address for r5

21 months agoadd sv.divmod2du test, inverse of the sv.madded
Luke Kenneth Casson Leighton [Wed, 12 Oct 2022 20:55:50 +0000 (21:55 +0100)]
add sv.divmod2du test, inverse of the sv.madded
using the same values

21 months agocomments clean-up on bigint big-mul case
Luke Kenneth Casson Leighton [Wed, 12 Oct 2022 15:04:21 +0000 (16:04 +0100)]
comments clean-up on bigint big-mul case

21 months agowhoops ea not ra in pifixedstore.mdwn
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 16:09:28 +0000 (17:09 +0100)]
whoops ea not ra in pifixedstore.mdwn

21 months agoadd Post-increment version of fixedstore.mdwn
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 14:05:58 +0000 (15:05 +0100)]
add Post-increment version of fixedstore.mdwn

21 months agoadd asciidump option to Mem class
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 16:09:08 +0000 (17:09 +0100)]
add asciidump option to Mem class

21 months agowhoops zero-error on masked-out
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 16:08:52 +0000 (17:08 +0100)]
whoops zero-error on masked-out

21 months agoWIP: add initial AV1 SVP64 porting
Konstantinos Margaritis [Tue, 11 Oct 2022 09:51:34 +0000 (09:51 +0000)]
WIP: add initial AV1 SVP64 porting

21 months agomove pypowersim_wrapper on its own
Konstantinos Margaritis [Tue, 11 Oct 2022 09:49:24 +0000 (09:49 +0000)]
move pypowersim_wrapper on its own

21 months agoadd experimental post-increment fixedload pseudocode
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 09:48:29 +0000 (10:48 +0100)]
add experimental post-increment fixedload pseudocode

21 months agoadd elwidth overrides on Indexed REMAP, 8-bit example. reduces reg usage
Luke Kenneth Casson Leighton [Mon, 10 Oct 2022 19:29:43 +0000 (20:29 +0100)]
add elwidth overrides on Indexed REMAP, 8-bit example. reduces reg usage

21 months agoadd elwidth overrides to get_idx_out2
Luke Kenneth Casson Leighton [Mon, 10 Oct 2022 19:02:59 +0000 (20:02 +0100)]
add elwidth overrides to get_idx_out2

21 months agofix format in debug log
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 23:35:34 +0000 (00:35 +0100)]
fix format in debug log

21 months agoforgot to add offset on GPR() get
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 23:32:05 +0000 (00:32 +0100)]
forgot to add offset on GPR() get

21 months agoadd elwidth overrides on destination (write) in ISACaller.
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 23:11:15 +0000 (00:11 +0100)]
add elwidth overrides on destination (write) in ISACaller.
first two unit tests pass (sv.add/ew=8, sv.add/ew=32)

21 months agosplit out base,offset in register decoding for elwidth overrides to work
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 20:14:24 +0000 (21:14 +0100)]
split out base,offset in register decoding for elwidth overrides to work
previously, calculating the register number was fine, it was straight
64-bit reg indexed.  however elwidths are *part-way* through registers
(packed) so need to compute the reg differently

21 months agoadd 8-bit elwidth alu svp64 case
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 19:42:17 +0000 (20:42 +0100)]
add 8-bit elwidth alu svp64 case

21 months agoadd rfscv to major_19.csv, add test_pysvp64dis.py unit test
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 13:37:33 +0000 (14:37 +0100)]
add rfscv to major_19.csv, add test_pysvp64dis.py unit test

21 months agodrat
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 13:29:20 +0000 (14:29 +0100)]
drat

21 months agoadd sc and scv support after moving from major.csv to extra.csv
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 13:28:00 +0000 (14:28 +0100)]
add sc and scv support after moving from major.csv to extra.csv
this now involves a laborious brute-force search looking for anything
with an extra.csv path, in order to prioritise the (full) 32-bit
pattern-match over e.g. MAJOR XO=17.
attn should also work (but currently does not, no idea why, possibly
because it should actually be in major.csv?

21 months agovector name "RSp" not recognised in sv.stq, added as example
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 12:26:09 +0000 (13:26 +0100)]
vector name "RSp" not recognised in sv.stq, added as example

21 months agoadd stq to CSV files and unit test to test_pysvp64dis.py
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 12:23:03 +0000 (13:23 +0100)]
add stq to CSV files and unit test to test_pysvp64dis.py

21 months agoseparate out DQ and DS to separate custom_immediates
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 12:14:13 +0000 (13:14 +0100)]
separate out DQ and DS to separate custom_immediates
D was unhappy about being a custom_field as an immediate.
better: create SignedImmediate class deriving from ImmediateOperand

21 months agouse new base-class EXTSOperand, derive from ImmediateOperand
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 12:11:33 +0000 (13:11 +0100)]
use new base-class EXTSOperand, derive from ImmediateOperand

21 months agoconvert TargetAddrOperand to base class EXTSOperand
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 11:45:30 +0000 (12:45 +0100)]
convert TargetAddrOperand to base class EXTSOperand
(about to do DQ/DS operand)

21 months agoadd lq and CONST_DQ
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 11:22:56 +0000 (12:22 +0100)]
add lq and CONST_DQ

21 months agorestore tests, accidentally disabled
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 10:11:28 +0000 (11:11 +0100)]
restore tests, accidentally disabled

21 months agoadd CY operand to fields.txt, in Z23-Form
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 10:09:39 +0000 (11:09 +0100)]
add CY operand to fields.txt, in Z23-Form
(missing from Power ISA v3.0B and v3.1 spec!)

21 months agoadd XER bits to register enums
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 10:04:05 +0000 (11:04 +0100)]
add XER bits to register enums

21 months agoadd addex to csv and sv_analysis db. also needs CryIn.OV enum
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 09:29:38 +0000 (10:29 +0100)]
add addex to csv and sv_analysis db. also needs CryIn.OV enum
added quick test_pysvp64dis.py test too

21 months agomisnamed instruction, lfiwzx
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 09:10:15 +0000 (10:10 +0100)]
misnamed instruction, lfiwzx

21 months agomore work on inssort. add useful reg-dump in ISACaller
Luke Kenneth Casson Leighton [Fri, 7 Oct 2022 12:47:03 +0000 (13:47 +0100)]
more work on inssort. add useful reg-dump in ISACaller

21 months agonope. failfirst needs to always save the result, but truncate VL *after*.
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 21:41:04 +0000 (22:41 +0100)]
nope.  failfirst needs to always save the result, but truncate VL *after*.
https://bugs.libre-soc.org/show_bug.cgi?id=936

21 months agofix fail-first to exclude failed element in VLi=0 mode
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 19:19:42 +0000 (20:19 +0100)]
fix fail-first to exclude failed element in VLi=0 mode

21 months agosort out CROPs fail-first in ISACaller. needed to take a copy of CR
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 17:34:38 +0000 (18:34 +0100)]
sort out CROPs fail-first in ISACaller.  needed to take a copy of CR
for when sv.cmp (and other pseudocode) *overwrites* CR and it needs
restoring (when VLI=0).  also needed to identify 3-bit and 5-bit
ffirst mode, and extract bottom 2 bits of BF

21 months agomake fail-first cope with sv.cmp which uses CR[BF]
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 16:26:24 +0000 (17:26 +0100)]
make fail-first cope with sv.cmp which uses CR[BF]

21 months agoadd insert sort svp64 test
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 14:59:54 +0000 (15:59 +0100)]
add insert sort svp64 test

21 months agosearch for BF in registers to over-ride Vector lookup into CR Register
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 14:58:11 +0000 (15:58 +0100)]
search for BF in registers to over-ride Vector lookup into CR Register
CR[32+BF...] is used, so it is more complex

21 months agostarting to add sv.cmp support and failfirst, had to add
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 13:36:23 +0000 (14:36 +0100)]
starting to add sv.cmp support and failfirst, had to add
SVMode to SVP64RMModeDecode to identify the different RM modes first

21 months agoadd PredicateBaseRM decode to CR Ops Simple mode as well as ff=3-bit
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 12:16:28 +0000 (13:16 +0100)]
add PredicateBaseRM decode to CR Ops Simple mode as well as ff=3-bit

21 months agoadd vli mode to ff=5 CR ops
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 11:57:57 +0000 (12:57 +0100)]
add vli mode to ff=5 CR ops

21 months agowhoops must only be PredicateBaseRM in CROpFF5RM
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 11:51:42 +0000 (12:51 +0100)]
whoops must only be PredicateBaseRM in CROpFF5RM

21 months agoadd sv.cmp (ffirst-5) decode/encode asm support
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 11:43:00 +0000 (12:43 +0100)]
add sv.cmp (ffirst-5) decode/encode asm support
* sv/trans/svp64.py needed a totally different ffirst handling
* CROpFF5RM needs to derive from FFPRRc0BaseRM and PredicateWidthBaseRM

21 months agoslightly different crops failfirst mode bits
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 11:18:30 +0000 (12:18 +0100)]
slightly different crops failfirst mode bits

21 months agoadd sv.cmp and try fail-first test_pysvp64dist.py
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 10:53:59 +0000 (11:53 +0100)]
add sv.cmp and try fail-first test_pysvp64dist.py

21 months agoremove complaints about standard Cray-style Vectors for the past 40 years
Luke Kenneth Casson Leighton [Sun, 2 Oct 2022 11:38:32 +0000 (12:38 +0100)]
remove complaints about standard Cray-style Vectors for the past 40 years
being able to have VL set to zero dynamically at runtime.
it is not appropriate to have complaints about 40-year-old standard
canonical behaviour of Cray Vectors in source code comments

VL=0 being set dynamically at runtime based on an algorithm input
sets the operations to nop because that is expected behaviour.
to not have VL=0 would be catastrophically inconvenient: it would
require either Illegal-Instruction traps to be raised, or Condition
Codes to be set and followed up with instructions to test and
branch for the dynamic condition when RA was zero, or to pre-test
for RA or CTR pre-being-zero prior to entry into a loop.

Data-Dependent Fail-First would become irrevocably damaged as well
as it is possible for VL to be set to zero at that time (first
test fails)

sv.bc would also be irrevocably damaged as it would no longer
be possible in VLSET mode to have VL become truncated to zero
dynamically based on a Condition Code.

in all it is pretty catastrophic to the entire Cray-Vector paradigm
and would severely damage SimpleV to disallow VL=0 purely for
arbitrary "convenience"

21 months agocomments for why preinc is called for svstep
Luke Kenneth Casson Leighton [Sun, 2 Oct 2022 02:29:39 +0000 (03:29 +0100)]
comments for why preinc is called for svstep

21 months agocomment out selectableint getitem logs
Luke Kenneth Casson Leighton [Sun, 2 Oct 2022 02:21:08 +0000 (03:21 +0100)]
comment out selectableint getitem logs

21 months agoskip svstate_pre_inc on svremap
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 23:35:08 +0000 (00:35 +0100)]
skip svstate_pre_inc on svremap
should not be needed

21 months agono svstate instruction
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 23:26:23 +0000 (00:26 +0100)]
no svstate instruction

21 months agosvstep calls SVSTATE_NEXT so needs svstate_pre_inc
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 23:24:25 +0000 (00:24 +0100)]
svstep calls SVSTATE_NEXT so needs svstate_pre_inc
setvl no longer calls SVSTATE_NEXT so does not

21 months agoremove special case from setvl calling SVSTATE_NEXT,
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 23:10:15 +0000 (00:10 +0100)]
remove special case from setvl calling SVSTATE_NEXT,
only accessible through svstep now

21 months agoreplacing setvl-svstep with just svstep
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 21:40:21 +0000 (22:40 +0100)]
replacing setvl-svstep with just svstep