Jacob Lifshay [Fri, 15 Oct 2021 03:27:42 +0000 (20:27 -0700)]
sort dpoints keys
Jacob Lifshay [Fri, 15 Oct 2021 03:21:12 +0000 (20:21 -0700)]
simplify dpoints computation
width is already set to fixed_width, we don't need to have a separate case
Jacob Lifshay [Fri, 15 Oct 2021 03:20:43 +0000 (20:20 -0700)]
dedup dpoints
Jacob Lifshay [Fri, 15 Oct 2021 03:10:04 +0000 (20:10 -0700)]
delete superfluous documentation section
Jacob Lifshay [Fri, 15 Oct 2021 03:09:40 +0000 (20:09 -0700)]
format code
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 16:55:49 +0000 (17:55 +0100)]
create quick test of what 24-12-5-6 layout was likely-expected to be
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 15:24:48 +0000 (16:24 +0100)]
add 2nd test to see what is going on in layout_experiment
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 15:09:11 +0000 (16:09 +0100)]
add FP "exponent" example, not quite matching expected results
needs analysis
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 14:45:33 +0000 (15:45 +0100)]
remove return of part_count parameter because it is not useful
the actual part_count (per se) is simply specified by vec_el_counts
which is a dictionary not a single item.
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 14:44:19 +0000 (15:44 +0100)]
fix issue where width was being computed based on 2 maximum values
actually needed is to multiply the number of elements by the width of
an element and use that to determine which is greater
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 14:26:13 +0000 (15:26 +0100)]
remove unnecessary sign argument from layout() tests
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 14:23:03 +0000 (15:23 +0100)]
remove signed. again
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 14:20:29 +0000 (15:20 +0100)]
whitespace for clarity. comments
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 13:48:26 +0000 (14:48 +0100)]
move "faulty" test to end of layout_experiment.py (last test)
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 12:40:43 +0000 (13:40 +0100)]
although it is a little less visually clear, removing the whitespace
allows illustrating what is used and what is not used in the 5-6-6-6
example
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 12:36:47 +0000 (13:36 +0100)]
add assert to check that the 5-6-6-6 example returns the expected
partition points 5,6,12,18
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 12:25:09 +0000 (13:25 +0100)]
fix layout() to put in only the number of *requested* vector elements
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 12:06:25 +0000 (13:06 +0100)]
rename part_counts to vec_el_counts
to indicate that it is intended to be the count of the number of vector
elements within a partition
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 11:55:44 +0000 (12:55 +0100)]
cpart_wid is just max(lane_shapes.values())
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 11:51:09 +0000 (12:51 +0100)]
redefine part_counts to be "number of vector elements in a partition"
fixes the bug
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 11:47:38 +0000 (12:47 +0100)]
whitespace
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 11:45:29 +0000 (12:45 +0100)]
whitespace, illustrate examples so as to make expected results clear
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 11:28:13 +0000 (12:28 +0100)]
unfortunately this is a multi-purpose commit.
it:
1) adds some types AND
2) adds some classes AND
3) fixes some whitespace issues AND
4) (finally) fixes some bugs
we strictly require *single* purpose commits
https://libre-soc.org/HDL_workflow/
Keep commits single-purpose
edit files making minimal single purpose modifications
(even if it involves multiple files. Good extreme example:
globally changing a function name across an entire codebase
is one purpose, one commit, yet hundreds of files.
miss out one of those files, requiring multiple commits,
and it actually becomes a nuisance).
https://bugs.libre-soc.org/show_bug.cgi?id=713#c98
Revert "fix layout bugs"
This reverts commit
9a318256b74054b8d592efe7be298764d0de415a.
Luke Kenneth Casson Leighton [Wed, 13 Oct 2021 11:25:25 +0000 (12:25 +0100)]
waaay too big a patch set (957 lines).
https://bugs.libre-soc.org/show_bug.cgi?id=713#c98
Revert "refactor layout to use SimdScope and XLEN"
This reverts commit
48c4d358fafb59fc7fdc414874c5288b81ec462d.
Jacob Lifshay [Wed, 13 Oct 2021 08:48:36 +0000 (01:48 -0700)]
refactor layout to use SimdScope and XLEN
Jacob Lifshay [Wed, 13 Oct 2021 08:47:38 +0000 (01:47 -0700)]
add SimdMap and SimdScope and XLEN
Jacob Lifshay [Wed, 13 Oct 2021 03:39:51 +0000 (20:39 -0700)]
fix layout bugs
Jacob Lifshay [Wed, 13 Oct 2021 01:04:20 +0000 (18:04 -0700)]
add docs for layout
Jacob Lifshay [Wed, 13 Oct 2021 00:55:19 +0000 (17:55 -0700)]
format code
Luke Kenneth Casson Leighton [Tue, 12 Oct 2021 13:29:06 +0000 (14:29 +0100)]
add option to specify fixed_width and no lane_shaps only to find
that there has been assumption that lane_shapes equals element width *times*
partition count.
https://bugs.libre-soc.org/show_bug.cgi?id=713#c67
next step is to set lane_shapes in terms of the element width
Luke Kenneth Casson Leighton [Mon, 11 Oct 2021 10:53:59 +0000 (11:53 +0100)]
add blanking mask, but current example has no blank areas
Luke Kenneth Casson Leighton [Mon, 11 Oct 2021 10:26:20 +0000 (11:26 +0100)]
whitespace
Luke Kenneth Casson Leighton [Mon, 11 Oct 2021 10:25:11 +0000 (11:25 +0100)]
improve code-comments some more
Luke Kenneth Casson Leighton [Mon, 11 Oct 2021 10:19:35 +0000 (11:19 +0100)]
improve code-comments some more
Luke Kenneth Casson Leighton [Mon, 11 Oct 2021 10:11:24 +0000 (11:11 +0100)]
improve code-comments
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 20:06:26 +0000 (21:06 +0100)]
whoops conversion of list of 0/1 needed reversing
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 15:22:20 +0000 (16:22 +0100)]
add option to do fixed-width layout
https://bugs.libre-soc.org/show_bug.cgi?id=713#c22
currently failing, answer is *backwards* (bit-inverted) which makes no sense
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 14:45:16 +0000 (15:45 +0100)]
add a check of bitp against the expected partition points when
going through the elwidths
https://bugs.libre-soc.org/show_bug.cgi?id=713#c47
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 14:19:31 +0000 (15:19 +0100)]
add phase 3 of the layout() experiment.
https://bugs.libre-soc.org/show_bug.cgi?id=713#c34
here the binary values are obtained which, if elwidth is set to a given
value, we expect the PartitionPoints mask to be set to that value
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 14:11:43 +0000 (15:11 +0100)]
convert to two-stage layout points-creation
https://bugs.libre-soc.org/show_bug.cgi?id=713#c34
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 13:59:34 +0000 (14:59 +0100)]
add code-comments
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 13:45:46 +0000 (14:45 +0100)]
added example with elwidth==Signal(2) from:
https://bugs.libre-soc.org/show_bug.cgi?id=713#c30
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 13:35:05 +0000 (14:35 +0100)]
remove Shape, signed and unsigned from layout experiment,
idea is to sub-class from ast.Shape() and therefore that provides
the full and complete understanding and specification of signed,
not layout()
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 13:30:52 +0000 (14:30 +0100)]
add layout experiment from
https://bugs.libre-soc.org/show_bug.cgi?id=713#c20
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 11:15:11 +0000 (12:15 +0100)]
fix SimdSignal Repl test (was previously unfinished)
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 10:35:20 +0000 (11:35 +0100)]
big rename PartitionedSignal to SimdSignal (shorter)
https://bugs.libre-soc.org/show_bug.cgi?id=713#c58
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 10:33:23 +0000 (11:33 +0100)]
add some more comments for the elwidth-adapter
https://bugs.libre-soc.org/show_bug.cgi?id=713#c34
Luke Kenneth Casson Leighton [Sat, 9 Oct 2021 19:52:14 +0000 (20:52 +0100)]
altered test_partsig2.py removed outval, run with outval2 instead
Luke Kenneth Casson Leighton [Sat, 9 Oct 2021 19:51:24 +0000 (20:51 +0100)]
add PartType context to PartitionedMux
not presently used, TBD, no harm done not using it due to the way that
PartitionedMux works
Luke Kenneth Casson Leighton [Sat, 9 Oct 2021 16:30:13 +0000 (17:30 +0100)]
convert PartitionedAssign and PAssign over to PartType
https://bugs.libre-soc.org/show_bug.cgi?id=713#c56
Luke Kenneth Casson Leighton [Sat, 9 Oct 2021 16:26:32 +0000 (17:26 +0100)]
covert PartitionedCat (and PCat) over to PartType format
https://bugs.libre-soc.org/show_bug.cgi?id=713#c56
Luke Kenneth Casson Leighton [Sat, 9 Oct 2021 16:22:36 +0000 (17:22 +0100)]
convert PartitionedRepl over to new "PartType" format
Luke Kenneth Casson Leighton [Sat, 9 Oct 2021 16:14:56 +0000 (17:14 +0100)]
add TestReplMod, under development
Luke Kenneth Casson Leighton [Tue, 5 Oct 2021 17:25:27 +0000 (18:25 +0100)]
add PartitionedRepl into PartitionedSignal.__Repl__
uses same auto-module-creation as PCat, PMux and PAssign
Luke Kenneth Casson Leighton [Tue, 5 Oct 2021 17:20:52 +0000 (18:20 +0100)]
shuffle order of functions (whitespace) to same order as ast.Value
Luke Kenneth Casson Leighton [Tue, 5 Oct 2021 17:09:24 +0000 (18:09 +0100)]
add PartitionedRepl first version, no unit test just demo
Luke Kenneth Casson Leighton [Tue, 5 Oct 2021 16:45:55 +0000 (17:45 +0100)]
whoops accidentally removed bugreport link
Luke Kenneth Casson Leighton [Tue, 5 Oct 2021 16:42:43 +0000 (17:42 +0100)]
add signed/unsigned functions and preliminary unit test
Luke Kenneth Casson Leighton [Tue, 5 Oct 2021 12:57:32 +0000 (13:57 +0100)]
pull in unit test code for PartitionedSignal.matches to be adapted
Luke Kenneth Casson Leighton [Tue, 5 Oct 2021 12:52:53 +0000 (13:52 +0100)]
bit of a reorder / reorg, to match up with current ast.Value function order
this makes it easier to ensure that all functions are there, easier to
read / find.
Luke Kenneth Casson Leighton [Tue, 5 Oct 2021 12:34:45 +0000 (13:34 +0100)]
disable mul and rmul in PartitionedSignal for now
Jacob Lifshay [Mon, 4 Oct 2021 23:28:32 +0000 (16:28 -0700)]
rewrite complex comprehensions as for loops
Jacob Lifshay [Mon, 4 Oct 2021 22:40:04 +0000 (15:40 -0700)]
Fix broken code caused by attempted removal of type annotations.
This partially reverts commit
0cdf4be4df5c0fbae476442c1a91b0e8140e2104.
Luke Kenneth Casson Leighton [Sat, 2 Oct 2021 18:02:36 +0000 (19:02 +0100)]
add TODO comments
https://bugs.libre-soc.org/show_bug.cgi?id=718
Luke Kenneth Casson Leighton [Sat, 2 Oct 2021 17:56:40 +0000 (18:56 +0100)]
add a PartitionedSignal.any() test and extend range of values tested
in horizontal logic operators
Luke Kenneth Casson Leighton [Sat, 2 Oct 2021 17:40:18 +0000 (18:40 +0100)]
make note about failing PartitionedAll
https://bugs.libre-soc.org/show_bug.cgi?id=176#c17
Luke Kenneth Casson Leighton [Sat, 2 Oct 2021 17:37:41 +0000 (18:37 +0100)]
revert to using self == Const(-1) for now in PartitionedSignal.all()
Luke Kenneth Casson Leighton [Sat, 2 Oct 2021 17:29:18 +0000 (18:29 +0100)]
bit more sophisticated on the partsig horizontal test, use subTest to report
function name and input value
Luke Kenneth Casson Leighton [Sat, 2 Oct 2021 17:26:41 +0000 (18:26 +0100)]
add PartitionedSignal.all() and unit test, currently failing
Luke Kenneth Casson Leighton [Sat, 2 Oct 2021 17:17:19 +0000 (18:17 +0100)]
add PartitionedAll operator, based on PartitionedBase
Luke Kenneth Casson Leighton [Sat, 2 Oct 2021 17:14:11 +0000 (18:14 +0100)]
add bool PartitionedSignal test
Luke Kenneth Casson Leighton [Sat, 2 Oct 2021 09:39:43 +0000 (10:39 +0100)]
removing unnecessary type information which makes the code
completely unreadable, longer and more complex
Jacob Lifshay [Sat, 2 Oct 2021 02:10:55 +0000 (19:10 -0700)]
add PartitionedSignalTester
Luke Kenneth Casson Leighton [Fri, 1 Oct 2021 21:00:19 +0000 (22:00 +0100)]
split out logical ops into PartitionedBase
Luke Kenneth Casson Leighton [Fri, 1 Oct 2021 16:33:09 +0000 (17:33 +0100)]
add PartitionedBool class (based on PartitionedXOR)
could very likely be combined but hey
Luke Kenneth Casson Leighton [Fri, 1 Oct 2021 16:03:25 +0000 (17:03 +0100)]
add quick use/self-test to PartitionedXOR
Luke Kenneth Casson Leighton [Thu, 30 Sep 2021 22:24:29 +0000 (23:24 +0100)]
add PartitionedSignal XOR partsig test
Luke Kenneth Casson Leighton [Thu, 30 Sep 2021 18:12:25 +0000 (19:12 +0100)]
partsig unit test tidyup
Luke Kenneth Casson Leighton [Thu, 30 Sep 2021 18:09:06 +0000 (19:09 +0100)]
test names to go under a different fileset
Luke Kenneth Casson Leighton [Thu, 30 Sep 2021 17:50:41 +0000 (18:50 +0100)]
add scalar test of PartitionedSignal.__Assign__
completes all 12 permutations needed
Luke Kenneth Casson Leighton [Thu, 30 Sep 2021 17:23:28 +0000 (18:23 +0100)]
add six combinations of PartitionedSignal.__Assign__ test:
* input width less, equal or greater to output width
* output signed or unsigned
Luke Kenneth Casson Leighton [Thu, 30 Sep 2021 15:10:21 +0000 (16:10 +0100)]
rework partsig TestAssign to cope with different types of input,
scalar/partitioned, lengths equal/greater/less, signed/unsigned
Luke Kenneth Casson Leighton [Thu, 30 Sep 2021 14:42:34 +0000 (15:42 +0100)]
fix PartitionedAssign, PAssign, and PartitionedSignal.__Assign__
preliminary unit test showed wiring was incorrect, as was the return
result from PAssign, which has to return Statements
Luke Kenneth Casson Leighton [Thu, 30 Sep 2021 13:59:28 +0000 (14:59 +0100)]
correct test_partsig name, remove redundant code
Luke Kenneth Casson Leighton [Thu, 30 Sep 2021 13:55:41 +0000 (14:55 +0100)]
remove PartitionedSignal.eq, expectation is to use PartitionedSignal.__Assign__
due to eq being removed, access to the underlying ".sig" is now
done using PartitionedSignal.lower()
Luke Kenneth Casson Leighton [Thu, 30 Sep 2021 13:40:15 +0000 (14:40 +0100)]
whitespace / comments
Luke Kenneth Casson Leighton [Wed, 29 Sep 2021 18:35:23 +0000 (19:35 +0100)]
add use of PartitionedAssign in PartitionedSignal, behind __Assign__
move to separate module due to recursive import issues
Luke Kenneth Casson Leighton [Wed, 29 Sep 2021 18:28:11 +0000 (19:28 +0100)]
add support in PartitionedAssign for scalar signals
Luke Kenneth Casson Leighton [Wed, 29 Sep 2021 18:10:48 +0000 (19:10 +0100)]
add PartitionedAssign class for use in PartitionedSignal
Luke Kenneth Casson Leighton [Wed, 29 Sep 2021 18:10:23 +0000 (19:10 +0100)]
add PartitionedSignal.shape function
(simply returns underlying self.sig.shape())
Luke Kenneth Casson Leighton [Wed, 29 Sep 2021 17:25:45 +0000 (18:25 +0100)]
add PartitionedSignal.__len__ override, redirects to self.sig len
Luke Kenneth Casson Leighton [Wed, 29 Sep 2021 16:13:45 +0000 (17:13 +0100)]
reduce part_mask in partsig tests to 3 (actual number of break points
not actual number of partitions), fix PartitionedSignal.like(),
needed to pass in PartitionPoints(other.partpoints)
Luke Kenneth Casson Leighton [Wed, 29 Sep 2021 16:12:51 +0000 (17:12 +0100)]
add assert to check partition jump point size
Luke Kenneth Casson Leighton [Wed, 29 Sep 2021 15:43:50 +0000 (16:43 +0100)]
unit test for PartitionedSignal.__Cat__
decided also to change the mask to be the number of partition points
(not waste one bit)
Luke Kenneth Casson Leighton [Tue, 28 Sep 2021 18:50:41 +0000 (19:50 +0100)]
move PCat to separate module
(didnt help but hey), solve recursive import by moving import of
PartitionedCat into the PCat function
Luke Kenneth Casson Leighton [Tue, 28 Sep 2021 18:41:20 +0000 (19:41 +0100)]
add PartitionedSignal.__Cat__ override
calls and creates PartitionedCat module
Luke Kenneth Casson Leighton [Tue, 28 Sep 2021 18:36:31 +0000 (19:36 +0100)]
corrections to PartitionedCat after corrections to PartitionedSignal,
using make_partitions2, off-by-one error
Luke Kenneth Casson Leighton [Tue, 28 Sep 2021 16:00:40 +0000 (17:00 +0100)]
add PartitionedSignal.__Mux__ unit test
split out from TestPartitionedSignal to reduce time and make it clear
what is being tested
Luke Kenneth Casson Leighton [Tue, 28 Sep 2021 14:17:15 +0000 (15:17 +0100)]
add PartitionedSignal.__Mux__ using existing PMux function
Luke Kenneth Casson Leighton [Mon, 27 Sep 2021 18:29:26 +0000 (19:29 +0100)]
derive PartitionedSignal from UserValue (temporarily) and add lower()