mem-cache,python: Allow custom TLB and events in each prefetcher.

The `BasePrefetcher` python class had members `_events` and `_tlbs`
defined as lists, meaning that any call to `list.append` on them would
affect `_events` and `_tlbs` for all prefetchers, not just the calling
object.  This change redefines them as instance members to fix the
problem.

Change-Id: I68feb1d6d78e2fa5e8775afba8c81c6dd0de6c60
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32394
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

util,systemc: Update the stats API used in one of the examples.

A new parameter as added to the initText method in March of this year,
but this example code was not updated which prevents it from compiling.

This change adds the parameter to the call and sets it to what the
documenting comments say is the default, true.

Change-Id: Ic8da46dba03f01f338c38a7bc02ba232a90ae349
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32641
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,systemc: Update the gem5-within-systemc TLM example code.

Some class names within gem5 changed in March of last year, and this
code was not updated to match. Change ExternalMaster::Port to
ExternalMaster::ExternalPort, and ExternalSlave::Port to
ExternalSlave::ExternalPort.

Change-Id: I04c0970c4107de3449473c24c7c6f99ada72bbb3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32640
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add Xen compilation to gen_arm_fs_files.py

Change-Id: I61014d9686f0362ebb83dca5d4d33ac08d66d0a7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32557
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Remove dependency check

The list is rather old and it contains some entries which are likely
unneeded. Since we are also now able to select specific FS binaries
to be compiled individually, there is not point of requiring all
components to be installed.
Instead, if is better to rely on the error message of building process
and let the users figure out which packages they need to install

Change-Id: I16c74861cb1f2b09c3e91e408ace01a9bd7a234d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32556
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Allow the short -j option in gen_arm_fs_files.py

Change-Id: I15c3bad13882cd38683b7c733311191e1f51d13f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32555
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Change gen_arm_fs_files.py to allow selective compilation

With the -b/--fs-binaries option it is possible to specify a list
of fs binaries to be fetched/compiled.

Change-Id: I12a642f65b74e8606c82cdddcbc3a8172bad2381
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32554
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Dropped the i386 host tag in tests

Issue-on: https://gem5.atlassian.net/browse/GEM5-532
Change-Id: Ifee50d59c65f8b460248508688232d9253c040b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32596
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Use isSecure variable for Stage2Lookup

TLB entries are tagged with the security state of the cpu instead
of the security attribute of the physical address

Change-Id: I728ba1c841de1ec6c1ee03aee012b185c968d078
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32639
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix physmem NS attribute in VMSAv8-32 descriptors

The NS field in PTEs descriptors is tagging Secure/Non-secure physical
memory (pages). This field is relevant in Secure state only:

While in Secure state, software can access both the Secure and
Non-secure physical address spaces, software in Non-secure state can
only access Non-secure memory; the NS bit is hence discarded/treated as
1.

This patch is aligning VMSAv8-32 with VMSAv8-64, which is tagging the
pointed memory as Non-secure in case of a Non-secure lookup.

The old behaviour was probably not leading to incorrect execution:
once a translation completes, the security flag in the memory request
is chcked against the security state of the cpu (and not only relying
on the NS bit in the TLB entry)

if (isSecure && !te->ns) {
    req->setFlags(Request::SECURE);
}

so we were already forbidding secure accesses from non secure world
if NS = 0.

It is however misleading in the debug logs to see tlb entries with
NSTID = 1 and NS = 0.

Change-Id: I1f964069f88c33fb14362dd4101cb22538907226
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32638
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: VSTTBR_EL2 doesn't contain a VMID field

Change-Id: Ia6e14b509d7016020af9c85941e7b2d89dcdd359
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32637
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Disable HVC when SCR_EL3.HCE is 0

This was already implemented for AArch32 but it had been wrongly
removed by:

https://gem5-review.googlesource.com/c/public/gem5/+/31394

Change-Id: Ida303d5ccb5d8568ca4e7faaedf9b4efd1cd88b5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32636
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix XN in TLB permissions

The SIF condition check should be logically ORed with the TLB
entry XN attribute, instead of overriding it.

Change-Id: I70b38d97bbdc82b9f385d40ad06546785fc2c5bb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32635
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix SoftwareStep::debugExceptionReturnSS

debugExceptionReturnSS is called on an ERET instruction to
check for software step. The method was not using the
SPSR.width and it was relying on the more generic ELIs32 to
check the execution mode of the destination EL.

This is not only an efficiency problem: the helper might not work
when returning to EL0. In general it is not possible to
understand if EL0 is using AArch32 or AArch64 if the current
EL is not EL0 and EL1 is using AArch64.

This is instead visible by inspecting the spsr.width during the
execution of an ERET instruction

Change-Id: Ibc5a43633d0020139f2c0e372959a3ab4880da6e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32634
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Use proper keywordargs for RedirectPath in apu_se

RedirectPath uses app_path and host_paths instead of src and dests.
This patch fixes that in apu_se.

The patch also changes the formatting for those lines, as simply
replacing dests with host_paths put the lines over the 80 char limit.

Change-Id: If7e4c41f2f52bc3d5aa26465c786294f9b68f8d3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32655
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Remove unneeded variable assignments in apu_se

This patch removes:
A line assigning a variable to itself

An assignment to a variable (chroot) that is never used.
The above assignment also caused an error, "'NoneType' object
has no attribute 'startswith'"

Change-Id: Ib93c25fee4a0f7c1440de8067b086d8b96614796
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32654
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Remove remnants of /dev/shm mapping from apu_se

This patch removes a redirect for /dev/shm. It also removes
a function call that cleaned up the /dev/shm redirect

Change-Id: Iec2598c715223d079bc5dfd2ea52859945706cfc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32354
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add build dependency to gcn Dockerfile

src/base/pngwriter.cc requires libpng-dev

Change-Id: I7f009cd8f5cacd64150c06b716b1ce3008832910
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32474
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

mem-ruby: Fix debug prints for regular Stores

In the updated implementation of LL/SC (27103) the default value
of success was changed, which results in printing "SC_Failed" for
any regular stores.

Change-Id: I4f2e0b26233ce0cbdf948aadd19c9d81bf18bec0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32514
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Free registers when execMask = 0

Flat instructions free some of their registers through their memory
requests, in particuar a call to scheduleWriteOperandsFromLoad(),
which gets called from GlobalMemPipeline::exec.

When execMask is 0, the instruction doesn't issue a memory request.

This patch adds in a call to scheduleWriteOperandsFromLoad() when
execMask is 0 for Flat Load and AtomicReturn instructions, as those
are the instructions that call scheduleWriteOperandsFromLoad()
in the memory pipeline.

This patch also adds in a missing return statement when execMask is 0
in one of the Flat instructions.

Change-Id: I09296adb7401e7515d3cedceb780a5df4598b109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32234
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: fix races between data and DMA in MOESI_AMD_Base-dir

There are race conditions while running several benchmarks, where
the DMA engine and the CorePair simultaneously send requests for the
same block. This patch fixes two scenarios
(a) If the request from the DMA engine arrives before the one from the
CorePair, the directory controller records it as a pending request.
However, once the DMA request is serviced, the directory doesn't check
for pending requests. The CorePair, consequently, never sees a response
to its request and this results in a Deadlock.

Added call to wakeUpDependents in the transition from BDR_Pm to U
Added call to wakeUpDependents in the transition from BDW_P to U

(b) If the request from the CorePair is being serviced by the directory
and the DMA requests for the same block, this causes an invalid
transition because the current coherence doesn't take care of this
scenario.

Added transition state where the requests from DMA are added to the
stall buffer.

Updated B to U CoreUnblock transition to check all buffers, as the DMA
requests were being placed later in the stall buffer than was being checked

Change-Id: I5a76efef97723bc53cf239ea7e112f84fc874ef8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31996
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: make read2st64_b32 write proper registers

Per the GCN3 ISA, read2st64_b32 writes to consecutive registers

Change-Id: Ibc1672584a72cf7de12e06068a03fe304b34dce2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32236
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Fixing HSA's barrier bit implementation

This changeset fixes several bugs in the HSA barrier bit implementation.

1. Forces AQL packet launch to wait for completion of all previous packets
2. Enforces barrier bit blocking only if there are packets pending completion
3. Barrier bit unblocking is correclty done by the last pending packet
4. Implementing barrier bit for all packets to conform to HSA spec

Change-Id: I62ce589dff57dcde4d64054a1b6ffd962acd5eb8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30354
Reviewed-by: Sooraj Puthoor <puthoorsooraj@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Install python six module in gcn dockerfile

six is used in develop, but wasn't used in the GCN staging branch.

Change-Id: Ic1ca42df871d1e683c288282497267d00421609f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32235
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Remove the stacktrace.hh switching header file.

This is no longer used.

Change-Id: I1419b28d51ff603beb7d8ab89632ad7038c3057e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32215
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-simple: Fix BaseSimpleCPU to reset group stats

BaseSimpleCPU::resetStats() should call Stats::Group::resetStats()
to reset new style hierarchy stats.

Change-Id: I932280449b29577d214db56ac8347aca4143c949
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32434
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add stub unit tests for the call types in the m5 utility.

These will be filled out in later changes. This CL just adds the
plumbing to the build script.

Change-Id: If58ea023d0c85eae0160f88217c83fca70346da2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27688
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

util: Pull "usage()" out of the call types in the m5 utility.

Also pull common implementations of some call type methods into the base
class, and make disappearing call types clean themselves up to make the
test a little simpler and less error prone.

Change-Id: Ie178fe02d41587647ddc90a084d1d1142b84dde9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27687
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Reduce boilerplate when extracting SelfDebug from tc

Change-Id: I1746400617be64ac9c2f3194442734e178342909
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31354
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix <timer>_CTL_EL<x>.ISTATUS when masking the irq

According to the ArmArm:

"When the value of the ENABLE bit is 1, ISTATUS indicates whether the
timer condition is met.  ISTATUS takes no account of the value of the
IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then
the timer interrupt is asserted."

Since ISTATUS is simply flagging that timer conditions are met, an
interrupt mask (via the <timer>_CTL_EL<x>.IMASK) shouldn't reset the
field to 0.
Clearing the ISTATUS bit leads to the following problem
as an example:

1) virtual timer (EL1) issuing a physical interrupt to the GIC

2) hypervisor handling the physical interrupt; setting the
CNTV_CTL_EL0.IMASK to 1 before issuing the virtual interrupt
to the VM

3) The VM receives the virtual interrupt but it gets confused
since CNTV_CTL_EL0.ISTATUS is 0 (due to point 2)

What happens when we disable the timer?

"When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN."

So we are allowed to not clear the ISTATUS bit if the timer gets
disabled

Change-Id: I8eb32459a3ef6829c1910cf63815e102e2705566
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31775
Reviewed-by: Hsuan Hsu <kugwa2000@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: don't wake up SE futex syscalls on ARM events

Before this commit:

* SEV events were not waking neither WFE (wrong) nor futex WAIT (correct)
* locked memory events (LLSC) due to LDXR and STXR were waking up both
  WFE (correct) and futex WAIT (wrong)

This commit fixes all wrong behaviours mentioned above.

The fact that LLSC events were waking up futexes leads to deadlocks,
as shown in the test case described at:
https://gem5.atlassian.net/browse/GEM5-537
because threads woken up by SVE are not removed from the waiter list
for the futex address they are sleeping on.

A previous fix atttempt was done at:
1531b56d605d47252dc0620bb3e755b7cf84df97
in which only sleeping threads are woken up. But that is not sufficient,
because the futex sleeping thread that was being wrongly woken up on SEV
can start to sleep on a second futex.

As an example, consider the case where 4 threads are fighting over two
critical sections protected by futex1 and futex2 addresses. In this case,
one thread wakes up the other thread after it is done with the section.

Suppose the following sequence of events:

* thread1 is awake and all others are suspended on futex1

* thread1 SEV wakes thread2 from the futex1 while in the critical region 1.

  This is the wrong behaviour that this patch prevents, because
  now thread2 is still in the sleeper list for futex1

* thread1 then futex wakes tread3, then proceeds to critical region 2.

* thread3 wakes up, but because thread2 has critical region, it sleeps
  again.

* thread2 finishes its work, futex wakes thread3, and then proceeds to
  futex2

  When it reaches futex2, thread1 is still working there, so it sleeps on
  futex2.

* thread3 futex wakes thread2, because it is still wrongly on the sleeper
  list of futex1. But thread2 is in futex2 now.

  If it weren't for this mistake, it should have awaken the final thread4
  instead.

Outcome: thread4 sleeps forever, no other thread ever wakes it, because all
other threads have woken from futex1 and awoken another thread.

The problem is fixed by adding the waitingTcs unordered_set FutexMap,
which is basically an inverse map to FutexMap, which tracks (addr,
tgid) -> ThreadContext. This allows us allow to quickly check
if a given ThreadContext is waiting on a futex in any address.

Then the SEV wakeup code path
now checks if the thread is k

Change-Id: Icec5e30b041f53e5aa3b6e0d291e77bc0e865984
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29777
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: factor out FutexMap::suspend and FutexMap::suspend_bitset

Both methods do basically the same, especially since they don't handle the
timeout which is basically the only difference between both modes of the
syscall (one uses absolute and the other relative time).

Remove the WaiterState::WaiterState(ThreadContext* _tc) constructor,
since the only calls were from FutexMap::suspend which does not use them
anymore. Instead, set the magic 0xffffffff constant as a parameter to
suspend_bitset.

Change-Id: I69d86bad31d63604657a3c71cf07e5623f0ea639
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29776
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: split futex_map.cc into header and source files

To speed up development when modifying the implementation.

Change-Id: I1b3c67c86f8faa38ed81a538521b08e256d21a5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29775
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-mips: Remove old TypeBufferArg call

TypeBufferArg was replaced by VPtr so this call is no longer needed.
This fixes the MIPS build / nightly build.

Change-Id: I3880229fa0ad87fad1ca35c136e12efc6c36ceda
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32414
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add checkpoint parameters for VMA list

Add checkpoint parameters (together with corresponding serialization
and unserialization) for VMA list of class MemState into a separate
section named 'vmalist'.

Without these VMA list parameters, a page table fault will occur when
running with --restore-simpoint-checkpoint, because of an empty VMA
list. For example:

  $ ./build/RISCV/gem5.debug --debug-flags=Exec configs/example/se.py \
      -c tests/test-progs/hello/bin/riscv/linux/hello \
      --cpu-type=NonCachingSimpleCPU --restore-simpoint-checkpoint \
      --checkpoint-dir m5out/ -r 2
  ...
  2404000: system.switch_cpus: T0 : @_int_malloc+3392    : sd a5, 8(a0) \
      : MemWrite :  D=0x000000000001ed21 A=0x862e8
  panic: Page table fault when accessing virtual address 0x862e8
  ...

Example checkpoint output:

  [system.cpu.workload.vmalist]
  size=3

  [system.cpu.workload.vmalist.Vma0]
  name=stack
  addrRangeStart=...
  addrRangeEnd=...

  [system.cpu.workload.vmalist.Vma1]
  name=heap
  addrRangeStart=...
  addrRangeEnd=...

  [system.cpu.workload.vmalist.Vma2]
  ...

Change-Id: Ib2fa7ad2c34fe667ce95bc4b10a1affcf60d9c1f
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31875
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-power: Implement GDB XML target description for PowerPC

Change-Id: I2610626a7e1464316ebaa770291d4bdcb59e8856
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31114
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Remove the "profile" parameter and plumbing.

This parameter is associated with a periodic event which would take a
sample for a kernel profile in FS mode. Unfortunately the only ISA which
had working versions of the necessary classes was alpha, and that has
been deleted. That means that without additional work for any given ISA,
the profile parameter has no chance of working.

Ideally, this parameter should be moved to the Workload classes. There
it can intrinsically be tied to a particular kernel, rather than having
to assume a particular kernel and gate everything on whether you're in
FS mode.

Because this isn't (IMHO) where this parameter should live in the long
term, and because it's currently unusable without additional development
for each of the ISAs, I think it makes the most sense to remove the
front end for this mechanism from the CPU.

Since the sampling/profiling mechanism itself could be useful and could
be re-plumbed somewhere else, the back end and its classes are left alone.

Change-Id: I2a3319c1d5ad0ef8c99f5d35953b93c51b2a8a0b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32214
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Adjust some type names in a couple tests.

These names happened to collide with names from gem5 itself, and when
linked together produced strange and incorrect results.

Ideally gem5's names should go inside a gem5 namespace, but that's a
much larger change.

Change-Id: Ie7c5f2236678d5dbb722a86321296fce395fbd37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32175
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Filter a pydot warning message out when checking test output.

This warning can show up if pydot isn't set up properly and doesn't have
anything to do with the success of the test.

Change-Id: Iddcea5aa27196bc5cf747bf5a295b6c9a91b3d2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32174
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons,fastmodel: Limit how many instances of simgen can run at once.

Each instance of simgen uses a license. If there are only so many to
go around, running many instances at once could exhaust the pool of
licenses and break the build.

The number of licenses may be less than the number of regular build
steps we want to do in parallel, but may be greater than zero. To
limit them to at most n in parallel where n might be less than j
and/or more than 1, we create a group of license slots, assign simgen
invocations to a slot, and then use scons's side effect mechanism to
ensure no two invocations in the same slot run at the same time.

This may be a suboptimal packing if the commands take significantly
different amounts of time to run since the slots are preallocated and
not demand allocated, but the difference shouldn't normally matter in
practice, and scons doesn't provide a better mechanism for partially
serializing certain build steps.

Change-Id: Ifae58b48ae1b989c1915444bf7564f352f042305
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32124
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Make src/systemc/tests/SConscript python 3 compatible.

The os.path.walk method was removed in python 3. Replace it with os.walk
which is available in both python 2 and 3.

Change-Id: I7919b6a2063c65bc3619927aa4514d8d6d1b2038
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32123
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Use VPtr for uname.

Change-Id: Ia4b6c9135f16e6c68bbcf3a9c15ba7433a0a6682
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29403
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>

sim: Convert stat functions to use VPtr.

Change-Id: I1fe43ad7508b5fbbcbf6c84195858455fc8f3e85
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29402
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Delete the now unused --update-ref option.

This option was for use with the old scons based regression tests.
Those had been deleted for a while, but some other bits and pieces
related to them were still lying around, depending on this option. Now
that those have been cleaned up, this option can go away.

Change-Id: I95b41dd0a14c51e74d1e527eb40e09f49aaeaf7e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32122
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Remove explicitly set defaults in calls to AddOption.

Like the optparse module's add_option method, most keyword arguments
have sensible default values. We should avoid setting those explicitly
when calling AddOption, since it usually doesn't make anything clearer
and just adds more text to wade through.

Change-Id: I70e425d9f1a0da1cafcc3d7dd24bfde18c0b3f35
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32116
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

utils,tests: Enable passing of build args to compiler-tests.sh

Previously we passed "-j `nproc`" to the scons. This a greedy approach
that should not be default. This change was introduced so the "-j" flag
may be passed via the "util/compiler-tests.sh" script.

Change-Id: I2e891ae3a9819770bd3ef15b95b81b7f5b71f7fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31734
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Delete the util/regress script.

This script was for running the old style scons based tests, but those
have all been deleted.

Change-Id: I644516a89ecafb611903ca304ced254e47e2e063
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32121
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

tests: Get rid of the now unused diff-out script.

This script had been used to compare the output of gem5 regression
tests to a golden reference, but all the tests that used it have been
deleted.

Change-Id: Ib65e4271ce8081dd5994b412ac2240869ab02d44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32120
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

tests: Get rid of the tests/testing python package.

This was used by the now deleted tests/tests.py script.

Change-Id: I18481b02a78432b88e6cd9226a4c046bc6433743
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32119
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

tests: Get rid of the tests/tests.py script.

This script was to manage and run the old style regression tests, which
have all been deleted.

Change-Id: I573f8e4ca0d61cb12de18f280ffabbb45a5443e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32118
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

scons: Remove the plumbing for running regression tests from scons.

All of these tests have been migrated to the new framework, so there's
no reason to leave the old plumbing lying around.

Change-Id: Iaa5412864354d5754a68a9f53f30aa42f07ec2eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32117
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

scons: Update some scons bug report URLs.

It appears that scons bugs are not on tigris.org any more and are now
on github, although fortunately old bugs seem to have been ported over
and have the same numbering.

This CL updates URLs which were in comments in the gem5 source,
specifically in scons scripts, to point to the corresponding github
version.

I also checked to see if these bugs were still open, or if we could
remove our workarounds for them.

1. 2356 is still open, and has been fairly recently assigned.
2. 2611 is marked as fixed. We might be able to implement the
   workaround in its last comment from August of 2019.
3. 2811 has been marked fixed, and as best I can tell the fix first
   appeared in around version 3.0 of scons. If/when that is our
   minimum version, we can remove the workaround in
   site_scons/site_tools/default.py. That is mostly fixing an annoying
   spurious rebuild by scons which does not affect correctness, so even
   if we remove that workaround we shouldn't break earlier versions,
   although it would be obnoxious for people that are affected by it
   and best avoided.

Change-Id: I0d74820f399044c6f80148bf3022d07d7bf6f4e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32114
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-kvm: Add missing 'override' keyword

clang requires all functions that override a member function to be
masked by the 'override' keyword. The missing 'override' in
timer.hh causes compiling issues while compiling gem5 with clang.
This commit adds the missing keyword.

Jira: https://gem5.atlassian.net/browse/GEM5-724

Change-Id: I3b5c7af666927b079a785803c8bb4869180ff777
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32095
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: fix double delete

Change-Id: I05cec0ef8b97fa39aa0d4bf97d7ebd79059e3d7b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32094
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Fix disassembling of float register instructions

In disassembling of float register instructions, Gem5 always gives 2
source registers rs1 and rs2. However, this is not correct for Mul-Add
instructions which have three rs1, rs2, and rs3, and for Move, Convert
instructions which have only rs1.

For example: (Gem5  output  vs Expected)
- fmadd.d fa0,fa0,fa4 vs  fmadd.d fa0,fa0,fa4,fa5
- fcvt.d.l fa4,a6,zero  vs  fcvt.d.l fa4,a6

This patch fixes the problem.

Change-Id: I02d840eab602ac4a9782911b3cdff2935dfe5e68
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32054
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Initialize cd_addr in src/dev/arm/smmu_v3_transl.cc

In src/dev/arm/smmu_v3_transl.cc#L1401, cd_addr might not be
initialized when all if statements fail.

Change-Id: Idf53c07a9b5d52eea488e631f7334d4b566e645a
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32015
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,scons: improve compareVersions function

Current compareVersions() fails in this case:
compareVersions("10", "10.0") return -1 while it should be 0.
This at least is causing a systemc compiling issue.

This problem causes by the comparison algorithm. The algorithm
turns the versions in two lists, and compares the corresponding
elements of the two lists up to the last element of the shorter
list. If all elements are equal, the longer list will be
determined to be the more recent version. Hence, this algorithm
determines "10.0" to be more recent to "10".

This commit addresses this issue by making the version lists
have the same length by adding 0 to the shorter list.

JIRA: https://gem5.atlassian.net/browse/GEM5-715

Change-Id: I859679185ac67e1b4d327d8803699cc5e399fa8c
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32014
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implementing SecureEL2 feature for Armv8

This patch adds Secure EL2 feature. This allows stage1
EL2/EL&0 and stage2 secure translation.
The changes are organized as follow:

  + insts/static_inst.cc: Modify checks for illegalInstruction on eret
  + isa.cc/hh: Enabling contorl bits
  + isa/insts/misc.hh/64.hh: Smc fault trigger.
  + miscregs.cc/hh: Declaration and initialization of new registers
  + self_debug.cc/hh: Add secureEL2 types for breakpoints
  + stage2_lookup.cc/hh: Allow stage2 in secure state.
  + tlb.cc/table_walker.cc: Allow secure state for stage2 and stage 1 EL2&0
                     translation regime
  + utility.cc/hh: New function InSecure and refactor of other helpers
                   to enable secure state

JIRA: https://gem5.atlassian.net/browse/GEM5-686

Change-Id: Ie59438b1828508e944334420da1d8f4745649056
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31394
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: relax GenericTimer check for CPU count

At Iff9ad68d64e67b3df51682b7e4e272e5f355bcd6 a check was added to prevent
segfaults when unserializing the GenericTimer in case the new number of
thread contexts was smaller than the old one pre-checkpoint.

However, GenericTimer objects are only created dynamically as needed after
timer miscreg accesses. Therefore, if we take the checkpoint before
touching those registers, e.g. from a simple baremetal example, then the
checkpoint saves zero timers, and upon restore the assert would fail
because we have one thread context and not zero:

> fatal: The simulated system has been initialized with 1 CPUs, but the
Generic Timer checkpoint expects 0 CPUs. Consider restoring the checkpoint
specifying 0 CPUs.

This commit solves that by ensuring only that the new thread context count
larger than, but not necessarily equal to the number of cores.

Change-Id: I8bcb05a6faecd4b4845f7fd4d71df95041bf6c99
JIRA: https://gem5.atlassian.net/browse/GEM5-703
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31894
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: add support for flat atomic adds, subs, incs, decs

Add support for all missing flat atomic adds, subtracts, increments,
and decrements, including their x2 variants.

Change-Id: I37a67fcacca91a09a82be6597facaa366105d2dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31974
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: fix name collisions in verifier.py

In verifier.py, testlib.test_util is imported and renamed to 'test',
while several functions in the file have a subfunction named 'test()',
which causes test.fail() to fail as 'test' points to the
subfunction instead of the module.

This commit addresses the above issue by keeping the imported module
as test_util instead of renaming it to test.

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I0ab7b52619f2fa9495e9a6ff8d469c022eea98bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31994
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Avoid code duplication in Pl111

Change-Id: I17af93459ace0e4ef82693622a4135c3e831aaf5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31176
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Relax size constraint on AMBA ID registers

This patch is allowing non word sized accesses to the AMBA ID
registers.

Change-Id: I61a7163a3b4120e8dbcdbd6d9b83d33a7996f979
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31175
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: generateBasicPioDeviceNode requiring an ArmInterruptPin

Change-Id: I16ed3b689158defe2a43cccfa053d48dec4a1e41
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31941
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix DTB autogen for HDLcd

The HDLcd was wrongly reporting the hardcoded IRQ=63 as the interrupt
number during DTB autogeneration. This is because the DTS is using 63.
However that corresponds to the SPI offset; the gem5 helper is
instead expecting the global IRQ number = 32 + SPI offset

Change-Id: I9e82360843eacb13cef5ddd2e28d2f3ef3147335
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31940
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Make the Sp805 use the new ArmInterruptPin::active

Change-Id: I65b53b33e13345eca93a76e82efac7f8c0b97755
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31939
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Make Sp804 use the ArmInterruptPin

Change-Id: I2d71c7e874ba1ec798e2314d7d282cb853b3f360
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31938
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Make AmbaInt/DmaDevice use the ArmInterruptPin

Change-Id: I7318b9186cd81f948211e8a955dab7eea6d2a2f5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31936
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Make Pl011 UART use the ArmInterruptPin

Change-Id: I995a424491f087b70b72d2558d96c7a472d4abaa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31935
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Introduce the active boolean for ArmInterruptPin

The active boolean will specify if the interrupt line is active
or not (high if it is active high or low if it is active low).

This is decoupled from the interrupt being in a pending state
within the GIC, and it can be used by a peripheral to query the
status of its interrupt pin

Change-Id: I18445b891a75767c8a72e9a7044d6d75fdb7e224
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31934
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Move checkpoint parameters for ptable into seperate section

In checkpoint output files, the parameters for page table including
size and entries are organized not very clearly. For example:

  [system.cpu.workload]
  ...
  ptable.size=...

  [system.cpu.workload.Entry0]
  vaddr=...
  paddr=...
  flags=...

  [system.cpu.workload.Entry1]
  ...

This commit moves these parameters into a separate section named
'ptable'. For example:

  [system.cpu.workload.ptable]
  size=...

  [system.cpu.workload.ptable.Entry0]
  vaddr=...
  paddr=...
  flags=...

  [system.cpu.workload.ptable.Entry1]
  ...

Change-Id: Iaa4129b3f4f090e8c3651bde90524abba0999c7f
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31874
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a "writefile" unit test to the m5 utility.

Change-Id: Ic0e8d5fbbd5b6d6b57f674cef6460f94206a5872
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27628
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>

configs: Change env defaults in apu_se.py for ROCm

This change simplifies the setup process for running
ROCm-based programs by adding the libraries that are
needed to LD_LIBRARY_PATH by default, using
preexisting environment variables that should be set
on the host.

HOME also gets set, as MIOpen-based programs can fail
without it set.

Change-Id: Ic599674babeaebb52de8a55981d04454cdc96cd8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30275
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

fastmodel: Implement GIC DTB auto-generation.

Implement generateDeviceTree for FastModelGIC so the interrupt
controller is automatically added to the DTB. This is sufficient to
allow a VExpressFastmodel system model to boot Linux without an
explicit DTB.

Change-Id: I69d86fd8bba1b86768c8a118d2de079a56179854
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31078
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Remove scs_prefix_appli_output binding.

The scx_prefix_appli_output function is removed in recent Fast Models
releases.

Change-Id: I324b911ec7ed68b7d0c324ac20a9795515e4de57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31077
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Fix hierachical Iris component names.

Recent releases of Fast Models structure Iris resources in a hierarchy.
Use the parent resource ID if set to construct the hierachical name of
components when constructing the resource map.

Change-Id: Iafafa26d5aff560c3b2e93894f81f770c0e98079
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31076
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Add missing dependencies.

Add -latomic library required by recent Fast Models releases.
Add SystemCExport directory for tlm_has_get_protocol_types.h include.

Change-Id: Ia0c275d55f5077499588228737ed1ff5975cd5db
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31075
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

base,scons: `-wno-deprecated-copy` added for hdf5.cc with GCC

As highlighted by Ciro here:
https://gem5-review.googlesource.com/c/public/gem5/+/31216, and
here: https://gem5.atlassian.net/browse/GEM5-365,  It appears that GCC
versions >= 9 requires `-wno-deprecated-copy` which was removed in
commit: https://gem5-review.googlesource.com/c/public/gem5/+/31216.
`-wno-deprecated-copy` appears to work for all versions of GCC. Clang
does not require `-wno-deprecated-copy` nor `-wno-deprecated` for
sucessfull compilation. Therefore branching has been introduced to the
SConscript to address this and simplify the solution.

Change-Id: I233b32aa945d479dd429bb5591272608ba342d8d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31754
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

configs, mem: Support running VIPER with GCN3

This changeset adds the necessary changes for running
GCN3 ISA with VIPER in apu_se.py.

Changes to the VIPER protocol configs are made to add support
for DMA and scalar caches.

hsaTopology is added to help the pseudo FS create the files
needed by ROCm to understand the device on which the SW is
being run.

Change-Id: I0f47a6a36bb241a26972c0faafafcf332a7d7d1f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30274
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implement ARM8.1-VHE feature

This commit implemented the VHE feature in ARMv8. This consist in 3
parts
    1. Register decl/init and register redirection from el1 to el2
        miscregs.cc/hh
        miscregs_types.hh
        isa.cc
        utility.cc/hh
    2. Definition of new EL2&0 translation regime.
        tlb.cc/hh
        table_walker.cc
        pagetable.hh
        tlbi_op.hh
        isa.cc ( for tlb invalidation functions)
    3. Self Debug adaptation for VHE
        self_debug.cc
    4. Effects on AMO/IMO/FMO interruptions
        faults.cc
        interrupts.hh

JIRA: https://gem5.atlassian.net/browse/GEM5-682

Change-Id: I478389322c295b1ec560571071626373a8c2af61
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31177
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Update HIP patch used in gcn Dockerfile

The new HIP patch includes a change that allows
calls to hipDeviceSynchronize() (and other functions
that call locked_wait()) to run without crashing

Change-Id: Iae6656c19168de696b0f94503e703be67f0baa09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31794
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Standardize console output in the m5 writefile command.

When the command reports an error, it should then exit(2) and not just
return as if everything worked. When printing the number of bytes
written or the file being opened, it should write this non-error message
to cout, and not cerr.

Also used proper capitalization and punctuation in a couple messages.

Change-Id: I2c0d6592357965ed2eee8f090c8b3d530b354b9f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27627
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a unit test for the m5 utility's "readfile" command.

This feeds a fake file to the readfile command which is just a sequence
of incrementing 32 bit values. The incrementing values make sure that
the right region of the input file is being read at the right position,
and the relatively small size means there shouldn't be tons of zeroes
everywhere which can't be distinguished from each other.

Change-Id: I4286b1f92684f127c4885c29192c6c5244a61855
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27608
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

util: Add unit tests for most remaining m5 utility commands.

The only two which still need unit tests are the more complex commands,
readfile and writefile.

Change-Id: Ib9984c71fb4449cbbbd1e2a43f3140975328d31f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27607
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a unit test for the m5 util's "sum" command.

This change adds the plumbing for and then implements a unit test for
the "sum" command. Despite the fact that this command is very simple,
there are a few things to verify.

1. That args are passed in the right positions.
2. That the number of arguments is checked correctly.
3. That the output to std::cerr is correct.

Change-Id: I71cd473b78fb710cac94df2d70c8d6dc76e5a037
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27566
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Make m5 commands return a bool instead of calling usage.

By delegating actually calling usage() elsewhere, we can remove a dependency
from the commands themselves, and also make testing easier since we won't
exit() every time we call a command with bad arguments.

Change-Id: I6b8e2cb77ce0456b16673f10349362cc53218bba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27565
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Split up the commands into separate files in the m5 util.

This way each individual command can have a unit test written for it,
covering how it gathers its arguments and puts them passes them to the
underlying dispatch function.

Change-Id: Ia629c412c8906fc6f5ae02c509ed630755cee45c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27564
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a "command" unit test for the m5 utility.

This tests the common "command" machinery, but not the individual
commands themselves.

Change-Id: I92769b4cef8210458786e60fd3c01e8e787fb9b2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27563
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

util: Redistribute command code in the m5 utility.

This division will make it easier to test both the common command code,
and the individual commands.

Change-Id: Ib7be2b93e40d07e9724443ba26784e45ad9d3b17
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27562
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a "call_type" unit test to the m5 utility.

Change-Id: I6ffdf1242a063e776dbb7c18664755773a591b8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27561
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

util: Add an "args" unit test to the m5 utility.

Change-Id: I7460daaff3301b09e071f2b7e8fb657909805438
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27560
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Make the googletest library available to the m5 utility.

The library will be available for the abis so that they can test
their unique call mechanisms, and also the main/native environment for
testing shared components.

Build instructions for things that should be built natively, ie unit
tests for common components, should go in the new SConscript.native.

Change-Id: I4a84b2cf2165c92dfb1b6d903b18b45e4cba1352
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27559
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Use lookup function in cache

There is a function to perform lookups; there is no need to replicate
its code everywhere.

Change-Id: I1290594615d282722cd91071be8ef3c372414e4e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23946
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Cleanup replacement_data usage

The replacement_data can be assigned as soon as a block is allocated.
With this cleanup the lookup function can be used to avoid code
duplication.

Change-Id: I7561fddaa3ed348866699ecaf1e6aa477ba0bc9a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23945
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Getter/setter for atomic ops in WriteMask

Adding getter and setter methods for getting and setting the atomic ops
in the WriteMask class. This allows for message types with WriteMasks to
get or set the atomic ops without explicitly modifying the constructor
for the message type. This will beused by the DMASequencer which uses the
SequencerMsg type where the constructor is auto generated via SLICC.

Change-Id: I71787d294c1b89547618e9a13e386b65bb3e1021
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31474
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix Trap to EL1 on register DC CVAU

Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31774
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Expose the "sum" m5 op in the m5 utility.

This is just for testing purposes, and can be used to sanity check that
m5 ops work when running a simulation.

Change-Id: I784d033fe4704e60ace5d109beac7bafe1498de6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27558
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,sim,misc: Add a new m5 op "sum" which just sums its inputs.

This very simple and mostly useless operation has no side effects, and
can be used to verify that arguments are making it into gem5, being
operated on, and then that a result can be returned into the simulation.

Change-Id: I29bce824078526ff77513c80365f8fad88fef128
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27557
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Make the device file name used by map_m5_mem overridable.

The name this function uses is now exposed as a global variable called
m5_mmap_dev which can be changed at run time.

This would be useful if using a non-standard location for /dev/mem, or
for testing where we might want to use a totally different device.

Change-Id: I5e7ac106c3e4e0555c99af2a7a0aca8171534451
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27556
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: c++-ify usage printing in the m5 utility.

Change-Id: Ice8641d490fa9a510a6f1e246530ca5c82ef8170
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27555
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>