mesa.git
11 years agomesa: Make Mesa core set up wrapped texture renderbuffer state.
Eric Anholt [Mon, 22 Apr 2013 18:04:21 +0000 (11:04 -0700)]
mesa: Make Mesa core set up wrapped texture renderbuffer state.

Everyone was doing effectively the same thing, except for some funky code
reuse in Intel, and swrast mistakenly recomputing _BaseFormat instead of
using the texture's _BaseFormat.  swrast's sRGB handling is left in place,
though it should be done by using _mesa_get_render_format() at render time
instead (as-is, it will miss updates to GL_FRAMEBUFFER_SRGB).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
11 years agointel: Simplify renderbuffer-for-texture width setup.
Eric Anholt [Mon, 22 Apr 2013 18:07:59 +0000 (11:07 -0700)]
intel: Simplify renderbuffer-for-texture width setup.

We're looking for the logical width of our level, which is what
image->Width2/Height2 is.  The previous code relied on MSAA textures being
only level 0.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
11 years agomesa: Make core Mesa allocate the texture renderbuffer wrapper.
Eric Anholt [Mon, 22 Apr 2013 17:38:41 +0000 (10:38 -0700)]
mesa: Make core Mesa allocate the texture renderbuffer wrapper.

Every driver did the same thing.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
11 years agoi965: Use brw_blorp_blit_miptrees() for CopyTexSubImage().
Eric Anholt [Tue, 30 Apr 2013 18:15:05 +0000 (11:15 -0700)]
i965: Use brw_blorp_blit_miptrees() for CopyTexSubImage().

Now that depth resolves are handled there, we don't need to make the
temporary renderbuffer.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
11 years agoi965: Move blorp resolve setup into brw_blorp_blit_miptrees().
Eric Anholt [Tue, 30 Apr 2013 17:48:09 +0000 (10:48 -0700)]
i965: Move blorp resolve setup into brw_blorp_blit_miptrees().

There was some comment about trying to avoid marking resolves in
updownsample, but if the downsample is never actually rendered to, then
the required resolve tracked in the downsample will never be executed, so
who cares?

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
11 years agogallivm: Fix build for LLVM < 3.3
Tom Stellard [Mon, 6 May 2013 16:58:56 +0000 (09:58 -0700)]
gallivm: Fix build for LLVM < 3.3

The C API versions of the LLVM multithreaded functions were added in
LLVM 3.3.

11 years agor600g/llvm: Parse config values in register / value pairs
Tom Stellard [Fri, 3 May 2013 20:10:29 +0000 (13:10 -0700)]
r600g/llvm: Parse config values in register / value pairs

Rather than relying on a predetermined order for the config values.

11 years agor600g/llvm: Don't feed LLVM output through r600_bytecode_build()
Tom Stellard [Fri, 3 May 2013 18:38:50 +0000 (11:38 -0700)]
r600g/llvm: Don't feed LLVM output through r600_bytecode_build()

The LLVM backend emits raw ISA now, so we can just its output
unmodified.

11 years agor600g/llvm: Don't emit CALL_FS for vertex shaders
Tom Stellard [Fri, 3 May 2013 18:15:55 +0000 (11:15 -0700)]
r600g/llvm: Don't emit CALL_FS for vertex shaders

The LLVM backend takes care of this now.

11 years agoi965: Lower bitfieldInsert.
Matt Turner [Thu, 11 Apr 2013 22:49:32 +0000 (15:49 -0700)]
i965: Lower bitfieldInsert.

v2: Only lower bitfieldInsert to BFM+BFI (and don't lower
    bitfieldExtract at all) since three-source instructions are now
    usable in the vertex shader.
v3: Lower bitfield_insert in the same pass with everything else, since
    it doesn't produce any instructions to be lowered (the other two
    lowering passes that were in a previous iteration of this series
    emitted subtractions which needed to be lowered).

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
11 years agoi965/vs: Add support for bit instructions.
Matt Turner [Thu, 18 Apr 2013 01:57:58 +0000 (18:57 -0700)]
i965/vs: Add support for bit instructions.

v2: Rebase on LRP addition.
    Use fix_3src_operand() when emitting BFE and BFI2.
    Add BFE and BFI2 to is_3src_inst check in
      brw_vec4_copy_propagation.cpp.
    Subtract result of FBH from 31 (unless an error) to convert
      MSB counts to LSB counts

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
11 years agoi965/fs: Add support for bit instructions.
Matt Turner [Wed, 10 Apr 2013 02:22:34 +0000 (19:22 -0700)]
i965/fs: Add support for bit instructions.

Don't bother scalarizing ir_binop_bfm, since its results are
identical for all channels.

v2: Subtract result of FBH from 31 (unless an error) to convert
    MSB counts to LSB counts.
v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref
    channel_expressions) from appearing multiple times in the IR.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
11 years agoi965: Add support for emitting and disassembling bit instructions.
Matt Turner [Wed, 10 Apr 2013 00:56:19 +0000 (17:56 -0700)]
i965: Add support for emitting and disassembling bit instructions.

Specifically
   bfe - for bitfieldExtract()
   bfi1 and bfi2 - for bitfieldInsert()
   bfrev - for bitfieldReverse()
   cbit - for bitCount()
   fbh - for findMSB()
   fbl - for findLSB()

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
11 years agoi965: Print the correct dst and shared-src types for 3-src instructions.
Matt Turner [Sun, 21 Apr 2013 04:41:15 +0000 (21:41 -0700)]
i965: Print the correct dst and shared-src types for 3-src instructions.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
11 years agoi965/gen7: Set src/dst types for 3-src instructions.
Matt Turner [Wed, 17 Apr 2013 19:23:54 +0000 (12:23 -0700)]
i965/gen7: Set src/dst types for 3-src instructions.

Also update asserts to allow BFE and BFI2, which take (unsigned)
doubleword arguments.

v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well.
    Assert that src2.type (instead of src0.type) matches dest.type since
    it's the primary argument and src0 and src1 might correctly have
    different types.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v1]
11 years agoi965: Add 3-src destination and shared-source type macros.
Matt Turner [Wed, 17 Apr 2013 18:52:00 +0000 (11:52 -0700)]
i965: Add 3-src destination and shared-source type macros.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
11 years agoi965: Add Gen7+ fields to brw_instruction and add comments.
Matt Turner [Wed, 17 Apr 2013 18:32:04 +0000 (11:32 -0700)]
i965: Add Gen7+ fields to brw_instruction and add comments.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
11 years agoglsl: Add a pass to lower bitfield-insert into bfm+bfi.
Matt Turner [Wed, 10 Apr 2013 05:43:05 +0000 (22:43 -0700)]
glsl: Add a pass to lower bitfield-insert into bfm+bfi.

i965/Gen7+ and Radeon/Evergreen+ have bfm/bfi instructions to implement
bitfieldInsert() from ARB_gpu_shader5.

v2: Add ir_binop_bfm and ir_triop_bfi to st_glsl_to_tgsi.cpp.
    Remove spurious temporary assignment and dereference.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
11 years agoglsl: Add constant evaluation of bit built-ins.
Matt Turner [Sun, 21 Apr 2013 19:33:59 +0000 (12:33 -0700)]
glsl: Add constant evaluation of bit built-ins.

v2: Order bits from LSB end (31 - count) for ir_unop_find_msb.
v3: Add ir_triop_bitfield_extract as an exception to the op[0]->type ==
    op[1]->type assertion in ir_constant_expression.cpp.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
11 years agoglsl: Add support for new bit built-ins in ARB_gpu_shader5.
Matt Turner [Wed, 10 Apr 2013 00:45:12 +0000 (17:45 -0700)]
glsl: Add support for new bit built-ins in ARB_gpu_shader5.

v2: Move use of ir_binop_bfm and ir_triop_bfi to a later patch.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
11 years agoglsl: Add new bit built-ins IR and prototypes from ARB_gpu_shader5.
Matt Turner [Tue, 9 Apr 2013 23:03:15 +0000 (16:03 -0700)]
glsl: Add new bit built-ins IR and prototypes from ARB_gpu_shader5.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
11 years agoglsl: Rework ir_reader to handle expressions with four operands.
Matt Turner [Tue, 9 Apr 2013 23:43:14 +0000 (16:43 -0700)]
glsl: Rework ir_reader to handle expressions with four operands.

Needed to support the bitfieldInsert() built-in added by
ARB_gpu_shader5.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
11 years agomesa: Add infrastructure for ARB_gpu_shader5.
Matt Turner [Tue, 9 Apr 2013 23:01:38 +0000 (16:01 -0700)]
mesa: Add infrastructure for ARB_gpu_shader5.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
11 years agoradeon/llvm: Always build libradeonllvm as static
Tom Stellard [Wed, 24 Apr 2013 03:14:01 +0000 (20:14 -0700)]
radeon/llvm: Always build libradeonllvm as static

This library is very small, so there is not much to gain from building
it as a shared library.  Also, when linking statically with LLVM, a
shared libradeonllvm exports LLVM symbols and creates problems when
used with other shared objects that also link statically to LLVM.

Reviewed-by: Mathias.Froehlich@web.de
11 years agoradeon/llvm: Use LLVM C API for compiling LLVM IR to ISA v2
Tom Stellard [Tue, 2 Apr 2013 17:42:50 +0000 (10:42 -0700)]
radeon/llvm: Use LLVM C API for compiling LLVM IR to ISA v2

The LLVM C API is considered stable and should never change, so it
is much more desirable to use than the LLVM C++ API, which is constantly in
flux.

v2:
  - Split target initialization and lookup into separate functions

Reviewed-by: Mathias.Froehlich@web.de
11 years agogallivm: Move LLVMStartMultithreaded() static initializer into gallivm
Tom Stellard [Tue, 30 Apr 2013 14:38:03 +0000 (07:38 -0700)]
gallivm: Move LLVMStartMultithreaded() static initializer into gallivm

This does not solve all of the problems with using LLVM in a
multithreaded enivronment, but it should help in some cases.

Reviewed-by: Mathias.Froehlich@web.de
11 years agoradeon/llvm: Don't use the global context when parsing LLVM IR
Tom Stellard [Thu, 2 May 2013 22:25:53 +0000 (18:25 -0400)]
radeon/llvm: Don't use the global context when parsing LLVM IR

This leads to crashes when multiple threads try to compile compute
shaders in the same time.

Fixes a crash in bfgminer when using more than one thread.

11 years agoi965: Remove GL_ARB_color_buffer_float from GL core contexts.
Eric Anholt [Thu, 25 Apr 2013 19:06:23 +0000 (12:06 -0700)]
i965: Remove GL_ARB_color_buffer_float from GL core contexts.

Of the 3 controls in the extension, one was kept in GL core and the other
two were explicitly deprecated and the reasonable default behavior was
encoded in the spec.  By not exposing the extension, we avoid shader
recompiles when switching between float and unorm color buffers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
11 years agor600g/llvm: Update radeon family mappings for LLVM backend
Tom Stellard [Mon, 29 Apr 2013 20:10:09 +0000 (13:10 -0700)]
r600g/llvm: Update radeon family mappings for LLVM backend

New processors were added to the backend to distinguish between
GPUs with and without vertex caches.

11 years agoandroid: libsync is needed on Android 4.2+ for any driver
Chia-I Wu [Fri, 3 May 2013 07:44:10 +0000 (15:44 +0800)]
android: libsync is needed on Android 4.2+ for any driver

Add libsync not only for MESA_BUILD_CLASSIC, but also for MESA_BUILD_GALLIUM.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
11 years agoandroid: add ilo to the build system
Chia-I Wu [Fri, 3 May 2013 07:44:09 +0000 (15:44 +0800)]
android: add ilo to the build system

It can be selected with

  BOARD_GPU_DRIVERS := ilo

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
11 years agoglsl: Flip around "if" statements with empty "then" blocks.
Eric Anholt [Fri, 3 May 2013 20:17:56 +0000 (13:17 -0700)]
glsl: Flip around "if" statements with empty "then" blocks.

This cleans up some funny-looking code in some unigine shaders I was
looking at.  Also slightly helps on planeshift and a few shaders in an
upcoming Valve release.

total instructions in shared programs: 1653715 -> 1653587 (-0.01%)
instructions in affected programs:     16550 -> 16422 (-0.77%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
11 years agoilo: correctly set return types of sampler messages
Chia-I Wu [Sun, 5 May 2013 06:13:39 +0000 (14:13 +0800)]
ilo: correctly set return types of sampler messages

Correctly set the types of the temporaries.  We do not want type conversions
when moving the results to the final destinations.

11 years agor600g/llvm: Undefines unrequired texture coord values
Vincent Lejeune [Tue, 30 Apr 2013 13:58:00 +0000 (15:58 +0200)]
r600g/llvm: Undefines unrequired texture coord values

This is a port of "r600g:mask unused source components for SAMPLE"
patch from Vadim Girlin.

11 years agonvc0: fixup video decoding with 2D_ARRAY
Maarten Lankhorst [Sat, 4 May 2013 18:56:02 +0000 (20:56 +0200)]
nvc0: fixup video decoding with 2D_ARRAY

Signed-off-by: Maarten Lankhorst <m.b.lankhorst@gmail.com>
11 years agogallium: fix type of flags in pipe_context::flush()
Chia-I Wu [Thu, 2 May 2013 08:25:15 +0000 (16:25 +0800)]
gallium: fix type of flags in pipe_context::flush()

It should be unsigned, not enum pipe_flush_flags.

Fixed a build error:

  src/gallium/state_trackers/egl/android/native_android.cpp:426:29: error:
  invalid conversion from 'int' to 'pipe_flush_flags' [-fpermissive]

v2: replace all occurrences of enum pipe_flush_flags by unsigned

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
[olv: document the parameter now that the type is unsigned]

11 years agoi965: Enable fast clears on non-8x4-aligned sizes.
Eric Anholt [Tue, 23 Apr 2013 20:58:31 +0000 (13:58 -0700)]
i965: Enable fast clears on non-8x4-aligned sizes.

Improves glb2.7 performance at a misaligned size by 2.3% +/- 0.7% (n=11).
The workaround was to avoid bad primitive/surface sizes, but that's worked
around as of a14dc4f92cdad6177d83f051a088a66e31a973bc.  (One might note
that pre-gen7 we don't know that the right half of an 8x4 at the right
edge is actually our pixels, but we're already clobbering those pixels for
depth resolves anyway and more work would be required to avoid that).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
11 years agovbo: add comments, const qualifiers
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
vbo: add comments, const qualifiers

Reviewed-by: José Fonseca <jfonseca@vmware.com>
11 years agomesa: whitespace, formatting fixes, etc in api_arrayelt.c
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
mesa: whitespace, formatting fixes, etc in api_arrayelt.c

Reviewed-by: José Fonseca <jfonseca@vmware.com>
11 years agovbo: use new no-op ArrayElement in _mesa_noop_vtxfmt_init()
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
vbo: use new no-op ArrayElement in _mesa_noop_vtxfmt_init()

As we do for the other commands which can appear between glBegin/End.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
11 years agomesa: change ctx->Driver.NeedFlush to GLbitfield and update comment
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
mesa: change ctx->Driver.NeedFlush to GLbitfield and update comment

Reviewed-by: José Fonseca <jfonseca@vmware.com>
11 years agomesa; change ctx->Driver.SaveNeedFlush to boolean, and document it.
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
mesa; change ctx->Driver.SaveNeedFlush to boolean, and document it.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
11 years agovbo: update comments for vbo_save_NotifyBegin()
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
vbo: update comments for vbo_save_NotifyBegin()

Reviewed-by: José Fonseca <jfonseca@vmware.com>
11 years agovbo: implement primitive merging for glBegin/End sequences
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
vbo: implement primitive merging for glBegin/End sequences

A surprising number of apps and benchmarks have poor code like this:

glBegin(GL_LINE_STRIP);
glVertex(v1);
glVertex(v2);
glEnd();
// Possibly some no-op state changes here
glBegin(GL_LINE_STRIP);
glVertex(v3);
glVertex(v4);
glEnd();
// repeat many, many times.

The above sequence can be converted into:

glBegin(GL_LINES);
glVertex(v1);
glVertex(v2);
glVertex(v3);
glVertex(v4);
glEnd();

Similarly for GL_POINTS, GL_TRIANGLES, etc.

Merging was already implemented for GL_QUADS in the display list code.
Now other prim types are handled and it's also done for immediate mode.

In one case:
                                 before   after
-----------------------------------------------
number of st_draw_vbo() calls:     141      45
number of _mesa_prims issued:     7520     632

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
11 years agovbo: create a few utility functions for merging primitives
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
vbo: create a few utility functions for merging primitives

To be used by following commit.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
11 years agodraw/pt: adjust overflow calculations
Zack Rusin [Fri, 3 May 2013 03:38:28 +0000 (23:38 -0400)]
draw/pt: adjust overflow calculations

gallium lies. buffer_size is not actually buffer_size but available
size, which is 'buffer_size - buffer_offset' so by adding buffer
offset we'd incorrectly compute overflow.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
11 years agotgsi/ureg: make the dst register match the src indirection
Zack Rusin [Thu, 2 May 2013 07:47:07 +0000 (03:47 -0400)]
tgsi/ureg: make the dst register match the src indirection

In ureg src registers could have an indirect register that was
either a temp or an addr register, while dst registers allowed
only addr. That made moving between them a little difficult so
make them behave the same way and allow temp's and addr registers
as indirect files for both (tgsi supports it, just ureg didn't).

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
11 years agogallium: tgsi documentation updates and clarification for integer opcodes.
Roland Scheidegger [Fri, 3 May 2013 19:34:12 +0000 (21:34 +0200)]
gallium: tgsi documentation updates and clarification for integer opcodes.

A lot of them were missing. Others were moved from the Compute ISA
to a new Integer ISA section as that seemed more appropriate.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
11 years agollvmpipe: get rid of depth swizzling.
Roland Scheidegger [Wed, 1 May 2013 15:54:08 +0000 (17:54 +0200)]
llvmpipe: get rid of depth swizzling.

Eliminating this we no longer need to copy between linear and swizzled layout.
This is probably not quite ideal since it's a bit more work for now, could do
some optimizations by moving depth testing outside the fragment shader loop
(but tricky for early depth test as we don't have neither the mask nor the
interpolated z in the right order handy).
The large amount of tile/untile code is no longer needed will be deleted
in next commit.
No piglit regressions.
v2: change a forgotten LAYOUT_NONE to LAYOUT_LINEAR.
v3: fix (bogus) uninitialized variable warnings, add comments, fix a bad type

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
11 years agor600g: Correctly initialize the shader key, v2
Lauri Kasanen [Fri, 3 May 2013 13:55:49 +0000 (16:55 +0300)]
r600g: Correctly initialize the shader key, v2

Assigning a struct only copies the members - any padding is left as is.

Thus this code:

struct foo_t foo;
foo = bar;

leaves the padding of foo intact, ie uninitialized random garbage.

This patch fixes constant shader recompiles by initializing the struct
to zero. For completeness, memcpy is used to copy the key to the shader
struct.

NOTE: This is a candidate for the stable branches.

Signed-off-by: Lauri Kasanen <cand@gmx.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
11 years agost/xvmc/tests: Fix build failure, v2
Lauri Kasanen [Fri, 3 May 2013 08:48:53 +0000 (11:48 +0300)]
st/xvmc/tests: Fix build failure, v2

v2: Removed extra libs as requested by Matt Turner.

Signed-off-by: Lauri Kasanen <cand@gmx.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
11 years agoscons: remove nouveau build
Andreas Boll [Fri, 3 May 2013 09:41:00 +0000 (11:41 +0200)]
scons: remove nouveau build

One build system for linux/unix only drivers should be enough.
Additionally the nouveau target was disabled anyway.

Acked-by: Jose Fonseca <jfonseca@vmware.com>
11 years agoscons: remove radeon build
Andreas Boll [Fri, 3 May 2013 09:33:35 +0000 (11:33 +0200)]
scons: remove radeon build

One build system for linux/unix only drivers should be enough.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48694

Acked-by: Jose Fonseca <jfonseca@vmware.com>
11 years agor600g: don't emit surface_sync after FLUSH_AND_INV_EVENT
Alex Deucher [Fri, 3 May 2013 13:56:31 +0000 (09:56 -0400)]
r600g: don't emit surface_sync after FLUSH_AND_INV_EVENT

It shouldn't be needed since the FLUSH_AND_INV_EVENT has already
made sure the destination caches are flushed.  Additionally,
we didn't previously emit the surface_sync until this commit:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5e4c07e7964a3258ed02b530bcdc24c0650204b
Emitting them together causes hangs in compute on cayman/TN
and hangs in Heaven on evergreen.

Note: this patch is a candidate for the 9.1 branch, but requires:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=156bcca62c9f4e79e78929f72bc085757f36a65a
as well.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
11 years agor600g/sb: zero-initialize bytecode structs
Vadim Girlin [Fri, 3 May 2013 12:53:27 +0000 (16:53 +0400)]
r600g/sb: zero-initialize bytecode structs

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
11 years agor600g/sb: fix constant propagation in gvn pass
Vadim Girlin [Fri, 3 May 2013 09:01:31 +0000 (13:01 +0400)]
r600g/sb: fix constant propagation in gvn pass

Fixes the bug that prevented propagation of literals in some cases.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
11 years agor600g/sb: don't run unnecessary passes
Vadim Girlin [Thu, 2 May 2013 15:36:52 +0000 (19:36 +0400)]
r600g/sb: don't run unnecessary passes

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
11 years agor600g/sb: silence warnings with gcc 4.8
Vadim Girlin [Thu, 2 May 2013 06:36:18 +0000 (10:36 +0400)]
r600g/sb: silence warnings with gcc 4.8

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
11 years agor600g/sb: fix handling of interference sets in post_scheduler
Vadim Girlin [Thu, 2 May 2013 03:53:00 +0000 (07:53 +0400)]
r600g/sb: fix handling of interference sets in post_scheduler

post_scheduler clears interference set for reallocatable values when
the value becomes live first time, and then updates it to take into
account modified order of operations, but this was not handled properly
if the value appears first time as a source in copy operation.

Fixes issues with webgl demo: http://madebyevan.com/webgl-water/

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
11 years agor600g/sb: fix allocation of indirectly addressed input arrays
Vadim Girlin [Thu, 2 May 2013 03:56:32 +0000 (07:56 +0400)]
r600g/sb: fix allocation of indirectly addressed input arrays

Some inputs may be preloaded into predefined GPRs,
so we can't reallocate arrays with such inputs.

Fixes issues with webgl demo: http://oos.moxiecode.com/js_webgl/snake/

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
11 years agor600g/sb: use hex instead of binary constants
Vadim Girlin [Wed, 1 May 2013 17:33:33 +0000 (21:33 +0400)]
r600g/sb: use hex instead of binary constants

This should fix build issues with GCC < 4.3

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
11 years agor600g: use old shader disassembler by default
Vadim Girlin [Fri, 3 May 2013 08:01:20 +0000 (12:01 +0400)]
r600g: use old shader disassembler by default

New disassembler is not completely isolated yet from further processing
in r600g/sb that is not required for printing the dump, so it has higher
probability to fail in case of any unexpected features in the bytecode.

This patch adds "sbdisasm" flag for R600_DEBUG that allows to use new
disassembler in r600g/sb for shader dumps when shader optimization
is not enabled.

If shader optimization is enabled, new disassembler is used by default.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
11 years agoradeon/uvd: enable interlaced buffers by default
Christian König [Thu, 2 May 2013 14:19:41 +0000 (16:19 +0200)]
radeon/uvd: enable interlaced buffers by default

Kills tilling on UVD buffers, but we currently don't really need that.

Signed-off-by: Christian König <christian.koenig@amd.com>
11 years agovl/idct: fix for commit 7d2f2a0c890b1993532a45c8c392c28950ddc06e
Christian König [Thu, 2 May 2013 14:02:05 +0000 (16:02 +0200)]
vl/idct: fix for commit 7d2f2a0c890b1993532a45c8c392c28950ddc06e

We still need the option for handling 3D textures as well.

Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=64143

Signed-off-by: Christian König <christian.koenig@amd.com>
11 years agovl/buffers: fix typo in function name
Christian König [Thu, 2 May 2013 13:42:24 +0000 (15:42 +0200)]
vl/buffers: fix typo in function name

Signed-off-by: Christian König <christian.koenig@amd.com>
11 years agoradeon/uvd: fix some MPEG4 artifacts
Christian König [Wed, 1 May 2013 12:33:49 +0000 (14:33 +0200)]
radeon/uvd: fix some MPEG4 artifacts

Still not perfect, but a step in the right direction.

Signed-off-by: Christian König <christian.koenig@amd.com>
11 years agodraw: Update for u_assembled_primitive -> u_assembled_prim rename.
José Fonseca [Fri, 3 May 2013 07:35:17 +0000 (08:35 +0100)]
draw: Update for u_assembled_primitive -> u_assembled_prim rename.

Mesa build is too complex to rely on successful builds. On refactorings
it is always a good idea to use git grep to prevent missing cases:

  $ git grep u_assembled_primitive
  src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline_llvm.c:      u_assembled_primitive(in_prim);

11 years agost/egl: fix bulid errors on Android 4.2
Chia-I Wu [Thu, 2 May 2013 08:13:28 +0000 (16:13 +0800)]
st/egl: fix bulid errors on Android 4.2

The differences from the previous releases that affect st/egl are

 - logging macros are prefixed with an 'A'
 - dequeueBuffer() and enqueueBuffer() require an additoinal argument for
   fence fd, acquired from libsync

Additionally, include gralloc_drm.h with extern "C".

11 years agoilo: use u_reduced_prims_for_vertices()
Chia-I Wu [Thu, 2 May 2013 06:32:30 +0000 (14:32 +0800)]
ilo: use u_reduced_prims_for_vertices()

We do not need our own prim_count() anymore.

11 years agoutil/prim: add u_reduced_prims_for_vertices()
Chia-I Wu [Thu, 2 May 2013 06:28:12 +0000 (14:28 +0800)]
util/prim: add u_reduced_prims_for_vertices()

The function returns the number of reduced/tessellated primitives for the
given vertex count.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
11 years agoutil/prim: assorted fixes for u_decomposed_prims_for_vertices()
Chia-I Wu [Thu, 2 May 2013 06:12:27 +0000 (14:12 +0800)]
util/prim: assorted fixes for u_decomposed_prims_for_vertices()

Switch to '>=' for comparisons, and it becomes obvious that the comparison for
PIPE_PRIM_QUAD_STRIP was wrong.

Add minimum vertex count check for PIPE_PRIM_LINE_LOOP.  Return 1 for
PIPE_PRIM_POLYGON with 3 vertices.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
11 years agoutil/prim: use vertex count info in u_validate_pipe_prim()
Chia-I Wu [Thu, 2 May 2013 05:49:30 +0000 (13:49 +0800)]
util/prim: use vertex count info in u_validate_pipe_prim()

As a side effect, primitives with adjacency are now correctly validated.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
11 years agoutil/prim: fix the name of the include guard
Chia-I Wu [Thu, 2 May 2013 05:46:21 +0000 (13:46 +0800)]
util/prim: fix the name of the include guard

It should be U_PRIM_H, not U_BLIT_H.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
11 years agodraw: use u_assembled_prim() instead of u_assembled_primitive()
Chia-I Wu [Thu, 2 May 2013 07:49:35 +0000 (15:49 +0800)]
draw: use u_assembled_prim() instead of u_assembled_primitive()

The latter function is also removed as a result of the change.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
11 years agoutil/prim: clean up and add comments
Chia-I Wu [Thu, 2 May 2013 05:29:59 +0000 (13:29 +0800)]
util/prim: clean up and add comments

Move together (or add) functions to decompose/reduce/assemble a primitive,
give them consistent names, and document them.  Add u_prim_vertex_count() so
that the vertex count information can be used elsewhere.

u_assembled_primitive() will be removed in a folow-on commit.

[olv: fix a warning when -Wold-style-declaration is enabled]

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
11 years agoutil/prim: fix primitive trimming for triangles with adjacency
Chia-I Wu [Thu, 2 May 2013 03:25:39 +0000 (11:25 +0800)]
util/prim: fix primitive trimming for triangles with adjacency

Fix for PIPE_PRIM_TRIANGLES_ADJACENCY and PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
11 years agoi965/vs: Add instruction scheduling.
Eric Anholt [Sat, 1 Dec 2012 00:13:34 +0000 (16:13 -0800)]
i965/vs: Add instruction scheduling.

While this is ignorant of dependency control, it's still good for a 0.39%
+/- 0.08% performance improvement on GLBenchmark 2.7 (n=548)

v2: Rewrite as a subclass of the base class for the FS instruction
    scheduler, inheriting the same latency information.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
11 years agoi965: Move most of the FS instruction scheduler code to a general class.
Eric Anholt [Mon, 29 Apr 2013 21:05:33 +0000 (14:05 -0700)]
i965: Move most of the FS instruction scheduler code to a general class.

About half of this is shareable with the VS code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
11 years agoi965: Pull a couple of FS scheduling functions out to methods.
Eric Anholt [Mon, 29 Apr 2013 23:45:10 +0000 (16:45 -0700)]
i965: Pull a couple of FS scheduling functions out to methods.

These will get virtualized as we add VS scheduling support.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
11 years agoi965: Move FS instruction scheduling to a non-FS-specific file.
Eric Anholt [Mon, 29 Apr 2013 20:59:38 +0000 (13:59 -0700)]
i965: Move FS instruction scheduling to a non-FS-specific file.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
11 years agoi965: Share the register file enum between the two backends.
Eric Anholt [Mon, 29 Apr 2013 23:05:05 +0000 (16:05 -0700)]
i965: Share the register file enum between the two backends.

I need this so I can look at vec4 and fs registers' files from the same
.cpp file without namespaces.  As far as I can tell we never rely on the
particular numerical values of the files, though I thought it sounded like
a good idea when doing the VS (it turns out having 0 be BAD_FILE is nicer).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
11 years agoi965: Make dump_instructions be a virtual method of the visitor.
Eric Anholt [Mon, 29 Apr 2013 21:21:14 +0000 (14:21 -0700)]
i965: Make dump_instructions be a virtual method of the visitor.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
11 years agoi965/vs: Do round-robin register allocation on gen6+ like we do in the FS.
Eric Anholt [Mon, 29 Apr 2013 18:48:22 +0000 (11:48 -0700)]
i965/vs: Do round-robin register allocation on gen6+ like we do in the FS.

This will free instruction scheduling to make better choices.  No
statistically significant performance difference on GLB2.7 (n=93).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
11 years agowayland: Make eglQueryBufferWL succeed for width and height requests too
Rob Bradford [Wed, 10 Apr 2013 10:36:24 +0000 (11:36 +0100)]
wayland: Make eglQueryBufferWL succeed for width and height requests too

Following the addition of the EGL_WIDTH and EGL_HEIGHT this function should
return EGL_TRUE for those requested attributes too.

11 years agodraw/gs: don't crash when vs/gs signatures don't match
Zack Rusin [Thu, 2 May 2013 01:09:32 +0000 (21:09 -0400)]
draw/gs: don't crash when vs/gs signatures don't match

instead of crashing just fill zeros at the input slots that don't
match, that's the mandated behavior and it avoids debug asserts.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
11 years agotgsi: allow negation of all integer types
Zack Rusin [Sun, 28 Apr 2013 14:50:55 +0000 (10:50 -0400)]
tgsi: allow negation of all integer types

It's valid because we reuse certain arithmetic operations
for both signed and unsigned types (e.g. uadd, umad, which
have a bit unfortunate naming)

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
11 years agoi965: Fix SNB GPU hangs when a blorp batch is the first thing to execute.
Eric Anholt [Wed, 1 May 2013 23:08:12 +0000 (16:08 -0700)]
i965: Fix SNB GPU hangs when a blorp batch is the first thing to execute.

The GPU apparently goes looking for constants even though there are no
shader stages enabled, and gets stuck because we haven't told it there are
no constants to collect.  If any other user of the 3D pipeline had run
(even the Render accel of the X server!) since power on, then the in-GPU
constant buffers would have been set up with some contents we didn't use,
and we would succeed.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56416
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Dave Airlie <airlied@redhat.com>
NOTE: This is a candidate for the stable branches.

11 years agor600g: Don't set the dest cache bits on surface sync for R600_CONTEXT_FLUSH_AND_INV
Tom Stellard [Fri, 26 Apr 2013 17:21:06 +0000 (13:21 -0400)]
r600g: Don't set the dest cache bits on surface sync for R600_CONTEXT_FLUSH_AND_INV

We are already emitting a EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT packet
when this flush flag is set, so flushing the dest caches with a
SURFACE_SYNC should not be necessary.

The motivation for this change is that emitting a SURFACE_SYNC packet with
the CB bits set was causing compute shaders to hang on Cayman.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
11 years agor600g/compute: Fix build error in debug code
Tom Stellard [Fri, 26 Apr 2013 17:21:04 +0000 (13:21 -0400)]
r600g/compute: Fix build error in debug code

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
11 years agoradeon: Fix build with LLVM 3.3
Armin K [Thu, 2 May 2013 10:55:05 +0000 (12:55 +0200)]
radeon: Fix build with LLVM 3.3

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
11 years agogallivm: Fix build with LLVM 3.3
Armin K [Thu, 2 May 2013 10:55:04 +0000 (12:55 +0200)]
gallivm: Fix build with LLVM 3.3

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
11 years agomesa: update comments, simplify code in vtxfmt.c
Brian Paul [Thu, 2 May 2013 01:15:33 +0000 (19:15 -0600)]
mesa: update comments, simplify code in vtxfmt.c

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
11 years agomesa: update GLvertexformat comments
Brian Paul [Thu, 2 May 2013 01:15:33 +0000 (19:15 -0600)]
mesa: update GLvertexformat comments

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
11 years agomesa: remove GLvertexformat::EvalMesh1(), EvalMesh2()
Brian Paul [Thu, 2 May 2013 01:15:33 +0000 (19:15 -0600)]
mesa: remove GLvertexformat::EvalMesh1(), EvalMesh2()

See previous commit comments.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
11 years agomesa: remove GLvertexformat::Rectf()
Brian Paul [Thu, 2 May 2013 01:15:33 +0000 (19:15 -0600)]
mesa: remove GLvertexformat::Rectf()

As with the glDraw* functions, this doesn't have to be in GLvertexformat.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
11 years agomesa: simplify dispatch for glDraw* functions
Brian Paul [Thu, 2 May 2013 01:15:33 +0000 (19:15 -0600)]
mesa: simplify dispatch for glDraw* functions

Remove all the glDraw* functions from the GLvertexformat structure.
The point of that dispatch struct is to handle all the functions which
dispatch differently depending on whether we're inside glBegin/End.
glDraw* are never allowed inside glBegin/End so we can remove those
entries.

This simplifies the code paths and gets rid of quite a bit of code.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
11 years agovbo: add new vbo_initialize_exec_dispatch(), vbo_initialize_save_dispatch()
Brian Paul [Thu, 2 May 2013 01:15:33 +0000 (19:15 -0600)]
vbo: add new vbo_initialize_exec_dispatch(), vbo_initialize_save_dispatch()

First step in simplifying the vertex array / glDraw dispatch code.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
11 years agomesa: remove _MESA_INIT_EVAL_VTXFMT() macro
Brian Paul [Thu, 2 May 2013 01:15:33 +0000 (19:15 -0600)]
mesa: remove _MESA_INIT_EVAL_VTXFMT() macro

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
11 years agomesa: remove _MESA_INIT_ARRAYELT_VTXFMT() macro
Brian Paul [Thu, 2 May 2013 01:15:32 +0000 (19:15 -0600)]
mesa: remove _MESA_INIT_ARRAYELT_VTXFMT() macro

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
11 years agomesa: remove _MESA_INIT_DLIST_VTXFMT() macro
Brian Paul [Thu, 2 May 2013 01:15:32 +0000 (19:15 -0600)]
mesa: remove _MESA_INIT_DLIST_VTXFMT() macro

Just expand the code.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>