i965/fs: Don't compute_to_mrf() on Gen >= 7.

No differences in shader-db on Haswell (Gen 7.5).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Remove now useless dot optimization on basis vect

The optimization in commit d056863b covers these cases, which were the
first optimizations I added to the GLSL compiler.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Emit mul instead of dot if only one component left.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85683
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85691
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

clover: Fix clBuildProgram piglit regression

Should trigger CL_INVALID_VALUE if device_list is NULL and num_devices
is greater than zero.

Introduced by e5468dfa523be2a7a0d04bb9efcf8ae780957563

Reported by: EdB

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

gallivm: Disable frame-pointer-omission on x86 to ensure right stack alignment.

Between release 3.2 and 3.3 LLVM stopped aligning properly when certain
conditions (no allocas, but large number of vectors causing spills to
the stack, and frame pointer omission enabled).

We were already disabling frame-pointer-omission on several build types,
but we now disable it on all build types.

It's not clear whether this affects 32-bits x86 processes only, or if it
can also affect 64-bits x86_64 processes when AVX registers are
available and used.  So disable frame-pointer-omission on both
x86/x86_64 to be on the safe side.

See also:
- http://llvm.org/PR21435

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallivm: When disassemble a function, start by printing out its name.

To help recognize what's supposed to do.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

i965/chv: Increase VS and GS thread counts

AFAICT the number of threads is 80, not 70. I am not sure if Ken knows
something I do not.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gallium/docs: fix NRM, NRM4 docs

Need to do a sqrt().

FWIW, the html that Sphinx 1.1.3 generates for the math expressions
looks completely broken.

Reviewed-by: José Fonseca <jfonseca@vmware.com>

softpipe: use the tgsi_free_tokens() function

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

tgsi: add a tgsi_free_tokens() function

To match tgsi_alloc_tokens().

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

util: simplify u_pstipple.c code

Use the new helper functions in the tgsi_transform.h file to emit
declarations and instructions.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

util: simplify temp register selection in u_pstipple.c

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

util: simplify util_pstipple_create_fragment_shader() params

Pass and return tgsi_token buffers instead of pipe_shader_state.

And update softpipe driver (the only user of this function).

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

softpipe: remove unused softpipe_create_fs_variant_exec() parameter

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

softpipe: check for SP_NEW_STIPPLE when building quad pipeline

Fixes polygon stipple if both DO_PSTIPPLE_IN_DRAW_MODULE and
DO_PSTIPPLE_IN_HELPER_MODULE are zero/off.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

r600g: Fix build with opencl and radeonsi disabled

clover: Fix bug when binary programs are passed to clBuildProgram() v2

This was a regression introduced by
611d66fe4513e53bde052dd2bab95d448c909a2a

Passing a binary program to clBuildProgram() is legal, but passing one
to clCompileProgram() is not.

v2:
  - Code cleanups.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

clover: Factor input validation of clCompileProgram into a new function v2

This factors out the validation that is common with clBuildProgram().

v2:
  - Code cleanups.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

radeonsi/compute: Enable PIPE_SHADER_IR_NATIVE for compute shaders v2

v2:
  - Drop dependency on LLVM >= 3.5.1
  - Rename si_create_shader() to si_shader_binary_read()

r600g/compute: Enable PIPE_SHADER_IR_NATIVE for compute shaders v2

v2:
  - Drop dependency on LLVM >= 3.5.1

gallium/radeon: Add query for symbol specific config information

This adds a query which allows drivers to access the config
information of a specific function within the LLVM generated ELF
binary.  This makes it possible for the driver to handle ELF
binaries with multiple kernels / global functions.

r300g: remove enabled/disabled hyperz and AA compression messages

It's annoying with octave. Reported by Michael Burian.

Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org>

r600g: Delete unused variable 'max_global_size' in 'r600_get_compute_param'

Signed-off-by: Dieter Nützel <Dieter@nuetzel-hh.de>

mesa: protect the debug state with a mutex

We are about to change mesa to spawn threads for deferred glCompileShader and
glLinkProgram, and we need to make sure those threads can send compiler
warnings/errors to the debug output safely.

Signed-off-by: Chia-I Wu <olv@lunarg.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: protect glsl_type with a mutex

glsl_type has several static hash tables and a static ralloc context.  They
need to be protected by a mutex as they are not thread-safe.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69200
Signed-off-by: Chia-I Wu <olv@lunarg.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: protect anonymous struct id with a mutex

There may be two contexts compiling shaders at the same time, and we want the
anonymous struct id to be globally unique.

Signed-off-by: Chia-I Wu <olv@lunarg.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

util: initialize locale_t with a static object

_mesa_strtod and _mesa_strtof may be called from multiple threads.  They need
to be thread-safe.

v2: platform checks are now done in configure.ac

Signed-off-by: Chia-I Wu <olv@lunarg.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

configure: check for xlocale.h and strtof

With the assumptions that xlocale.h implies newlocale and strtof_l.  SCons is
updated to define HAVE_XLOCALE_H on linux and darwin.

Signed-off-by: Chia-I Wu <olv@lunarg.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

util: add _mesa_strtod and _mesa_strtof

Both core mesa and glsl have their own wrappers for strtof_l.  Merge
and move them to util/.  They are compiled with a C++ compiler so that
we can make them thread-safe in a following commit.

Signed-off-by: Chia-I Wu <olv@lunarg.com>
Reviewed-by: Kenneth Graunke <kenneth@whiteacpe.org>

mesa/gallium: Signal _NEW_TRANSFORM from glClipControl.

This removes the need for the gallium rasterizer state
to listen to viewport changes.
Thanks to Marek Olšák <maraeo@gmail.com>.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>

Revert "i965/compaction: Disable compaction on SNB temporarily."

This reverts commit cabc93c5adc9ea62be901621eff5ce4cb9574791.

Mark thinks the failures on the SNB GT2 in the lab are actually because
of faulty hardware, not instruction compaction. The GT1 didn't see any
problems after changes to the compaction code.

i965/vec4: Perform CSE on MAD instructions with final arguments switched.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Perform CSE on MAD instructions with final arguments switched.

Multiplication is commutative.

instructions in affected programs:     48314 -> 47954 (-0.75%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Drop constant 0.0 components from dot products.

Helps a small number of vertex shaders in the games Dungeon Defenders
and Shank, as well as an internal benchmark.

instructions in affected programs:     2801 -> 2719 (-2.93%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glx/dri3: Implement LIBGL_SHOW_FPS=1 for DRI3/Present.

v2: Use the UST value provided in the PRESENT_COMPLETE_NOTIFY event
    rather than gettimeofday(), which gives us the presentation time
    instead of the time when SwapBuffers was called.  Suggested by
    Keith Packard.  This relies on the fact that the X DRI3/Present
    implementations use microseconds for UST.

v3: Properly ignore PresentCompleteKindMSCNotify; multiply in 64 bits
    (caught by Keith Packard).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Keith Packard <keithp@keithp.com> [v3]
Reviewed-by: Marek Olšák <marek.olsak@amd.com> [v1]

i965: Rename brw_vec4_gs.[ch] to brw_gs.[ch].

These source files support actual geometry shaders, so using "gs" for
the name makes a lot of sense.  We're going to be adding SIMD8 geometry
shader support as well, at which point "vec4_gs" will be a misnomer.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Rename brw_gs{,_emit}.[ch] to brw_ff_gs{,_emit}.[ch].

The brw_gs.[ch] and brw_gs_emit.c source files contain code for
emulating fixed-function unit functionality (VF primitive decomposition
or SOL) using the GS unit.  They do not contain code to support proper
geometry shaders.

We've taken to calling that code "ff_gs" (see brw_ff_gs_prog_key,
brw_ff_gs_prog_data, brw_context::ff_gs, brw_ff_gs_compile,
brw_ff_gs_prog).  So it makes sense to make the filenames match.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Rename intel_bufferobj_* functions to match GL and DD hooks.

The GL functions and driver hooks use corresponding names---for example,
glMapBufferRange and Driver.MapBufferRange.  But our implementation was
called "intel_bufferobj_map_range," which has the words "map" and
"buffer" swapped, as well as randomly adding "obj."

FlushMappedBufferRange was even trickier: it ordered the words
3, "obj", 1, 2, 4: intel_bufferobj_flush_mapped_range.

Even though the old names were consistent, I always had trouble
rearranging the jumble of words when searching for a function,
and it took a few tries to eventually land there.

The new names match the word order of GL and the driver hooks;
FlushMappedBufferRange is simply brw_flush_mapped_buffer_range.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

configure: fix typos

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

configure: include llvm systemlibs when using static llvm

v2: drop -WL,--exclude-libs, it's not necessary
    fix tabs/spaces

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70410
Tested-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

radeon/llvm: Dynamically allocate branch/loop stack arrays

This prevents us from silently overflowing the stack arrays, and allows
arbitrary stack depths.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85454

Cc: mesa-stable@lists.freedesktop.org
Reported-and-Tested-by: Nick Sarnie <commendsarnex@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: Fix order of errors for glDrawTransformFeedbackStream

The OpenGL 4.0 core profile specification, section 2.17.3
Transform Feedback Draw Operations says:

   "The error INVALID_VALUE is generated if <stream> is greater
    than or equal to the value of MAX_VERTEX_STREAMS.
    ...
    The error INVALID_OPERATION
    is generated if EndTransformFeedback has never been called
    while the object named by id was bound."

Fixes the piglit test:
   ARB_transform_feedback3/arb_transform_feedback3-draw_using_invalid_stream_index
   (with the test itself fixed to eliminate an unrelated failure)

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

vc4: Add support for ARL and indirect register access on TGSI_FILE_CONSTANT.

Fixes 14 ARB_vp tests (which had no lowering done), and should improve
performance of indirect uniform array access in GLSL.

vc4: Fix mixup of return type in reloc_tex().

vc4: Drop redundant check for is_tmu_write().

This function is only called when it would return true.

vc4: Don't forget to validate code that's got PROG_END on it.

This signal doesn't terminate the program now, it terminates the program
soon.  So you have to actually validate the code in the instruction.

vc4: Add .dir-locals.el for kernel style in the kernel code.

vc4: Fix a couple missing '\n's in error output.

st/mesa: use PIPE_BIND_DISPLAY_TARGET when checking for sRGB capability

When we're checking if the framebuffer is sRGB capable, call
is_format_supported() with the PIPE_BIND_DISPLAY_TARGET flag.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

Revert "st/mesa: set MaxUnrollIterations = 255"

This reverts commit 20836c81851e0df29a8ee9c86e5e5388738c840b.

255 is a huge number. If you have a loop with 255 iterations, unrolling it
will exceed the SM3 instruction limit. Let's use the default again.

The comment about a SM3 limit doesn't make sense. For SM3, we generally
want 32 (default) or a lower number due to the SM3 instruction limit, which
is 512 instructions. For SM4, we can try higher numbers if needed, but
some shaders can end up being pretty huge and shader compilation can take
more time.

This fixes a shader compile failure on R500/SM3. Reported on IRC.

Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

r300g/vdpau: enable again

Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

r300g: only set clip_halfz for chips with HW TCL

I forgot that we cannot emit vertex shader state on a chip without VS.
In such a case, clip_halfz is handled by the Draw module.

radeonsi: fix incorrect index buffer max size for lowered 8-bit indices

Cc: 10.2 10.3 mesa-stable@lists.freedesktop.org
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: fix polygon mode for points and lines and point/line fill modes

Fixes piglit/polygon-mode-offset.

Cc: 10.2 10.3 mesa-stable@lists.freedesktop.org
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: fix polygon mode for points and lines and point/line fill modes

Fixes piglit/polygon-mode-offset.

Cc: 10.2 10.3 mesa-stable@lists.freedesktop.org
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: Implement sm5 UBO/sampler indexing

Caveat: Shaders using UBO/sampler indexing will
not be optimized by SB, due to SB not currently
supporting the necessary CF_INDEX_[01] index
registers.

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>

r600g: Implement sm5 interpolation functions

Requires evergreen/cayman

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>

docs: Update GL3.txt and relnotes for GL_KHR_context_flush_control

mesa: Add support for the GL_KHR_context_flush_control extension

The GL side of this extension just provides an accessor via glGetIntegerv for
the value of GL_CONTEXT_RELEASE_BEHAVIOR so it is trivial to implement. There
is a constant on the context for the value of the enum which is initialised to
GL_CONTEXT_RELEASE_BEHAVIOR_FLUSH. The extension is always enabled because it
doesn't need any driver interaction to retrieve the value.

If the value of the enum is anything but FLUSH then _mesa_make_current will
now refrain from calling _mesa_flush. This should only affect drivers that
explicitly change the enum to a non-default value.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

gles2: Update gl2ext.h to revision 28335

The main incentive to do this is to get the defines for the
GL_KHR_context_flush_control extension.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/fs: Don't set dependency hints on instructions with spilled destinations

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Make scratch write instructions use the correct execution size

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Use correct spill offsets

Different platforms require the offset to be in different units.  However,
the generator fixes all of this up for us and only requires an offset in
bytes.  Previously, we were getting this wrong all over the place.  Some
computed/used it correctly as bytes while others treated the offset as
whole registers or computed it as bytes or bytes*2 in SIMD16 mode.  This
commit cleans all this up and makes us properly treat it as bytes
everywhere.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Use the spill destination for the message header on GEN >= 7

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Don't [un]spill multiple registers at a time in SIMD8 mode

I thought this would be a clever way to make spilling less expensive.
However, it appears that the oword read/write messages we are using for
spilling ignore the execution size and assume SIMD16 whenever working with
more than one register.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Use instruction execution sizes when generating scratch reads/writes

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

egl/drm: do not crash when swapping buffers without any rendering

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

nv50: handle inverted render conditions

This enables ARB_conditional_render_inverted.

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/ir3: consider instruction neighbors in cp

Fanin (merge) nodes require it's srcs to be "adjacent" in consecutive
scalar registers.  Keep track of instruction neighbors in copy-
propagation step and avoid eliminating mov's which would cause an
instruction to need multiple distinct left and/or right neighbors.

This lets us not fall on our face when we encounter things like:

  1: MOV TEMP[2], IN[0].xyzw
  2: TEX OUT[0].xy, TEMP[2], SAMP[0], SHADOW2D
  3: MOV TEMP[2].xy, IN[0].yxzz
  4: TEX OUT[0].zw, TEMP[2], SAMP[0], SHADOW2D
  5: END

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: always mov tex coords

Always insert extra mov's for the tex coord into the fanin.  This
simplifies things a bit, and avoids a scenario where multiple sam
instructions can have mutually exclusive input's to it's fanin, for
example:

  1: TEX OUT[0].xy, IN[0].xyxx, SAMP[0], 2D
  2: TEX OUT[0].zw, IN[0].yxxx, SAMP[0], 2D

The CP pass can always remove the mov's that are not actually needed,
so better to start out with too many mov's in the front end, than not
enough.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: rename a couple debug flags

dscis -> noscis
dbypass -> nobypass

a bit more consistant w/ nobin, etc.  And IMO a bit more sensible names.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: skip virtual outputs in standalone compiler

Kills get added to the outputs list, to ensure they get scheduled.  But
they aren't *really* outputs so skip them in the header comment block.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

glx: Fix make check.

This fixes https://bugs.freedesktop.org/show_bug.cgi?id=85429.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>

mesa: Add ARB_clip_control.xml to automake.

Adding this makes 'make check' catch failures introduced from
within ARB_clip_control.xml earlier.

Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>

freedreno/ir3: standalone compiler updates for ir3test

In order to test compiler changes more easily, spit out the assembled
shader with some header information so that we can know about
inputs/outputs more easily.

See: git://people.freedesktop.org/~robclark/ir3test

In ir3test we have a big collection of tgsi shaders and reference
ir3_compiler outputs.  When making compiler changes, regenerate the
compiler outputs and feed to ir3test to compare the new vs reference
shader.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

ilo: improve blob decoding

The last few dwords were skipped if the total number of dwords was not a
multiple of 4.  Change the formatting for better readability.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>

i965: Skip recalculating URB allocations if the entry size didn't change.

We only get here if the VS/GS compiled programs change, but we can even
skip it if the VS/GS size didn't change.

Affects cairo runtime on glamor by -1.26471% +/- 0.674335% (n=234)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Standardize names and fix typos

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Silence unused parameter warning in brw_dump_ir

Just remove the parameter.  Silences:

brw_program.c: In function 'brw_dump_ir':
brw_program.c:566:33: warning: unused parameter 'brw' [-Wunused-parameter]

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Remove brwIsProgramNative

Originally I just fixed some unused parameter warnings in this
function.  However, Ken pointed out:

    "You could instead remove this driver hook.  If the dd pointer is
    NULL, arbprogram.c will return true.  I think I'd prefer that."

Way, way back in time, I think _mesa_GetProgramivARB had the opposite
behavior.  Given that it works the way it now works, I also prefer
removing the driver hook.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Silence unused parameter warning in _mesa_init_shader_program

Just remove the parameter.  Silences:

../../src/mesa/main/uniform_query.cpp:1062:1: warning: unused parameter 'ctx' [-Wunused-parameter]

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Remove context parameter from dd_function_table::NewShaderProgram

This fixes some unused parameter warnings introduced by the previous
commit.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Make _mesa_init_shader_program static

Since a couple commits ago, there is only one caller, and that caller is
in the same file.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Remove context parameter from _mesa_init_shader_program

Silences:

../../src/mesa/main/shaderobj.c: In function '_mesa_init_shader_program':
../../src/mesa/main/shaderobj.c:239:46: warning: unused parameter 'ctx' [-Wunused-parameter]

For now, this adds a couple other unused parameter warnings, but future
patches will clean those up.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl_to_tgsi: Remove st_new_shader

It was identical to the default implementation in _mesa_new_shader.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: Dave Airlie <airlied@redhat.com>

glsl_to_tgsi: Remove st_new_shader_program

It was identical to the default implementation in
_mesa_new_shader_program.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: Dave Airlie <airlied@redhat.com>

i965: Remove brw_new_shader_program

It was identical to the default implementation in
_mesa_new_shader_program.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Silence unused parameter warning in _mesa_clear_shader_program_data

Just remove the parameter.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

linker: Rely on _mesa_clear_shader_program_data to clear link information

_mesa_link_shader_program already calls _mesa_clear_shader_program_data
before calling link_shaders, so this is already done.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: Add some missing clean-up to _mesa_clear_shader_program_data

All of this is already done in link_shaders.  More clean-ups coming.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Remove prototypes for nonexistent functions

_mesa_UseShaderProgramEXT, _mesa_ActiveProgramEXT, and
_mesa_CreateShaderProgramEXT were all removed when support for
GL_EXT_separate_shader_objects was removed.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

ff_fragment_shader: Silence unused parameter warning in smear

Just remove the parameter.  Silences:

../../src/mesa/main/ff_fragment_shader.cpp:668:1: warning: unused parameter 'p' [-Wunused-parameter]

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

meta: Only use _mesa_ClipControl if the extension is supported

Fixes many piglit failures on IVB since 85edaa8.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85425
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: Mathias Fröhlich <Mathias.Froehlich@gmx.net>

docs: add news item and link release notes

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

docs: Add sha256 sums for the 10.3.2 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 95994706429e08665d1d33d248c8bcd67d40251e)

Add release notes for the 10.3.2 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 3b6a4758fa8958db4b76e6d7efccc93b12b1da06)

i965/fs: Compute q-values for register allocation manually

Previously, we were allowing the register allocation code to do the
computation for us in ra_set_finalize.  However, the runtime for this
computation is O(c^4 * g) where c is the number of classes and g is the
number of GRF registers.  However, these q-values are directly computable
based on the way we lay out our register classes so there is no need for
the aweful runtime algorithm.

We were doing ok until commit 7210583eb where we bumped the number of
register classes from 11 to 16.  While startup times don't normally matter,
this caused piglit to take 4 times as long to run on Bay Trail.  This patch
should make generating the ra_set much faster and melt the piglit run
times.

v2: Fixed a couple of bugs.  I have now verified that the same q-values are
generated both ways.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Don't interfere with too many base registers

On older GENs in SIMD16 mode, we were accidentally building too much
interference into our register classes.  Since everything is divided by 2,
the reigster allocator thinks we have 64 base registers instead of 128.
The actual GRF mapping still needs to be doubled, but as far as the ra_set
is concerned, we only have 64.  We were accidentally adding way too much
interference.

Signed-off-by: Jason Ekstrand <jason.ekstrand@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Properly precolor payload registers on GEN5 in SIMD16

For GEN6 SIMD16 mode, we have to 2-align all the registers, so we only have
the even-numbered ones.  This means that we have to divide the register
number by 2 when we precolor.  This wasn't a problem before because we were
setting up the interference between ra_node registers wrong.  This will be
fixed in the next commit.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Add another use of MAX_VGRF_SIZE

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>