ls2.git
2 years agoadd FPGA argument to DDR3SoC
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 21:01:11 +0000 (21:01 +0000)]
add FPGA argument to DDR3SoC

2 years agoadd microwatt console lib and #includes
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 20:11:35 +0000 (20:11 +0000)]
add microwatt console lib and #includes

2 years agomake cpu optional (test purposes), make bios optional,
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 13:43:55 +0000 (13:43 +0000)]
make cpu optional (test purposes), make bios optional,
start on adding SDRAM

2 years agoremove minerva cpu
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 14:20:19 +0000 (14:20 +0000)]
remove minerva cpu

2 years agodrop clock frequency to 25 mhz and disable abc9 (it fails to build)
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 14:16:18 +0000 (14:16 +0000)]
drop clock frequency to 25 mhz and disable abc9 (it fails to build)

2 years agoadd openocd load command for ecp5
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 14:15:58 +0000 (14:15 +0000)]
add openocd load command for ecp5

2 years agowildcards never ok. update comments
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 13:16:10 +0000 (13:16 +0000)]
wildcards never ok. update comments

2 years agoadd copyright notices
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 13:12:59 +0000 (13:12 +0000)]
add copyright notices

2 years agoupdate ECP5 PLL to accept parameters for setting arbitrary clock frequencies
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 12:30:20 +0000 (12:30 +0000)]
update ECP5 PLL to accept parameters for setting arbitrary clock frequencies

2 years agoadd start of README as reminder
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 01:24:15 +0000 (01:24 +0000)]
add start of README as reminder

2 years ago* add uart_pins to UART16550 peripheral so they get connected
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 01:23:13 +0000 (01:23 +0000)]
* add uart_pins to UART16550 peripheral so they get connected
* add yosys -abc9 option
* correct path to external_core_top.v

2 years ago* disable DDR3 for now
Luke Kenneth Casson Leighton [Wed, 16 Feb 2022 00:54:26 +0000 (00:54 +0000)]
* disable DDR3 for now
* reduce bootrom size
* add external_core_top.v when building for VERSA_ECP5

2 years agoconnect up stall signals (fake) for WB Classic compliance
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 20:10:05 +0000 (20:10 +0000)]
connect up stall signals (fake) for WB Classic compliance

2 years agoalternative uart wishbone mapping which just takes 8-bit data and
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 15:57:58 +0000 (15:57 +0000)]
alternative uart wishbone mapping which just takes 8-bit data and
drops it onto 32-bit bus

2 years agoattempt to do 8-bit downconvert on wishbone bus for uart,
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 15:43:30 +0000 (15:43 +0000)]
attempt to do 8-bit downconvert on wishbone bus for uart,
but it is probably actually 8-bit data aligned to 32-bit
(see soc.vhdl in microwatt)
also set CTS,DSR,RI, DCD to default values

2 years agocorrect syscon bus address to 0xC000_0000
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 15:04:58 +0000 (15:04 +0000)]
correct syscon bus address to 0xC000_0000

2 years agoadd microwatt SYSCON peripheral at 0xc000_0000
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 13:55:15 +0000 (13:55 +0000)]
add microwatt SYSCON peripheral at 0xc000_0000
this is for (Sys)tem (Con)figuration info

2 years agoincrease size of bootmem
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 01:35:25 +0000 (01:35 +0000)]
increase size of bootmem

2 years agoadd interrupt controller module, remove stall feature from CPU buses
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 00:41:59 +0000 (00:41 +0000)]
add interrupt controller module, remove stall feature from CPU buses

2 years agoFLGA_TARGET=verilator not uppercase
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 00:41:12 +0000 (00:41 +0000)]
FLGA_TARGET=verilator not uppercase

2 years agoadd external cpu
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 14:03:11 +0000 (14:03 +0000)]
add external cpu

2 years agoconvert boot rom to bootmem and get first hello_world firmware loaded
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 11:47:42 +0000 (11:47 +0000)]
convert boot rom to bootmem and get first hello_world firmware loaded

2 years agoadd IBM microwatt CC4 license and copyright notices
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 11:36:01 +0000 (11:36 +0000)]
add IBM microwatt CC4 license and copyright notices

2 years agoadd first cut of verilator simulation, over from microwatt
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 11:33:20 +0000 (11:33 +0000)]
add first cut of verilator simulation, over from microwatt

2 years agoadd verilog build option, make DDR3 PHY optional, add UART pins
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 10:34:48 +0000 (10:34 +0000)]
add verilog build option, make DDR3 PHY optional, add UART pins

2 years agoadd future sim option (needs Simulated DDR PHY)
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 15:33:58 +0000 (15:33 +0000)]
add future sim option (needs Simulated DDR PHY)

2 years agoadd build to gitignore
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:26:29 +0000 (14:26 +0000)]
add build to gitignore

2 years agorename examples to src
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:26:07 +0000 (14:26 +0000)]
rename examples to src

2 years agonot for any good reason, separate adding the uart16550 verilog source
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:25:44 +0000 (14:25 +0000)]
not for any good reason, separate adding the uart16550 verilog source

2 years agoadd MemoryMap to UART16550 (TODO, put that into UART16550 class)
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:13:51 +0000 (14:13 +0000)]
add MemoryMap to UART16550 (TODO, put that into UART16550 class)

2 years agostart adding uart16550
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:03:30 +0000 (14:03 +0000)]
start adding uart16550

2 years agoselect a firmware file
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 12:53:08 +0000 (12:53 +0000)]
select a firmware file

2 years agoallow selection of alternative FPGAs at commandline
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 12:48:51 +0000 (12:48 +0000)]
allow selection of alternative FPGAs at commandline

2 years agoadd blinky lights so we know FPGA is alive
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 12:42:14 +0000 (12:42 +0000)]
add blinky lights so we know FPGA is alive

2 years agomake firmware and cpu optional for now to get a basic compile
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 12:39:11 +0000 (12:39 +0000)]
make firmware and cpu optional for now to get a basic compile

2 years agobegin a tidyup on the example
Luke Kenneth Casson Leighton [Sat, 12 Feb 2022 20:57:05 +0000 (20:57 +0000)]
begin a tidyup on the example
core, put addresses of peripherals at the microwatt-expected addresses

2 years agoresolve imports, whitespace, add Copyright
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 12:37:39 +0000 (12:37 +0000)]
resolve imports, whitespace, add Copyright

2 years agoadd crg.py
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 12:36:33 +0000 (12:36 +0000)]
add crg.py

2 years agoupdate contributors
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 12:32:32 +0000 (12:32 +0000)]
update contributors

2 years agosort out license and headers for NLnet and NGI POINTER funded work
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 12:31:27 +0000 (12:31 +0000)]
sort out license and headers for NLnet and NGI POINTER funded work

2 years agoadd gram soc example and license and contributors
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 11:59:39 +0000 (11:59 +0000)]
add gram soc example and license and contributors

2 years agoempty first commit
Luke Kenneth Casson Leighton [Wed, 9 Feb 2022 13:24:08 +0000 (13:24 +0000)]
empty first commit