Iago Toral Quiroga [Mon, 30 May 2016 11:31:25 +0000 (13:31 +0200)]
i965/vec4: fix size_written for doubles
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Thu, 25 Aug 2016 09:49:53 +0000 (11:49 +0200)]
i965: move exec_size from fs_instruction to backend_instruction
We are going to need this in the vec4 backend too.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Samuel Iglesias Gonsálvez [Thu, 7 Jul 2016 11:35:30 +0000 (13:35 +0200)]
i965/vec4: use the new helper function to create double immediates
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Wed, 9 Mar 2016 15:37:33 +0000 (16:37 +0100)]
i965/vec4: add a helper function to create double immediates
Gen7 hardware does not support double immediates so these need
to be moved in 32-bit chunks to a regular vgrf instead. Instead
of doing this every time we need to create a DF immediate,
create a helper function that does the right thing depending
on the hardware generation.
v2 (Curro):
- Use swizzle() and writemask() helpers and make tmp const.
v3 (Iago):
- Adapt to changes in offset()
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Thu, 18 Feb 2016 08:24:16 +0000 (09:24 +0100)]
i965/vec4: fix optimize predicate for doubles
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Fri, 5 Feb 2016 09:12:57 +0000 (10:12 +0100)]
i965/vec4: implement fsign() for doubles
v2: use a MOV with a conditional_mod instead of a CMP, like we do in d2b, to skip
loading a double immediate.
v3: Fix comment (Matt)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Wed, 17 Feb 2016 12:08:47 +0000 (13:08 +0100)]
i965/vec4: implement d2b
v2 (Curro):
- Generate the flag register with a MOV with conditional_mod instead of a CMP
instruction, which has the benefit that we can skip loading a DF
0.0 constant.
- Avoid the PICK_LOW_32BIT + MOV by using the flag result and a
SEL to set the boolean result.
v3:
- Fix comment (Matt)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Wed, 17 Feb 2016 10:12:19 +0000 (11:12 +0100)]
i965/vec4: implement d2i, d2u, i2d and u2d
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Wed, 29 Jun 2016 11:08:25 +0000 (13:08 +0200)]
i965/vec4: implement HW workaround for align16 double to float conversion
From the BDW PRM, Workarounds chapter:
"DF->f format conversion for Align16 has wrong emask calculation when
source is immediate."
Notice that Broadwell and later are strictly scalar at the moment though, so
this is not really necessary.
v2: Instead of moving the immediate to a vgrf and converting from there, just
convert the double immediate to float in the compiler and move the result
to the destination (Matt)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Wed, 29 Jun 2016 11:07:35 +0000 (13:07 +0200)]
i965/vec4: add helpers for conversions to/from doubles
Use these helpers to implement d2f and f2d. We will reuse these helpers when
we implement things like d2i or i2d as well.
v2:
- Rename the helpers (Matt)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Wed, 17 Feb 2016 09:32:05 +0000 (10:32 +0100)]
i965/vec4: Rename DF to/from F generator opcodes
The opcodes are not specific for conversions to/from float since we need
the same for conversions to/from other 32-bit types. Rename the opcodes
accordingly and change the asserts to check the size of the types involved
instead.
v2:
- Rename to VEC4_OPCODE_TO_DOUBLE and VEC4_OPCODE_FROM_DOUBLE (Matt)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Mon, 15 Feb 2016 09:07:42 +0000 (10:07 +0100)]
i965/vec4: fix register allocation for 64-bit undef sources
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Fri, 12 Feb 2016 12:10:06 +0000 (13:10 +0100)]
i965/vec4: make opt_vector_float ignore doubles
The pass does not support doubles in its current form.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Fri, 12 Feb 2016 07:47:21 +0000 (08:47 +0100)]
i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations
v2: Make dst_reg_for_nir_reg() handle this for nir_register since we
want to have the correct type set before we call offset().
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Wed, 5 Oct 2016 08:54:35 +0000 (10:54 +0200)]
i965/vec4: fix indentation in get_nir_src()
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Thu, 13 Aug 2015 22:34:24 +0000 (15:34 -0700)]
i965/vec4/nir: implement double comparisons
v2:
- Added newline before if() (Matt)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Wed, 1 Jun 2016 07:57:06 +0000 (09:57 +0200)]
i965/vec4: implement double packing
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Wed, 1 Jun 2016 07:58:00 +0000 (09:58 +0200)]
i965/vec4: implement double unpacking
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Thu, 11 Feb 2016 13:19:58 +0000 (14:19 +0100)]
i965/vec4: don't copy propagate vector opcodes that operate in align1 mode
Basically, ALIGN1 mode will ignore swizzles on the input vectors so we don't
want the copy propagation pass to mess with them.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Wed, 24 Aug 2016 09:21:57 +0000 (11:21 +0200)]
i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW,HIGH}_32BIT
These align1 opcodes do partial writes of 64-bit data. The problem is that we
want to use them to write on the same register to implement packDouble2x32 and
from the point of view of DCE, since both opcodes write to the same register,
only the last one stands and decides to eliminate the first, which is
not correct, so prevent this from happening.
v2: Make a helper in vec4_instruction to know if the instruction is an
align1 partial write. This will come in handy when we implement a
simd splitting pass in a later patch.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Fri, 17 Jun 2016 10:19:35 +0000 (12:19 +0200)]
i965/vec4: add VEC4_OPCODE_SET_{LOW,HIGH}_32BIT opcodes
These opcodes will set the low/high 32-bit in each 64-bit data element
using Align1 mode. We will use this to implement packDouble2x32.
We use Align1 mode because in order to implement this in Align16 mode
we would need to use 32-bit logical swizzles (XZ for low, YW for high),
but the IR works in terms of 64-bit logical swizzles for DF operands
all the way up to codegen.
v2:
- use suboffset() instead of get_element_ud()
- no need to set the width on the dst
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Tue, 31 May 2016 08:17:37 +0000 (10:17 +0200)]
i965/vec4: add VEC4_OPCODE_PICK_{LOW,HIGH}_32BIT opcodes
These opcodes will pick the low/high 32-bit in each 64-bit data element
using Align1 mode. We will use this, for example, to do things like
unpackDouble2x32.
We use Align1 mode because in order to implement this in Align16 mode
we would need to use 32-bit logical swizzles (XZ for low, YW for high),
but the IR works in terms of 64-bit logical swizzles for DF operands
all the way up to codegen.
v2:
- use suboffset() instead of get_element_ud()
- no need to set the width on the dst
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Fri, 5 Feb 2016 09:11:48 +0000 (10:11 +0100)]
i965/vec4: add dst_null_df()
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Tue, 10 Nov 2015 09:20:25 +0000 (10:20 +0100)]
i965/vec4: We only support 32-bit integer ALU operations for now
Add asserts so we remember to address this when we enable 64-bit
integer support, as suggested by Connor and Jason.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Wed, 25 May 2016 06:21:23 +0000 (08:21 +0200)]
i965/disasm: align16 DF source regions have a width of 2
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Wed, 18 Nov 2015 13:00:58 +0000 (14:00 +0100)]
i965/vec4: set correct register regions for 32-bit and 64-bit
For 32-bit instructions we want to use <4,4,1> regions for VGRF
sources so we should really set a width of 4 (we were setting 8).
For 64-bit instructions we want to use a width of 2 because the
hardware uses 32-bit swizzles, meaning that we can only address 2
consecutive 64-bit components in a row. Also, Curro suggested that
the hardware is probably fixing the width to 2 for 64-bit instructions
anyway, so just go with that and use <2,2,1>.
v2:
- No need to explicitly set the vertical stride of 64-bit regions to 2,
brw_vecn_grf with a width of 2 will do that for us.
- No need to adjust the width of dst registers.
v3 (Ian):
- Make type_size and width const.
Signed-off-by: Connor Abbott <connor.w.abbott@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Connor Abbott [Thu, 13 Aug 2015 21:22:03 +0000 (14:22 -0700)]
i965: add brw_vecn_grf()
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Thu, 13 Aug 2015 22:56:22 +0000 (15:56 -0700)]
i965/vec4: translate d2f/f2d
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Thu, 13 Aug 2015 22:36:05 +0000 (15:36 -0700)]
i965/vec4: add double/float conversion pseudo-opcodes
These need to be emitted as align1 MOV's, since they need to have a
stride of 2 on the float register (whether src or dest) so that data
from another thread doesn't cross the middle of a SIMD8 register.
v2 (Iago):
- The float-to-double needs to align 32-bit data to 64-bit before doing the
conversion. This was doable in align16 when we tried to use an execsize
of 4, but with an execsize of 8 we would need another align1 opcode to do
that (since we need data to cross the middle of a SIMD register). Just
making the opcode handle this internally seems more practical that adding
another opcode just for this purpose and having the caller know about this
before converting.
- The double-to-float conversion produces 32-bit elements aligned to 64-bit
so we make the opcode re-pack the result to 32-bit and fit in one register,
as expected by SIMD4x2 operation. This still requires that callers reserve
two registers for the float data destination because we need to produce
64-bit aligned data first, and repack it later on the same destination
register, but it saves the need for a re-pack opcode only to achieve this
making the operation complete in a single opcode. Hopefully that is worth
the weirdness of the double register allocation...
Signed-off-by: Connor Abbott <connor.w.abbott@intel.com>
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Connor Abbott [Thu, 13 Aug 2015 21:18:04 +0000 (14:18 -0700)]
i965/vec4: add support for printing DF immediates
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Thu, 13 Aug 2015 22:30:34 +0000 (15:30 -0700)]
i965/vec4/nir: fix emitting 64-bit immediates
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Connor Abbott [Thu, 13 Aug 2015 21:35:46 +0000 (14:35 -0700)]
i965/vec4/nir: set the right type for 64-bit registers
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Wed, 25 May 2016 07:27:49 +0000 (09:27 +0200)]
i965/vec4/nir: support doubles in ALU operations
Basically, this involves considering the bit-size information to set
the appropriate type on both operands and destination.
v2 (Curro)
- Don't use two temporaries (and write one of them twice ) to obtain
the nir_alu_type.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Mon, 2 Nov 2015 05:07:27 +0000 (00:07 -0500)]
i965/vec4/nir: Add bit-size information to types
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Connor Abbott [Mon, 29 Feb 2016 11:35:05 +0000 (12:35 +0100)]
i965/vec4/nir: allocate two registers for dvec3/dvec4
v2 (Curro):
- Do not special-case for a bit-size of 64, divide the bit_size by 32
instead.
- Use DIV_ROUND_UP so we can handle sub-32-bit types.
v3 (Ian):
- Make num_regs const.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Connor Abbott [Mon, 10 Aug 2015 18:35:34 +0000 (11:35 -0700)]
i965/vec4/nir: simplify glsl_type_for_nir_alu_type()
Less duplication, one one less case to handle for doubles and support
for sized NIR types.
v2: Fix call to get_instance by swapping rows and columns params (Iago)
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Samuel Iglesias Gonsálvez [Mon, 6 Jun 2016 13:49:52 +0000 (15:49 +0200)]
i965/nir: double/dvec2 uniforms only need to be padded to a single vec4 slot
max_vector_size is used in the vec4 backend to pad out the uniform
components to match a size that is a multiple of a vec4. Double and dvec2
uniforms only require a single vec4 slot, not two.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Samuel Iglesias Gonsálvez [Fri, 23 Dec 2016 06:37:38 +0000 (07:37 +0100)]
i965/fs: fix exec_size when emitting DIM instruction
Otherwise, DIM instructions will be emitted with the default exec size
which could be 16 in some cases, that is not legal.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Suggested-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Timothy Arceri [Sun, 20 Nov 2016 13:29:29 +0000 (00:29 +1100)]
st/mesa: get Version from gl_program rather than gl_shader_program
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Mon, 7 Nov 2016 23:28:12 +0000 (10:28 +1100)]
i965: stop passing gl_shader_program to brw_compile_gs() and gen6_gs_visitor()
Instead we caan just use gl_program.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Mon, 7 Nov 2016 23:25:57 +0000 (10:25 +1100)]
i965: get InfoLog and LinkStatus via the shader program data pointer in gl_program
This removes another dependency on gl_shader_program in the codegen
functions.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Mon, 7 Nov 2016 23:05:42 +0000 (10:05 +1100)]
i965: eliminate gen6_xfb_enabled field in brw_gs_prog_data
We can just get this information from shader_info instead.
Note that passing gen6_gs_visitor() gl_program via _LinkedShaders
will go away in a later patch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Tue, 20 Dec 2016 10:37:23 +0000 (21:37 +1100)]
i965: update brw_get_shader_time_index() not to take gl_shader_program
This removes another dependency on gl_shader_program in the codegen
functions which will help allow us to use gl_program in the
CurrentProgram array rather than gl_shader_program.
Reviewed-by: Eric Anholt <eric@anholt.net>
Marek Olšák [Mon, 2 Jan 2017 22:16:48 +0000 (23:16 +0100)]
gallium/hud: fix the windows build by disabling file dumping
Kenneth Graunke [Mon, 2 Jan 2017 10:56:52 +0000 (02:56 -0800)]
glsl: Update ES 3.2 shader output restrictions.
This disallows fancy varyings in tessellation and geometry shaders,
as required by ES 3.2.
Fixes:
dEQP-GLES31.functional.tessellation.user_defined_io.negative.per_patch_array_of_structs
dEQP-GLES31.functional.tessellation.user_defined_io.negative.per_patch_structs_containing_arrays
(Not a candidate for stable branches as it only disallows things which
should be working as desktop GL allows them.)
v2: Update error messages to not say "vertex shader" (caught by Iago).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Ben Widawsky [Tue, 20 Dec 2016 14:29:05 +0000 (14:29 +0000)]
i965/miptree: Create a disable CCS flag
Cc: Chad Versace <chadversary@chromium.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Ben Widawsky [Sun, 18 Dec 2016 18:31:25 +0000 (10:31 -0800)]
i965: Replace bool aux disable with enum
As CCS buffers are passed to KMS, it becomes useful to be able to
determine exactly what type of aux buffers are disabled. This was
previously not entirely needed (though the code was a little more
confusing), however it becomes very desirable after a recent patch from
Chad:
commit
1c8be049bea786c2c054a770025976beba5b8636
Author: Chad Versace <chadversary@chromium.org>
Date: Fri Dec 9 16:18:11 2016 -0800
i965/mt: Disable aux surfaces after making miptree shareable
The next patch will handle CCS and get rid of no_ccs.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Edmondo Tommasina [Wed, 21 Dec 2016 21:58:14 +0000 (22:58 +0100)]
docs: document GALLIUM_HUD_DUMP_DIR envvar
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edmondo Tommasina [Wed, 21 Dec 2016 21:58:13 +0000 (22:58 +0100)]
gallium/hud: set filedescriptor for fps graph
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edmondo Tommasina [Wed, 21 Dec 2016 21:58:12 +0000 (22:58 +0100)]
gallium/hud: set filedescriptor for cpu graph
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edmondo Tommasina [Wed, 21 Dec 2016 21:58:11 +0000 (22:58 +0100)]
gallium/hud: move file initialization to a function
The function will be used later to create the filedescriptor
for other metrics.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edmondo Tommasina [Wed, 21 Dec 2016 21:58:09 +0000 (22:58 +0100)]
gallium/hud: dump hud_driver_query values to files
Dump values for every selected data source in GALLIUM_HUD.
Every data source has its own file and the filename is
equal to the data source identifier.
Set GALLIUM_HUD_DUMP_DIR to dump values to files in this directory.
No values are dumped if the environment variable is not set, the
directory doesn't exist or the user doesn't have write access.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Fri, 30 Dec 2016 05:39:30 +0000 (00:39 -0500)]
anv,radv: disable StorageImageWriteWithoutFormat for now
The SPIR-V capability isn't even marked as enabled, and there are no
tests in Vulkan-CTS. Per Jason Ekstrand, this won't work in anv as such
write-only surfaces require additional setup which is currently not
performed.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Fri, 30 Dec 2016 23:35:02 +0000 (15:35 -0800)]
i965: Avoid NULL pointer dereference when transform feedback is off.
upload_3dstate_streamout can be called when there's no currently bound
transform feedback object. In this case, we get the default object,
which has a NULL shader (previously gl_shader_program, now gl_program).
The old code did something sketchy, but which worked:
const struct gl_transform_feedback_info *linked_xfb_info =
&xfb_obj->shader_program->LinkedTransformFeedback;
Here, if shader_program is NULL, this would be a bogus pointer of 0x60.
But we never actually dereferenced it, so it worked out.
With Timothy's recent reworks, we actually end up dereferencing
xfb_obj->program along the way, which crashes since it's NULL.
The solution is to move this pointer initialization into the "active"
block, where we know it actually exists and won't be bogus.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99231
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Timothy Arceri [Tue, 20 Dec 2016 10:37:25 +0000 (21:37 +1100)]
glsl/mesa: add reference to gl_shader_program_data from gl_program
We also add the stubs for the standalone compiler in this change.
By adding a reference here we can now refactor some code to use
gl_program where we were previously awkwardly using gl_shader_program.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Fri, 30 Dec 2016 20:45:35 +0000 (07:45 +1100)]
mesa: make union in gl_program a struct and add FIXME
i915 is mixing the use of these fields, for now change this to a
struct and add a FIXME.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99229
Jason Ekstrand [Sat, 24 Dec 2016 19:21:57 +0000 (11:21 -0800)]
i965/peephole_ffma: Use nir_builder
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sat, 24 Dec 2016 19:03:01 +0000 (11:03 -0800)]
nir/split_var_copies: Use a nir_shader rather than a void *mem_ctx
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sat, 24 Dec 2016 18:58:17 +0000 (10:58 -0800)]
nir/opt_peephole_select: Pass around the actual nir_shader
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sat, 24 Dec 2016 18:39:19 +0000 (10:39 -0800)]
nir/conditional_if: Properly use the builder
We were passing around a void *mem_ctx and using that to initialize the
builder which was wrong since that pointed to ralloc_parent(impl) which
is the shader but the builder is supposed to be initialized with the
nir_function_impl.
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sat, 24 Dec 2016 18:34:33 +0000 (10:34 -0800)]
nir/lower_var_copies: Use a shader rather than a void *mem_ctx
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sat, 24 Dec 2016 18:24:29 +0000 (10:24 -0800)]
nir/lower_io: Use the builder instead of carrying a mem_ctx
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sat, 24 Dec 2016 18:14:48 +0000 (10:14 -0800)]
nir/from_ssa: Use nir_builder for emit_copy
This lets us get rid of the void *mem_ctx parameter and make things a
bit more type safe.
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sat, 24 Dec 2016 17:42:34 +0000 (09:42 -0800)]
nir: Make nir_copy_deref follow the "clone" pattern
We rename it to nir_deref_clone, re-order the sources to match the other
clone functions, and expose nir_deref_var_clone. This past part, in
particular, lets us get rid of quite a few lines since we no longer have
to call nir_copy_deref and wrap it in deref_as_var.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Rob Clark [Mon, 28 Nov 2016 21:02:31 +0000 (16:02 -0500)]
freedreno/ir3: rework varying slots (maybe??)
See:
dEQP-GLES2.functional.shaders.swizzles.vector_swizzles.mediump_vec2_yyyy_fragment
if we only access (in FS) varying.y then it ends up in slot zero.. I'm
not sure the hw likes that..
Signed-off-by: Rob Clark <robdclark@gmail.com>
Ilia Mirkin [Fri, 30 Dec 2016 01:59:12 +0000 (20:59 -0500)]
spirv: always expose SpvCapabilityStorageImageExtendedFormats
I forgot to do this in commit
76b97d544e ("anv: enable storage image
extended formats"). Since both drivers support this now, no need for the
conditional enable.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Sun, 27 Nov 2016 20:45:54 +0000 (15:45 -0500)]
anv: add support for extended texture gather
Now that the SPIR-V -> NIR translation is in place, no additional logic
is required.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Dave Airlie [Thu, 29 Dec 2016 23:11:19 +0000 (23:11 +0000)]
radv: only allow cmask/dcc in color optimal.
I had this on transfers due to the clear color cmd, but
it seems like that path shouldn't get fast clears.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 29 Dec 2016 22:46:27 +0000 (22:46 +0000)]
radv: only allow cmask/dcc on exclusive or concurrent with graphics queue.
Otherwise we don't get the barriers to flush dcc etc.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Wed, 14 Dec 2016 05:00:34 +0000 (21:00 -0800)]
nir: Rewrite lower_regs_to_ssa to use the phi builder
This keeps some of Connor's original code. However, while I was at it,
I updated this very old pass to a bit more modern NIR.
Jason Ekstrand [Thu, 15 Dec 2016 04:25:51 +0000 (20:25 -0800)]
nir/phi-builder: Set the value in the block when creating a phi
After we figure out the value that we are going to return, we have a
loop that walks up the dominance tree and sets the value in each of the
blocks that doesn't have one yet. In the case of the phi, the def is
set to NEEDS_PHI not NULL, so the last one where the phi node actually
goes never gets filled out. This can lead to duplicating the phi node
unnecessarily.
Jason Ekstrand [Wed, 14 Dec 2016 04:54:38 +0000 (20:54 -0800)]
nir: Add foreach_register helper macros
Jason Ekstrand [Wed, 14 Dec 2016 02:19:42 +0000 (18:19 -0800)]
nir: Rename convert_to_ssa lower_regs_to_ssa
This matches the naming of nir_lower_vars_to_ssa, the other to-SSA pass.
Timothy Arceri [Fri, 4 Nov 2016 02:51:59 +0000 (13:51 +1100)]
mesa/glsl/i965: remove Driver.NewShader()
After removing brw_shader in the previous commit this is no longer
needed.
V2: remove use in src/compiler/glsl/test_optpass.cpp
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Fri, 4 Nov 2016 02:37:21 +0000 (13:37 +1100)]
i965: move compiled_once flag to brw_program
This allows us to delete brw_shader and removes the last use of
gl_linked_shader in the codegen paths.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Thu, 3 Nov 2016 23:10:19 +0000 (10:10 +1100)]
mesa/glsl: move BlendSupport bitfield to gl_program
This will let us to make _CurrentFragmentProgram a gl_program pointer
allowing for simpilifications to be made.
We also need to add a field to gl_shader to hold it during parsing.
In gl_program we put it inside a union in anticipation of moving
more fields here that can be only fs or vertex stage fields.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Thu, 3 Nov 2016 03:35:08 +0000 (14:35 +1100)]
mesa: store gl_program in gl_transform_feedback_object rather than gl_shader_program
This will allow us to make the CurrentProgram array store gl_program which allows
us to do a bunch of simplifications.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Thu, 3 Nov 2016 05:00:37 +0000 (16:00 +1100)]
mesa/glsl: move LinkedTransformFeedback from gl_shader_program to gl_program
This will help allow us to store gl_program in the CurrentProgram array rather
than gl_shader_program which will allow a bunch of simplifications.
Note that we make LinkedTransformFeedback a pointer so we don't waste
memory creating a struct for each stage. We also store a pointer to
the gl_program that will contain the pointer in gl_shader_program so
we can get easy access to the correct stage.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Tue, 8 Nov 2016 09:59:25 +0000 (20:59 +1100)]
i965: get LinkedTransformFeedback from gl_transform_feedback_object
We have already set the gl_shader_program pointer to the correct
shader program in _mesa_BeginTransformFeedback() so use it.
This is more consistent with how we do it for gen7.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Mon, 31 Oct 2016 11:08:24 +0000 (22:08 +1100)]
mesa: move _Used to gl_program
We no longer need to initialise it because gl_program is never reused.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Mon, 31 Oct 2016 11:06:37 +0000 (22:06 +1100)]
mesa/compiler: add local_size_variable to shader_info
This will be used in api_validate.c in a following patch when we
switch to using gl_program pointers for the pipelines CurrentProgram
array.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Mon, 31 Oct 2016 10:51:40 +0000 (21:51 +1100)]
mesa: pass gl_program to _mesa_append_uniforms_to_file()
This now contains everything we need.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Mon, 31 Oct 2016 08:35:49 +0000 (19:35 +1100)]
glsl/mesa: set separate_shader directly in shader_info
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Wed, 28 Dec 2016 21:56:43 +0000 (08:56 +1100)]
mesa/glsl: move subroutine metadata to gl_program
This will allow us to store gl_program rather than gl_shader_program
as the current program perstage which allows us to simplify code
that makes use of the CurrentProgram list.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Mon, 31 Oct 2016 08:57:57 +0000 (19:57 +1100)]
mesa/compiler: add stage to shader_info
This will allow us to simplify the current program logic for SSO.
Also since we aim to detach shader_info from nir_shader this will come
in handy avoiding passing nir_shader around just to keep track of
the stage we are dealing with.
V2: set stage for arb asm programs also.
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Tue, 27 Dec 2016 21:52:54 +0000 (13:52 -0800)]
vc4: Rework scheduling of thread switch to cut one more NOP.
Jonas's patch got us most of the benefit of scheduling instructions into
the delay slots of thread switch, but if there had been nothing to pair
the thrsw with, it would move the thrsw up and leave a NOP where the thrsw
was.
Instead, don't pair anything with thrsw through the normal scheduling
path, and have a separate helper function that inserts the thrsw earlier
if possible and inserts any necessary NOPs.
total instructions in shared programs: 93027 -> 92643 (-0.41%)
instructions in affected programs: 14952 -> 14568 (-2.57%)
Jonas Pfeil [Sun, 20 Nov 2016 19:45:13 +0000 (20:45 +0100)]
vc4: Fill thread switching delay slots
Scan for instructions without a signal set in front of the switching
instruction and move the signal up there.
shader-db results:
total instructions in shared programs: 94494 -> 93027 (-1.55%)
instructions in affected programs: 23545 -> 22078 (-6.23%)
v2: Fix re-emitting of the instruction in the loop trying to emit NOPs,
drop a scheduling change from branch delay slots. (by anholt)
Signed-off-by: Jonas Pfeil <pfeiljonas@gmx.de>
Eric Anholt [Tue, 27 Dec 2016 20:29:09 +0000 (12:29 -0800)]
vc4: Enable NIR-based loop unrolling.
This successfully unrolls a new shader in GLB2.7, which also gets that
shader to successfully compile in multithreaded mode.
Timothy Arceri [Thu, 29 Dec 2016 02:18:59 +0000 (13:18 +1100)]
nir: stop gcc warning about uninitialised variables
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Tue, 27 Dec 2016 23:28:05 +0000 (23:28 +0000)]
radv: denote support for extended storage image formats.
I'm sure anv has support for these as well, but this is just
a first use of the interface to allow different supported spir-v
features.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 27 Dec 2016 23:27:14 +0000 (23:27 +0000)]
spirv: add interface for drivers to define support extensions.
I expect over time the struct contents will change as all
drivers support stuff etc, but for now this should be a good
starting point.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Chad Versace [Tue, 27 Dec 2016 22:26:24 +0000 (14:26 -0800)]
mesa/shaderobj: Fix races on refcounts
Use atomic ops when updating gl_shader::RefCount.
Fixes intermittent failures and crashes in
'dEQP-EGL.functional.sharing.gles2.multithread.*'.
All tests in that group now pass except
'dEQP-EGL.functional.sharing.gles2.multithread.simple_egl_server_sync.textures.copyteximage2d_texsubimage2d_render'.
Tested with:
mesa: branch 'master' at
d6545f2
deqp: branch 'nougat-cts-dev' at
4acf725 with additional local fixes
DEQP_TARGET: x11_egl
hw: Intel Broadwell 0x1616
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99085
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Cc: Mark Janes <mark.a.janes@intel.com>
Cc: Haixia Shi <hshi@chromium.org>
Rob Clark [Mon, 26 Dec 2016 19:16:57 +0000 (14:16 -0500)]
freedreno/ir3: fix linkage::var size
It should actually be 32 for a4xx/a5xx.. we still only advertise 16 but
for a5xx the linkage map includes position/psize.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 25 Dec 2016 18:16:51 +0000 (13:16 -0500)]
freedreno/ir3: treat clipvertex like a normal varying
We need this in case it is streamed out. Not sure why we were treating
it specially before. Having it as a VS out is harmless if FS doesn't
have a matching input.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 24 Dec 2016 19:44:26 +0000 (14:44 -0500)]
freedreno/a5xx: transform-feedback support
We'll need to revisit when adding hw binning pass support, whether we
can still do this in main draw step, as we do w/ a3xx/a4xx, or if we
needed to move it to the binning stage.
Still some failing piglits but most tests pass and the common cases seem
to work.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 24 Dec 2016 16:57:35 +0000 (11:57 -0500)]
freedreno: update generated headers
Pull in a5xx streamout related regs. Also fixes a couple incorrect
register definitions.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 24 Dec 2016 00:19:01 +0000 (19:19 -0500)]
freedreno/ir3: UBO support for 64b GPUs (a5xx)
Update address calculation to support 64b addresses.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 22 Dec 2016 03:43:52 +0000 (22:43 -0500)]
freedreno/ir3: rework location of driver constants
Rework how we lay out driver constants (driver-params, UBO/TFBO buffer
addresses, immediates) for more flexibility. For a5xx+ we need to deal
with the fact that gpu ptrs are 64b instead of 32b, which makes the
fixed offset scheme not work so well. While we are dealing with that
we might also make the layout more dynamic to account for varying # of
UBOs, etc.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 22 Dec 2016 03:47:42 +0000 (22:47 -0500)]
freedreno/a5xx: fix emit for bo addresses
Reloc for the buffer address is two dwords on 64b devices (a5xx+)
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 6 Dec 2016 18:32:31 +0000 (13:32 -0500)]
freedreno/a5xx: texture layout
Seems to be imilar to a4xx, and sampler state "array-pitch" needs
to be aligned to page size.
Signed-off-by: Rob Clark <robdclark@gmail.com>