i965/gen8: Use the generic ISL-based path for texture surfaces

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/state: Add generic surface update functions based on ISL

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/surface_state: Rename brw_update to gen4_update

We're about to add generic versions which work across gens and those should
have the brw name.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/state: Use ISL for emitting image surfaces

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/blorp: Use a generic ISL path for texture surfaces on gen8

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/state: Add a helper for emitting a surface state using isl

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/blorp: Use the generic ISL path for texture surfaces on gen6

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen6

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/blorp: Use the generic ISL path for texture surfaces on gen7

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen7

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen8-9

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/blorp: Add a generic ISL-based surface state emit path

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/miptree: Add a helper for getting the aux isl_surf from a miptree

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/miptree: Add a helper for getting the ISL clear color from a miptree

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/miptree: Add a helper for getting an isl_surf from a miptree

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965: Add an isl_device to the brw_context

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>

isl/state: Add support for OffsetX/Y in surface state

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Add support for filling out surface states all the way back to gen4

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Add an ISL_DEV_IS_G4X macro

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>

genxml: Add macros and #includes for gens 4-6

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>

genxml: Make X/Y Offset field of SURFACE_STATE a uint

THe offset type has special implications that it's intended to be some form
of aligned memory address.  These assumptions allow it to handle the case
where there is some alignment requirement on the offset and the bottom bits
are used for other things.  However, the offsets in the surface state field
are really just unsigned integers.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>

genxml: Add enough XML for gens 4, 4.5, and 5 to get SURFACE_STATE

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Chad Versace <chad.versace@intel.com>

isl/state: Divide the aux qpitch by 4

The field is in multiples of 4 like regular QPitch.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Fix the bs assertion in isl_tiling_get_info

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>

anv: Handle VK_WHOLE_SIZE properly for buffer views

The old calculation, which used view->offset, encorporated buffer->offset
into the size calculation where it doesn't belong.  This meant that, if
buffer->offset > buffer->size, you would always get a negative size.  This
fixes 170 dEQP-VK.renderpass.attachment.* Vulkan CTS tests on Haswell.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

anv: Add an align_down_npot_u32 helper

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

anv: Enable independentBlend on gen7

We can totally do it, we were just only setting up one BLEND_STATE and, now
that the code is unified with gen8, we should be handling it correctly.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

anv/pipeline: Unify blend state setup between gen7 and gen8

This fixes all 674 broken dEQP-VK.pipeline.blend Vulkan CTS tests on
Haswell.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

genxml: Make gen6-7 blending look more like gen8

This renames BLEND_STATE to BLEND_STATE_ENTRY and adds an new struct
BLEND_STATE which is just an array of 8 BLEND_STATE_ENTRYs.  This will make
it much easier to write gen-agnostic blend handling code.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

vc4: Speed up glGenerateMipmaps by avoiding shadow baselevel.

To support general GL_TEXTURE_BASE_LEVEL we have to copy to a temporary
miptree.  However, if a single level is being selected, we can use the
existing miptree and force all the sampling to be from that particular
level.

This avoids a ton of software fallbacks in glGenerateMipmaps(), which uses
base levels in the blit implementation in gallium.  Improves "glmark2 -b
terrain" from 2 fps to 3 (perhaps some more precision would be useful?),
and cuts its CPU usage during the benchmarking from ~30% to ~10% (total
CPU time from 8.8s to 7.6s).

vc4: Drop VC4_DIRTY_TEXSTATE in favor of the per-stage flags.

The compiler uses the per-stage flags already, so it didn't need this.
vc4_uniforms was using it, so just replace it with both of the stage flags
for now.

vc4: Remove dead dirty_samplers field.

We use a big VC4_DIRTY_FRAGTEX/VC4_DIRTY_VERTEX on the stage, instead.

vc4: Turn on control flow support in the simulator environment.

We can't merge the non-simulator support until we merge the kernel side and
get a new libdrm release.

mesa: handle numLevels, numSamples in _mesa_test_proxy_teximage()

If numSamples > 0, we can compute the size of the whole mipmapped texture.
That's the case for glTexStorage(GL_PROXY_TEXTURE_x).

Also, multiply the texture size by numSamples for MSAA textures.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

mesa: add proxy texture targets in _mesa_next_mipmap_level_size()

So we can use it for computing size of proxy textures.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

mesa: add numLevels, numSamples to Driver.TestProxyTexImage()

So that the function can work properly with glTexStorage(), where we know
how many mipmap levels there are.  And so we can compute storage for MSAA
textures.

Also, remove the obsolete texture border parameter.

A subsequent patch will update _mesa_test_proxy_teximage() to use these
new parameters.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

mesa: use _mesa_clear_texture_image() in clear_texture_fields()

This avoids a failed assert(img->_BaseFormat != -1) in
init_teximage_fields_ms() because the internalFormat argument is GL_NONE.
This was hit when using glTexStorage() to do a proxy texture test.

Fixes a failure with the updated Piglit tex3d-maxsize test.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

svga: avoid ubinding render targets that have already been unbound

Fixed the remaining redundant SetRenderTargets command emission.

Tested with lightsMark2008, Heaven, mtt piglit, glretrace, conform.

Reviewed-by: Brian Paul <brianp@vmware.com>

svga: dump code for GenMips.

Reviewed-by: Brian Paul <brianp@vmware.com>

Disable use of weak in threads_posix.h on Cygwin

Weak doesn't work the same on PE/COFF as on ELF, they are only weak
references.  Specifically, since nothing else pulls in the object which
contains pthread_mutexattr_init() (and coming from the C library, that is
the only thing that object contains), means that it ends up as 0

Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>

configure: Don't require pthread-stubs on Cygwin

Commit 1f4869a2 unconditionally requires pthread-stubs.  Unfortunately, the
cleverness that pthread-stubs is doesn't work with PE/COFF, and historically
Cygwin doesn't have a pthread-stubs.pc.

Don't require pthread-stubs on Cygwin.

Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>

Use correct names for dlopen()ed files on Cygwin

Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
Reviewed-by: Jon Turney <jon.turney@dronecode.org.uk>

configure: Define _GNU_SOURCE for Cygwin as well

Cygwin headers are now a bit more correct in handling feature test macros,
so use _GNU_SOURCE when building for Cygwin, as well.

(Notwithstanding f381c27c, we should probably have always been using
_GNU_SOURCE, since asprintf() is used by mesa in places)

Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
Reviewed-by: Jon Turney <jon.turney@dronecode.org.uk>

Revert "isl: Don't filter tiling flags if a specific tiling bit is set"

This reverts commit 091f1da902c71ac8d3d27b325a118e2f683f1ae5 .

Although a user may specify a specfic tiling bit, ISL should still
prevent incompatible tiling/surface combinations.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

anv/blit2d: Copy with stencil sources when needed

In the next patch, ISL will unconditionally perform verification of a
surface's tiling and usage. Since it will require that w-tiled images
be stencil buffers, create a stencil surface to copy from a
w-tiled/stencil surface.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/image: Fix initialization of the ISL tiling

If an internal user creates an image with Vulkan tiling VK_IMAGE_TILING_OPTIMAL
and an ISL tiling that isn't set, ISL will fail to create the image as
anv_image_create_info::isl_tiling_flags will be an invalid value.

Correct this by making anv_image_create_info::isl_tiling_flags an opt-in,
filtering bitmask, that allows the caller to specify which ISL tilings are
acceptable, but not contradictory to the Vulkan tiling.

Opt-out of filtering for vkCreateImage.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

isl: Fix isl_tiling_is_any_y()

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/device: Fix max buffer range limits

Set limits that are consistent with ISL's assertions in
isl_genX(buffer_fill_state_s)() and Anvil's format-DescriptorType
mapping in anv_isl_format_for_descriptor_type().

Fixes the following new crucible tests:
* stress.limits.buffer-update.range.uniform
* stress.limits.buffer-update.range.storage

These tests are in this patch: https://patchwork.freedesktop.org/patch/98726/

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

isl: Fix assert on raw buffer surface state size

See inline PRM reference.

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/cmd_buffer: Simplify range member assignment

A ternary is clearer because the range member is assigned one of two values
dependant on one condition.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/cmd_buffer: Remove unused variable

This became unused due to commit 612e35b2c65c99773b73e53d0e6fd112b1a7431f .

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/descriptor_set: Fix binding partly undefined descriptor sets

Section 13.2.3. of the Vulkan spec requires that implementations be able to
bind sparsely-defined Descriptor Sets without any errors or exceptions.

When binding a descriptor set that contains a dynamic buffer binding/descriptor,
the driver attempts to dereference the descriptor's buffer_view field if it is
non-NULL. It currently segfaults on undefined descriptors as this field is never
zero-initialized. Zero undefined descriptors to avoid segfaulting. This
solution was suggested by Jason Ekstrand.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96850
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

svga: handle mismatched number of samplers, sampler views

in svga_init_shader_key_common().  Since the CSO module only tracks
sampler views for fragment shaders, the number of samplers and sampler
views can be mismatched for other types of shaders.  This situation
triggered an assertion in Chrome with maps.google.com

This patch adds defensive code to handle that situation.

Fixes VMware bug 1694027
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

st/omx/enc: check uninitialized list from task release

The uninitialized list should be checked and returned.

Thank Julien for the notification and suggested fix.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

nv50/ir: add missing string for SV_WORK_DIM

Fixes: 2aa1197 ("nouveau: Add support for SV_WORK_DIM")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>

Revert "radeon/llvm: Use alloca instructions for larger arrays"

This reverts commit 513fccdfb68e6a71180e21827f071617c93fd09b.

Bioshock Infinite hangs with that.

r600,compute: Reserve vtx 3 for kernel arguments

Using vtx 0 does not work for dynamic offsets.

v2: add explanatory comment

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

radeon/uvd: fail to create a decoder if RUVD_MSG_CREATE submission fails

This is the bare minimum for reporting the error to the user.

Reviewed-by: Christian König <christian.koenig@amd.com>

winsys/amdgpu: return an error on IB submission failures

Reviewed-by: Christian König <christian.koenig@amd.com>

gallium/radeon: add a return value to cs_flush

Required by our UVD code.

Reviewed-by: Christian König <christian.koenig@amd.com>

glsl/types: Use _mesa_hash_data for hashing function types

This is way better than the stupid string approach especially since you
could overflow the string.  Again, I thought I had something better at one
point but it obviously got lost.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

glsl/types: Fix function type comparison function

It was returning true if the function types have different lengths rather
than false.  This was new with the SPIR-V to NIR pass and I thought I'd
fixed it a while ago but it may have gotten lost in rebasing somewhere.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

freedreno/a4xx: Fix sign compare warnings

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a3xx: Fix sign compare warnings

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a2xx: Fix sign compare warnings

Signed-off-by: Rob Clark <robdclark@gmail.com>

radeon/vce: handle newly added parameters

Replace the previous hardcoded value with newly defined parameters

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/omx: assign previous values to new structure

Assign previously hardcoded values for OMX to newly defined
structure. As a result, OMX behaviour will not change at all.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

vl: add parameters for VAAPI encode

Allow to specify more parameters in the encoding interface
which previously just hardcoded in the encoder

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/mesa: fix reference counting bug in st_vdpau

Otherwise we leak the resources created for the DMA-buf descriptors.

Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Tested-and-Reviewed by: Leo Liu <leo.liu@amd.com>
Ack-by: Tom St Denis <tom.stdenis@amd.com>

vc4: Emit resets of the uniform stream at the starts of blocks.

If a block might be entered from multiple locations, then the uniform
stream will (probably) be at different points, and we need to make sure
that it's pointing where we expect it to be.  The kernel also enforces
that any block reading a uniform resets uniforms, to prevent reading
outside of the uniform stream by using looping.

vc4: Add support for scheduling of branch instructions.

For now we don't fill the delay slots, and instead just drop in NOPs.

vc4: Move the QPU instructions to schedule into each block.

We'll want to schedule them individually, to handle delay slots.

vc4: Disable vc4_opt_vpm in the presence of control flow.

It's a really valuable pass currently, but it will be a mess to rewrite
for control flow.  For now, just disable it if we have multiple blocks
present.

vc4: Convert vc4_opt_dead_code to work in the presence of control flow.

With control flow, we can't be sure that we'll see the uses of a variable
before its def as we walk backwards.  Given that NIR is eliminating our
long chains of dead code, a simple solution for now seems fine.

This slightly changes the order of some optimizations, and so an opt_vpm
happens before opt_dce, causing 3 dead MOVs to be turned into dead FMAXes
in Minecraft:

instructions in affected programs:     52 -> 54 (3.85%)

vc4: Update copy propagation for control flow.

Previously, we could assume that a MOV from a temp was always an available
copy, because all temps were SSA in NIR, and their non-SSA state in QIR
was just due to the fact that they were from a bcsel or pack_unorm_4x8, so
we could use the current value of the temp after that series of QIR
instructions to define it.

However, this is no longer the case with control flow.  Instead, we track
a new array of MOVs defined within the block that haven't had their source
or dest killed yet, and use that primarily.  We fall back to looking
through the QIR defs array to handle across-block MOVs, but now require
that copies from the SSA defs have an SSA src as well.

i965/fs: emit DIM instruction to load 64-bit immediates in HSW

v2 (Matt):
- Use brw_imm_df() as source argument of DIM instruction.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/eu: set DF imm value to the source of DIM

According to HSW's PRM, vol02b, the DIM instruction has the following
restriction:

"Restriction : src0 must be immediate. src0 must specify the :f (F, Float)
type encoding but is an immediate 64-bit DF (Double Float) value. dst
must have type DF."

This commit allows to upload the immediate 64-bit DF value to the source
of a DIM instruction even when it is of float type encoding.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: enable the emission of the DIM instruction

v2 (Matt):
- Take a DF source argument for the DIM instruction emission
in the visitors.
- Indentation.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

anv: Add a stub for CmdCopyQueryPoolResults on Ivy Bridge

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

i965: fix compiler warnings for 32bit build

Reviewed-by: Matt Turner <mattst88@gmail.com>

Revert "gallium: Force blend color to 16-byte alignment"

This reverts commit d8d6091a846ac2a40a011d512d6d57f6c8442e6a.

Heap allocations may be only 8-byte aligned on 32-bit system, and so having
members with 16-byte alignment (such as in the case where pipe_blend_color is
embedded in radeonsi's si_context) is undefined behavior which indeed causes
crashes when compiled with gcc -O3.

Cc: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96835
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Acked-by: Chuck Atkins <chuck.atkins@kitware.com>

isl/state: Add support for handling auxiliary surfaces

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Add an auxiliary surface usage enum

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Add support for color control surfaces

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Add support for multisample compression surfaces

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Add support for HiZ surfaces

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Kill off isl_format_layout::bs

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Take bpb rather than bs in tiling_get_info

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Use bpb in a few places where it's more natural than bs

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Use bpb for determining YUV image padding

When we initially dropped bpb in favor of bs, we accidentally didn't change
this one line properly.  This brings it back to what it should be.

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Bring back isl_format_layout::bpb

A while ago we got rid of the bits-per-block because we thought we didn't
need it.  We're about to introduce some very useful 1 and 2-bit formats so
we really should be able to handle them again.

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Change the physical size of a W-tile to 128x32

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Rework the way we define tile sizes.

This is based on a very long set of discussions between Chad and myself
about how we should properly represent HiZ and CCS buffers.  The end result
of that discussion was that a tiling actually has two different sizes, a
logical size in elements, and a physical size in bytes and rows.  This
commit reworks ISL's pitch and size calculations to work in terms of these
two sizes.

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Rework the way we handle surface padding

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Use ARRAY_PITCH_SPAN_FULL for depth/stencil surfaces on gen7

We helpfully inserted a PRM quotation about how we need to use
ARRAY_PITCH_SPAN_FULL and then set it to COMPACT.  Oops...

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Stop multiplying height by block size

The row pitch already specifies the size of a row of elements.
Multiplying by the block height simply causes us to allocate as muc as 12
times more memory than needed for compressed textures.

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Get rid of tiling_get_extent

It was unused

Reviewed-by: Chad Versace <chad.versace@intel.com>

nir/spirv: Don't multiply the push constant block size by 4

I have no idea why we were multiplying by 4 before.  The offsets we get
from SPIR-V are in bytes and so is nir->num_uniforms so there's no need to
do any adjustment whatsoever.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

anv/pipeline: Assert that the number of uniforms from NIR fits

radeonsi: report accurate SGPR and VGPR spills

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>